TWI859822B - Chip packaging structure, manufacturing method, and electronic equipment - Google Patents

Abstract

A chip packaging structure, a manufacturing method, and an electronic equipment. The chip packaging structure includes a packaging substrate, a first chip, and a first packaging layer. The packaging substrate includes a first substrate and a second substrate. The first substrate includes a first dielectric layer and a first wiring layer disposed on a surface of the first dielectric layer. The second substrate includes a second dielectric layer covering a surface of the first wiring layer facing away from the first dielectric layer, and a second wiring layer disposed on a surface of the second dielectric layer facing away from the first wiring layer. The second wiring layer includes an input pad and an output pad. The second substrate defines an opening penetrating the second dielectric layer and the second wiring layer and exposing a part of the second wiring layer. The first chip is arranged in the opening and is electrically connected to the first wiring layer. The first packaging layer infills the opening and encapsulates the first chip.

Description

Chip packaging structure, manufacturing method thereof and electronic equipment

This application relates to the field of electronic technology, and in particular to a chip packaging structure, a method for manufacturing a chip packaging structure, and an electronic device including a chip packaging structure.

With the development of electronic technology, users have higher and higher requirements for the performance of electronic equipment, which has led to an increase in the number of transistors in electronic equipment, which requires the chip size to be larger and larger. However, as electronic equipment continues to develop towards integration and ultra-thinness, the chips in electronic equipment have to develop towards miniaturization.

In view of this, it is necessary to provide a chip packaging structure that is conducive to miniaturization, a manufacturing method thereof, and an electronic device.

The first aspect of the present application provides a chip packaging structure, including a packaging substrate, a first chip and a first packaging layer. The packaging substrate includes a first substrate and a second substrate. The first substrate includes a first dielectric layer and a first circuit layer disposed on the surface of the first dielectric layer. The second substrate includes a second dielectric layer covering the surface of the first circuit layer away from the first dielectric layer and a second circuit layer disposed on the surface of the second dielectric layer away from the first circuit layer, and the second circuit layer includes an input pad and an output pad. The second substrate is provided with an opening that passes through the second dielectric layer and the second circuit layer and exposes a portion of the second circuit layer. The first chip is disposed in the opening and electrically connected to the first circuit layer. The first packaging layer fills the opening and covers the first chip.

In some embodiments, the chip package structure further includes a metal layer, which covers the surface of the first dielectric layer facing away from the first circuit layer.

In some embodiments, the chip packaging structure further includes a first solder mask layer, which is disposed on the surface of the second circuit layer away from the second dielectric layer and exposes the input pad and the output pad.

In some embodiments, the surface of the first solder mask layer facing away from the second circuit layer is flush with the surface of the first packaging layer exposed in the opening.

In some embodiments, the chip packaging structure further includes a third circuit layer, a second chip and a second packaging layer, the third circuit layer is disposed on a surface of the first dielectric layer away from the first circuit layer, the second chip is electrically connected to the third circuit layer, and the second packaging layer covers the second chip.

In some embodiments, the chip packaging structure further includes a second solder mask layer, which is disposed on a surface of the third circuit layer away from the first dielectric layer and exposes a portion of the third circuit layer, and a second packaging layer is disposed on a surface of the second solder mask layer away from the first dielectric layer.

The second aspect of this application provides an electronic device, comprising any of the above-mentioned chip packaging structures and a motherboard, wherein the motherboard is disposed on one side of the chip packaging structure and is electrically connected to the input pad and the output pad.

The third aspect of the present application provides a method for manufacturing a chip packaging structure, comprising the following steps: providing a substrate, the substrate comprising a base layer and two metal layers disposed on opposite sides of the base layer; pressing two first substrates on two surfaces of the substrate, the first substrate comprising a first dielectric layer connected to the metal layer and a first conductor layer disposed on a surface of the first dielectric layer away from the first dielectric layer; processing the first conductor layer to form a first circuit layer, the first circuit layer comprising a plurality of first connection pads disposed at intervals; forming a nickel layer covering the plurality of first connection pads; and forming a nickel layer on a surface of the first circuit layer away from the first dielectric layer. Pressing a second substrate, the second substrate including a second dielectric layer covering the nickel layer and the first circuit layer and a second conductor layer disposed on the surface of the second dielectric layer away from the first circuit layer; Processing the second conductor layer to form a second circuit layer, the second circuit layer including an input pad and an output pad; Separating the metal layer from the base layer to expose the metal layer to the external environment; Removing the portion of the second substrate corresponding to the plurality of first connection pads and the nickel layer to form an opening exposing the plurality of first connection pads; Installing the first chip on the plurality of first connection pads, and forming a first packaging layer covering the first chip.

In some embodiments, the method for manufacturing a chip packaging structure further includes the following steps: forming a first solder mask layer on the surface of the second circuit layer, wherein the first solder mask layer exposes the input pad and the output pad.

In some embodiments, the method for manufacturing a chip packaging structure further includes the following steps: processing the metal layer to form a third circuit layer; installing a second chip on the third circuit layer; and forming a second packaging layer covering the second chip.

In the chip packaging structure and its manufacturing method and electronic device provided by the embodiment of this application, the first chip and the input pad and output pad for connecting to the motherboard are located on the same side of the chip packaging structure in the thickness direction, and the first chip is embedded in the second substrate, which reduces the overall thickness of the chip packaging structure and facilitates miniaturization.

200: Chip packaging structure

10: Matrix

11: Base layer

12: Metal layer

13: Removable film

20: First substrate

21: First dielectric layer

22: First conductor layer

23: First circuit layer

231: First connection pad

31: Seed layer

32: Nickel layer

33: Dry film

40: Second substrate

41: Second dielectric layer

42: Second conductor layer

43: Second circuit layer

431: Input pad

432: Output pad

420: First conductive structure

410: First blind hole

50: First solder mask layer

40a: Opening

100:Packaging substrate

60: First chip

70: First packaging layer

300: Electronic equipment

310: Motherboard

320: Solder ball

121: Third circuit layer

121a: Second connection pad

61: Second chip

71: Second packaging layer

Figure 1 is a schematic cross-sectional view of the substrate provided in an embodiment of this application.

FIG2 is a schematic cross-sectional view of the first substrate after being pressed onto both sides of the substrate shown in FIG1.

FIG3 is a schematic cross-sectional view of the first circuit layer after being formed on the first substrate shown in FIG2.

FIG4 is a schematic cross-sectional view of the surface of the first circuit layer shown in FIG3 after the dry film is pressed.

FIG5 is a schematic cross-sectional view after a seed layer is formed on the surface of the first dielectric layer shown in FIG4.

FIG6 is a schematic cross-sectional view after a nickel layer is formed on the surface of the seed layer shown in FIG5.

FIG7 is a schematic cross-sectional view of the second substrate after being pressed onto the surface of the first circuit layer shown in FIG6.

FIG8 is a schematic cross-sectional view of the second circuit layer after being formed on the second substrate shown in FIG7.

FIG9 is a schematic cross-sectional view after a first solder mask layer is formed on the second circuit layer shown in FIG8.

FIG10 is a schematic cross-sectional view of the structure shown in FIG9 after the metal layer and the base layer are separated.

FIG11 is a schematic cross-sectional view after an opening is formed on the second dielectric layer shown in FIG10 .

FIG12 is a schematic cross-sectional view of the structure shown in FIG11 after the nickel layer is removed.

FIG13 is a schematic cross-sectional view of the structure shown in FIG12 after the seed layer is removed.

Figure 14 is a cross-sectional schematic diagram of the packaging structure provided in an embodiment of this application.

Figure 15 is a cross-sectional schematic diagram of an electronic device provided in an embodiment of this application.

Figure 16 is a cross-sectional schematic diagram of another embodiment of the present application after the third circuit layer is formed on the metal layer.

FIG17 is a schematic cross-sectional view after a second solder mask layer is formed on the third circuit layer described in FIG16.

Figure 18 is a cross-sectional schematic diagram of a chip packaging structure provided in another embodiment of the present application.

The technical scheme in the implementation mode of the present invention will be described clearly and completely below. Obviously, the implementation mode described is only a part of the implementation mode of the present invention, not all of the implementation modes. Based on the implementation mode of the present invention, all other implementation modes obtained by ordinary technicians in this field without creative labor are within the scope of protection of the present invention.

It should be noted that, unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by technicians in the technical field of the present invention. The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

Please refer to Figures 1 to 14. An embodiment of the present application provides a method for manufacturing a chip packaging structure 200, including the following steps.

Step S1, please refer to Figure 1, provide a substrate 10. The substrate 10 includes a base layer 11 and two metal layers 12 arranged on opposite sides of the base layer 11.

The base layer 11 is used to support the metal layer 12. The material of the metal layer 12 may include copper, gold, silver, etc. In this embodiment, the metal layer 12 is copper foil. In some embodiments, the waste removed after the circuit board is punched can be used as the base 10.

In some embodiments, the base layer 11 is connected to the metal layer 12 via a removable adhesive film 13 sandwiched between the base layer 11 and the metal layer 12, so as to facilitate separation of the metal layer 12 from the surface of the base layer 11.

Step S2, please refer to Figure 2, two first substrates 20 are pressed on two surfaces of the base 10. The first substrate 20 includes a first dielectric layer 21 and a first conductive layer 22 disposed on the surface of the first dielectric layer 21. After pressing, the first dielectric layer 21 is connected to the metal layer 12 and sandwiched between the metal layer 12 and the first conductive layer 22.

The first dielectric layer 21 can be made of a resin material with high temperature resistance, and the material can be selected from at least one of polyimide (PI), polyethylene terephthalate (PET), polytetrafluoroethylene (PTFE), polyamide (PA), polypropylene (PP), polyethylene (PE), liquid crystal polymer (LCP), polyvinyl chloride polymer (PVC), etc. In this embodiment, the material of the first dielectric layer 21 is PTFE.

The first conductive layer 22 is made of conductive material, which may include copper, gold, silver, etc. In this embodiment, the first conductive layer 22 is copper foil.

Step S3, please refer to Figure 3, the first conductor layer 22 is processed to form a first circuit layer 23. The first circuit layer 23 includes a plurality of first connection pads 231, and the plurality of first connection pads 231 are arranged at intervals from each other.

In this embodiment, the first conductor layer 22 is processed by a photolithography process to form the first circuit layer 23. It is understandable that other conventional circuit manufacturing methods can also be used to form the first circuit layer 23, and this application does not limit it.

Specifically, step S4 includes the following steps: step S41, referring to FIG. 4, a dry film 33 is pressed on the surface of the first circuit layer 23 facing away from the first dielectric layer 21, and the dry film 33 is exposed and developed to expose the plurality of first connection pads 231 and a portion of the surface of the first dielectric layer 21, the portion of the surface including the surface of the first dielectric layer 21 between the plurality of first connection pads 231 and the surface of the first dielectric layer 21 surrounding the plurality of first connection pads 231. The surface of the first dielectric layer 21 is exposed; step S42, please refer to FIG5, a seed layer 31 is formed on the exposed surface of the first dielectric layer 21; step S43, please refer to FIG6, a nickel layer 32 is formed on the seed layer 31 and a plurality of first connection pads 231, and the dry film 33 is removed to expose the first wiring layer 23, the portion of the first connection pad 231 is removed, and the portion of the first dielectric layer 21 corresponding to the nickel layer 32 and the first wiring layer 23 is removed.

The seed layer 31 may be formed on the surface of the first dielectric layer 21 by, but not limited to, a sputtering plating process. The nickel layer 32 may be formed on the surface of the seed layer 31 and the plurality of first connection pads 231 by, but not limited to, a chemical plating process.

Step S5, please refer to FIG. 7, the second substrate 40 is pressed on the surface of the first circuit layer 23 away from the first dielectric layer 21. The second substrate 40 includes a second dielectric layer 41 and a second conductor layer 42 disposed on the surface of the second dielectric layer 41. After pressing, the second dielectric layer 41 covers the nickel layer 32, the first circuit layer 23 is exposed on the surface of the first dielectric layer 21 and the nickel layer 32, and the first dielectric layer 21 is exposed on the surface of the first circuit layer 23 and the nickel layer 32, and the second conductor layer 42 is located on the surface of the second dielectric layer 41 away from the first dielectric layer 21.

The second dielectric layer 41 can be made of a resin material with high temperature resistance. The material of the second dielectric layer 41 and the material of the first dielectric layer 21 can be the same or different, and this application does not limit it. In this embodiment, the material of the second dielectric layer 41 is PI. The second conductive layer 42 is made of a conductive material, and its material can include copper, gold, silver, etc. In this embodiment, the second conductive layer 42 is copper foil.

Step S6, please refer to Figure 8, the second conductor layer 42 is processed to form a second circuit layer 43. The second circuit layer 43 includes input pads 431 and output pads 432 arranged at intervals. The input pads 431 and the output pads 432 are used to connect to the motherboard to supply power to the second circuit layer 43 and the first circuit layer 23. The second circuit layer 43 also exposes the surface of the second dielectric layer 41 corresponding to the nickel layer 32.

In this embodiment, the second conductor layer 42 is processed by photolithography to form the second circuit layer 43. It is understandable that other conventional circuit manufacturing methods can also be used to form the second circuit layer 43, and this application does not limit it.

The second circuit layer 43 is electrically connected to the first circuit layer 23 through the first conductive structure 420 penetrating the second dielectric layer 41. The first conductive structure 420 can be manufactured by the following method: forming a first blind hole 410 penetrating the second dielectric layer 41 and exposing a portion of the first circuit layer 23, and forming the first conductive structure 420 in the first blind hole 410 by electroplating, printing and other processes.

Step S7, please refer to Figure 9, a first solder mask layer 50 is formed on the surface of the second circuit layer 43, and the first solder mask layer 50 exposes part of the surface of the input pad 431 and part of the surface of the output pad 432.

The first solder mask 50 is used to protect the second circuit layer 43 to prevent the second circuit layer 43 from being oxidized or short-circuited by welding. The first solder mask 50 can be formed on the surface of the second circuit layer 43 by a printing process using solder mask ink, but is not limited to it.

Step S8, please refer to Figure 10, board separation: separate the metal layer 12 from the base layer 11, so that the metal layer 12 is exposed to the external environment.

When the metal layer 12 and the base layer 11 are separated, the metal layer 12 and the first substrate and the second substrate located on the side of the metal layer 12 away from the base layer 11 are separated as a whole to form a package substrate. By separating the boards, the stacked structure shown in FIG. 9 is divided into structures that can form two package substrates, thereby improving processing efficiency.

Step S9, please refer to Figure 11, remove the portion of the second dielectric layer 41 corresponding to the position of the nickel layer 32 to form an opening 40a that exposes the nickel layer 32.

The opening 40a exposes the entire nickel layer 32, so that the nickel layer 32 can be removed through the opening 40a. The opening 40a can be formed by, but not limited to, laser cutting, mechanical cutting, etc.

Step S10, please refer to Figure 12, remove the nickel layer 32 to expose multiple first connection pads 231 and the seed layer 31 in the opening 40a. The nickel layer 32 can be removed by, but is not limited to, an etching process.

Step S11, please refer to Figure 13, remove the seed layer 31 to expose part of the surface of the first dielectric layer 21 to obtain the packaging substrate 100. The seed layer 31 can be removed by, but not limited to, an etching process.

The package substrate 100 includes a metal layer 12, a first substrate 20, a second substrate 40 and a first solder mask 50. The first substrate 20 includes a first dielectric layer 21 and a first circuit layer 23 disposed on a surface of the first dielectric layer 21. The first dielectric layer 21 covers a surface of the metal layer 12. The first circuit layer 23 is located on a surface of the first dielectric layer 21 away from the metal layer 12. The second substrate 40 includes a second dielectric layer 41 and a second circuit layer 43 disposed on a surface of the second dielectric layer 41. The second dielectric layer 41 covers a surface of the first circuit layer 23 away from the first dielectric layer 21 and is connected to the first dielectric layer 21. The second substrate 40 is provided with an opening 40a that penetrates the second dielectric layer 41 and the second circuit layer 43 and exposes a plurality of first connection pads 231 of the first circuit layer 23. The input pad 431 and the output pad 432 of the second circuit layer 43 are located on both sides of the opening 40a and are electrically connected to the first circuit layer 23 through the first conductive structure 420, so that the second circuit layer 43 and the first circuit layer 23 are electrically connected. The first solder mask 50 covers the surface of the second circuit layer 43 and exposes the input pad 431 and the output pad 432.

Step S12, please refer to Figure 14, install the first chip 60 on the first connection pad 231, and fill the opening 40a with packaging material to form a first packaging layer 70, so as to obtain a chip packaging structure 200. The first chip 60 is accommodated in the opening 40a. The first packaging layer 70 covers the first chip 60 and fills the gap between the first chip 60 and the opening 40a, so that the first chip 60 is buried in the first packaging layer 70. The first chip 60 can be electrically connected to the first connection pad 231 by, but not limited to, flip-chip packaging.

In some embodiments, the material of the first packaging layer 70 is a non-conductive material, and the non-conductive material includes one or more of injection molding materials such as EMC (Epoxy Molding Compound), ABS (Acrylonitrile Butadiene Styrene), PC (Polycarbonate), and PET (Polyethylene Terephthalate).

In some embodiments, the surface of the first packaging layer 70 exposed in the opening 40a is flush with the surface of the first solder mask 50 facing away from the second dielectric layer 41.

It is understood that the order of the above steps and subsequent steps can be adjusted as needed. For example, step S7 can be executed after step S8, step S9, step S10, step S11 or step S12.

In the chip package structure 200 provided by the embodiment of the present application, the first chip 60 and the input pad 431 and the output pad 432 for connecting to the motherboard are located on the same side of the chip package structure 200 in the thickness direction, and the first chip 60 is embedded in the second substrate 40, which reduces the overall thickness of the chip package structure 200 and facilitates miniaturization. In addition, the metal layer 12 has a whole continuous structure, which is located on the side of the chip package structure 200 away from the first chip 60 and corresponds to the position of the first chip 60, which can achieve electrostatic shielding.

Referring to FIG. 15 , an embodiment of the present application provides an electronic device 300, including a chip package structure 200 and a motherboard 310. The motherboard 310 is disposed on a side of the chip package structure 200 where an input pad 431 and an output pad 432 are provided, and is electrically connected to the input pad 431 and the output pad 432 to supply power to the chip package structure 200. The motherboard 310 can be electrically connected to the input pad 431 and the output pad 432 through solder balls 320.

In some embodiments, after step S8, the method for manufacturing the chip package structure 200 further includes the following steps.

Step S81, please refer to Figure 16, the metal layer 12 is processed to form a third circuit layer 121. The third circuit layer 121 includes a plurality of second connection pads 121a arranged at intervals.

In this embodiment, the metal layer 12 is processed by photolithography to form the third circuit layer 121. It is understandable that other conventional circuit manufacturing methods can also be used to form the third circuit layer 121, and this application does not limit it.

The third circuit layer 121 is electrically connected to the first circuit layer 23 through the second conductive structure 122 penetrating the first dielectric layer 21. The second conductive structure 122 can be manufactured by the following method: forming a second blind hole penetrating the first dielectric layer 21 and exposing a portion of the first circuit layer 23, and forming the second conductive structure 122 in the second blind hole by electroplating, printing and other processes.

Step S82, please refer to Figure 17, a second solder mask layer 51 is formed on the surface of the third circuit layer 121, and the second solder mask layer 51 exposes part of the surface of the second connection pad 121a.

Step S83, please refer to Figure 18, the second chip 61 is installed on the second connection pad 121a, and a second packaging layer 71 covering the second chip 61 is formed. The second packaging layer 71 also covers the surface of the second solder mask 51 away from the third circuit layer 121, and fills the gap between the second chip 61 and the second connection pad 121a. The second chip 61 can be electrically connected to the second connection pad 121a by, but not limited to, flip-chip packaging. The second chip 61 is packaged on the side of the chip packaging structure 200 away from the first chip 60, which improves the integration of the chip packaging structure 200 and facilitates miniaturization.

In addition, technicians in this field can also make other changes within the spirit of the invention. Of course, these changes made based on the spirit of the invention should be included in the scope of protection required by the invention.

200: Chip packaging structure

12: Metal layer

20: First substrate

21: First dielectric layer

23: First circuit layer

231: First connection pad

40: Second substrate

41: Second dielectric layer

43: Second circuit layer

431: Input pad

432: Output pad

420: First conductive structure

410: First blind hole

50: First solder mask layer

40a: Opening

100:Packaging substrate

60: First chip

70: First packaging layer

Claims (7)

A chip packaging structure, comprising: a packaging substrate, the packaging substrate comprising a first substrate and a second substrate, the first substrate comprising a first dielectric layer and a first circuit layer arranged on a surface of the first dielectric layer, the second substrate comprising a second dielectric layer and a second circuit layer, the second dielectric layer covering a surface of the first circuit layer away from the first dielectric layer, the second circuit layer being arranged on a surface of the second dielectric layer away from the first circuit layer, the second circuit layer comprising an input solder pad and an output solder pad, the second substrate being provided with a plurality of solder pads extending through the second dielectric layer. The first circuit layer and the second circuit layer are provided with an opening that exposes a portion of the second circuit layer; a first chip, the first chip is arranged in the opening and is electrically connected to the first circuit layer; and a first packaging layer, the first packaging layer is filled in the opening and covers the first chip; a first solder mask layer, the first solder mask layer is arranged on the surface of the second circuit layer away from the second dielectric layer and exposes the input solder pad and the output solder pad, and the surface of the first solder mask layer away from the second circuit layer is flush with the surface of the first packaging layer exposed in the opening. The chip package structure as described in claim 1, wherein the chip package structure further includes a metal layer, and the metal layer covers the surface of the first dielectric layer away from the first circuit layer. The chip packaging structure as described in claim 1, wherein the chip packaging structure further includes a third circuit layer, a second chip and a second packaging layer, the third circuit layer is arranged on the surface of the first dielectric layer away from the first circuit layer, the second chip is electrically connected to the third circuit layer, and the second packaging layer covers the second chip. The chip packaging structure as described in claim 3, wherein the chip packaging structure further includes a second solder mask layer, the second solder mask layer is disposed on the surface of the third circuit layer away from the first dielectric layer and exposes a portion of the third circuit layer, and the second packaging layer is disposed on the surface of the second solder mask layer away from the first dielectric layer. An electronic device, comprising a chip package structure and a motherboard as described in any one of claims 1 to 4, wherein the motherboard is arranged on one side of the chip package structure and is electrically connected to the input pad and the output pad. A method for manufacturing a chip package structure, wherein the method comprises the following steps: providing a substrate, wherein the substrate comprises a base layer and two metal layers arranged on opposite sides of the base layer; pressing two first substrates on two surfaces of the substrate, wherein the first substrate comprises a first dielectric layer connected to the metal layer and a first conductor layer arranged on a surface of the first dielectric layer facing away from the first dielectric layer; processing the first conductor layer to form a first circuit layer, wherein the first circuit layer comprises a plurality of first connection pads arranged at intervals; forming a nickel layer covering the plurality of first connection pads; pressing a second substrate on a surface of the first circuit layer facing away from the first dielectric layer, wherein the second substrate comprises a second dielectric layer covering the nickel layer and the first circuit layer and a second conductor layer arranged on a surface of the second dielectric layer facing away from the first dielectric layer; A second conductive layer is formed on the surface of the first circuit layer; the second conductive layer is processed to form a second circuit layer, the second circuit layer includes an input solder pad and an output solder pad; a first solder mask is formed on the surface of the second circuit layer, the first solder mask exposes the input solder pad and the output solder pad; the metal layer is separated from the base layer to expose the metal layer to the external environment; the portion of the second substrate corresponding to the plurality of first connection pads and the nickel layer are removed to form an opening to expose the plurality of first connection pads; a first chip is mounted on the plurality of first connection pads, and a first packaging layer covering the first chip is formed, the surface of the first solder mask facing away from the second circuit layer is flush with the surface of the first packaging layer exposed in the opening. The manufacturing method of the chip packaging structure as described in claim 6 further includes the following steps: Processing the metal layer to form a third circuit layer; installing a second chip on the third circuit layer; forming a second packaging layer covering the second chip.

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