CN115515325B - Circuit board and method for manufacturing the same - Google Patents
Circuit board and method for manufacturing the same Download PDFInfo
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- CN115515325B CN115515325B CN202110694227.0A CN202110694227A CN115515325B CN 115515325 B CN115515325 B CN 115515325B CN 202110694227 A CN202110694227 A CN 202110694227A CN 115515325 B CN115515325 B CN 115515325B
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- Prior art keywords
- layer
- circuit
- copper
- circuit layer
- dielectric layer
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Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 68
- 229910052802 copper Inorganic materials 0.000 claims abstract description 68
- 239000010949 copper Substances 0.000 claims abstract description 68
- 239000002184 metal Substances 0.000 claims abstract description 54
- 229910052751 metal Inorganic materials 0.000 claims abstract description 54
- 239000010410 layer Substances 0.000 claims description 492
- 239000000758 substrate Substances 0.000 claims description 47
- 238000009713 electroplating Methods 0.000 claims description 12
- 238000000059 patterning Methods 0.000 claims description 8
- 239000000084 colloidal system Substances 0.000 claims description 4
- 239000011241 protective layer Substances 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 239000003292 glue Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 239000004698 Polyethylene Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 229920000573 polyethylene Polymers 0.000 description 2
- -1 polyethylene terephthalate Polymers 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229920000877 Melamine resin Polymers 0.000 description 1
- 229920001807 Urea-formaldehyde Polymers 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000007306 functionalization reaction Methods 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000011112 polyethylene naphthalate Substances 0.000 description 1
- 229920002635 polyurethane Polymers 0.000 description 1
- 239000004814 polyurethane Substances 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Abstract
A circuit board and a manufacturing method thereof are provided, the circuit board comprises a first dielectric layer, a first circuit layer, a first copper layer, a metal protection layer, a second dielectric layer and a second circuit layer, along the stacking direction of the circuit board, the projection of the metal protection layer covers part of the first circuit layer, the projection of the second circuit layer is located on the outer side of the metal protection layer, a groove is formed in the second dielectric layer to expose the metal protection layer, the metal protection layer is removed to form a containing cavity, a first element is provided and is placed in the containing cavity, a second element is provided and is placed in the containing cavity and is placed on the first element, a first copper-clad plate is provided and is pressed on the surface of the two circuit layers, the first copper-clad plate comprises a third dielectric layer and a second copper layer, the third dielectric layer is filled in the containing cavity, the first copper layer is patterned to form a third circuit layer electrically connected with the first element, and the second copper layer is patterned to form a fourth circuit layer electrically connected with the second element, and the circuit board is obtained.
Description
Technical Field
The present disclosure relates to printed circuit boards, and particularly to a printed circuit board and a method for manufacturing the same.
Background
With the multifunctionalization of electronic devices, the mounting area of the packaging structure in the electronic device is further compressed, so that the packaging of the circuit board is required to meet the requirements of lightness, thinness, shortness and multifunctionalization.
However, the existing circuit board packaging structure is large in size, the number of installed electronic components is small, the space utilization rate is low, and the requirements are difficult to meet.
Disclosure of Invention
In view of this, in order to overcome at least one of the above-mentioned drawbacks, it is necessary to propose a method for manufacturing a circuit board.
In addition, the invention also provides a circuit board manufactured by adopting the manufacturing method.
The invention provides a manufacturing method of a circuit board, which comprises the following steps:
The circuit substrate comprises a first dielectric layer, a first circuit layer embedded in and exposed on the first surface of the first dielectric layer, a first copper layer arranged on the first surface and covering the first circuit layer, a metal protection layer arranged on the second surface of the first dielectric layer, which is away from the first circuit layer, at least one second dielectric layer formed on the second surface, and a second circuit layer arranged on one side of each second dielectric layer, which is away from the first dielectric layer, wherein the second dielectric layer covers the metal protection layer, and along the stacking direction of the circuit substrate, the projection of the metal protection layer covers part of the first circuit layer, and the projection of the second circuit layer is positioned on the outer side of the metal protection layer.
Slotting on each second dielectric layer to expose the metal protection layer;
And removing the metal protection layer to form a containing cavity.
At least one first element is provided, which is inserted into the receiving space.
At least one second element is provided, which is inserted into the receiving space and is placed on the first element.
Providing a first copper-clad plate, pressing the first copper-clad plate to one side, away from the first circuit layer, of the two circuit layers, wherein the first copper-clad plate comprises a third dielectric layer and a second copper layer, and the third dielectric layer is filled in the accommodating cavity.
And patterning the first copper layer to form a third circuit layer, wherein the third circuit layer is electrically connected with the first element, patterning the second copper layer to form a fourth circuit layer, and the fourth circuit layer is electrically connected with the second element, so that the circuit board is obtained.
In an embodiment of the present application, the manufacturing of the circuit substrate includes the following steps:
Providing a carrier plate, wherein the carrier plate comprises a substrate layer and a stripping layer positioned on at least one surface of the substrate layer, and forming the first copper layer on the surface of at least one stripping layer, which is away from the substrate layer.
And forming the first circuit layer on the surface of the first copper layer, which is away from the carrier plate.
Providing a second copper-clad plate, wherein the second copper-clad plate comprises a first dielectric layer and a third copper layer positioned on the second surface of the first dielectric layer, the second copper-clad plate is covered on the surface of the first circuit layer, which is away from the carrier plate, and is pressed, and the first circuit layer is embedded in the first dielectric layer.
And removing part of the third copper layer to form the metal protection layer, wherein the projection of the metal protection layer covers part of the first circuit layer along the stacking direction of the carrier plate.
Providing at least one third copper-clad plate, wherein each third copper-clad plate comprises a second dielectric layer and a fourth copper layer positioned on the surface of the second dielectric layer, the third copper-clad plate is covered on the second surface of the first dielectric layer and pressed, the metal protective layer is embedded in the second dielectric layer, the fourth copper layer is patterned to form a second circuit layer, and the projection of each second circuit layer is positioned on the outer side of the metal protective layer along the stacking direction of the carrier plate.
And removing the carrier plate to obtain the circuit substrate.
In an embodiment of the present application, the second circuit layer includes a bottom circuit layer and an electroplating circuit layer, the bottom circuit layer is located on a surface of the second dielectric layer, the electroplating circuit layer is located on a surface of the bottom circuit layer facing away from the second dielectric layer, and the manufacturing method of the circuit substrate further includes:
and electroplating the surface of the fourth copper layer to form the electroplating circuit layer.
And patterning the fourth copper layer to form the bottom circuit layer, thereby obtaining the second circuit layer.
In an embodiment of the present application, before forming the third circuit layer and the fourth circuit layer, the manufacturing method further includes a step of forming a via hole.
In the embodiment of the application, a laser is used for grooving each second dielectric layer.
In an embodiment of the present application, the electrical connection end of each first element faces the third circuit layer, and the electrical connection end of each second element faces the fourth circuit layer.
In an embodiment of the present application, after the first element is installed in the accommodating cavity, the manufacturing method further includes:
And coating colloid on the surface of the first element, which is away from the first medium layer.
In an embodiment of the present application, the method further includes:
And adding layers on one side of the third circuit layer and/or the fourth circuit layer, which is away from the first medium layer, to form at least one fifth circuit layer, wherein each fifth circuit layer is electrically connected with the third circuit layer and/or the fourth circuit layer.
In an embodiment of the present application, the specific step of removing the metal protection layer includes:
And covering a dry film on the surface of the third circuit layer, which is away from the first circuit layer.
And exposing and developing the dry film, and removing the metal protective layer exposed to the dry film.
And removing the dry film.
In an embodiment of the present application, the first circuit layer is in contact with and electrically connected to the third circuit layer.
The invention also provides a circuit board which comprises a circuit substrate, a containing cavity, at least one first element, at least one second element, a third dielectric layer and a fourth circuit layer. The circuit substrate comprises a first dielectric layer, a second dielectric layer and a first electrode, wherein the first dielectric layer comprises a first surface and a second surface which are oppositely arranged; a first circuit layer embedded in and exposed to the first surface of the first dielectric layer; at least one second dielectric layer arranged on the second surface of the first dielectric layer; the circuit comprises a first medium layer, a second medium layer, a third medium layer, a containing cavity, a fourth medium layer, a first element, a second element, a third element and a first element, wherein the first medium layer is arranged on the first surface and covers part of the first medium layer, the containing cavity penetrates through each second medium layer, the first medium layer is covered by projection of the containing cavity along the stacking direction of the circuit substrate, the second circuit layer is arranged on the outer side of the containing cavity, each first element is arranged in the containing cavity and is electrically connected with the third circuit layer, each second element is arranged in the containing cavity and is arranged on the first element, the third medium layer is arranged on the side of the second circuit layer, which is away from the first circuit layer, the third medium layer extends into the containing cavity, the fourth circuit layer is arranged on the side of the third medium layer, which is away from the second circuit layer, and is electrically connected with the fourth element.
Compared with the prior art, the manufacturing method of the circuit board provided by the invention has the advantages that the first circuit layer is buried in the circuit substrate, the first circuit layer can be effectively prevented from being oxidized, the metal protection layer is arranged, the first circuit layer is effectively prevented from being damaged in the process of forming the accommodating cavity, the depth control precision of the accommodating cavity can be improved, the glue stripping process is avoided in the process of forming the accommodating cavity, the surface of the first circuit layer is prevented from being polluted by residual glue, a plurality of elements can be accommodated in the accommodating cavity, double-sided conduction can be realized, the element installation density of the circuit board is improved, the space utilization rate of the circuit board is improved, and the multi-functional, light, thin and short circuit board can be favorably met.
Drawings
Fig. 1 is a schematic structural diagram of a carrier and a first copper layer according to an embodiment of the present invention.
Fig. 2 and 3 are schematic diagrams illustrating formation of a first circuit layer on a surface of the first copper layer shown in fig. 1.
Fig. 4 is a schematic diagram of laminating a second copper-clad plate on the surface of the first circuit layer shown in fig. 3.
Fig. 5 and 6 are schematic views illustrating the removal of a portion of the third copper layer shown in fig. 4 to form a metal protection layer.
Fig. 7 and 8 are schematic diagrams illustrating formation of a second circuit layer on the surface of the first dielectric layer shown in fig. 6.
Fig. 9 is a schematic view of removing the circuit substrate on the carrier shown in fig. 8.
Fig. 10 is a schematic structural diagram of a circuit substrate according to an embodiment of the invention.
FIG. 11 is a schematic illustration of a trench formed in the second dielectric layer shown in FIG. 10 to expose the metal protection layer.
Fig. 12 and 13 are schematic views illustrating removal of the metal protection layer shown in fig. 11 to form a receiving cavity.
Fig. 14 is a schematic view of the first element installed in the receiving chamber shown in fig. 13.
Fig. 15 is a schematic view of disposing a gel on the first element shown in fig. 14.
Fig. 16 is a schematic view of a second element disposed on the gel in the receiving chamber shown in fig. 15.
Fig. 17 is a schematic diagram of laminating a first copper-clad plate on a surface of the second dielectric layer facing away from the first circuit layer shown in fig. 16.
Fig. 18 is a schematic view of punching holes in the first copper-clad plate and the third copper-clad plate shown in fig. 17.
Fig. 19 is a schematic view illustrating patterning of the first copper layer and the fourth copper layer shown in fig. 18 to form a third circuit layer and a fourth circuit layer, respectively.
Fig. 20 is a schematic structural diagram of a circuit board according to an embodiment of the invention.
Description of the main reference signs
Circuit Board 100 Carrier 20
Substrate layer 21 of circuit board 10
First dielectric layer 11 release layer 22
First surface 111 dry films 30, 30a, 30b
Second surface 112 second copper-clad plate 40
Third copper layer 41 of first wiring layer 12
First copper layer 13 third copper-clad plate 50
Fourth copper layer 51 of metal cap layer 14
Second dielectric layer 15 accommodates cavity 60
Second circuit layer 16 first element 71
Underlying wiring layer 161 second element 72
Electroplating line layer 162 colloid 73
Third circuit layer 17 first copper-clad plate 80
Third dielectric layer 81 of via holes 171,181
Second copper layer 82 of conductive pillars 172,182
Fourth dielectric layer 90 of fourth line layer 18
Fifth wiring layer 19 direction a
The invention will be further described in the following detailed description in conjunction with the above-described figures.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
The embodiment of the invention provides a manufacturing method of a circuit board 100, which specifically comprises the following steps:
In step S1, referring to fig. 1 to 10, a circuit substrate 10 is provided, and the circuit substrate 10 includes a first dielectric layer 11, a first circuit layer 12, a first copper layer 13, a metal protection layer 14, at least one second dielectric layer 15, and at least one second circuit layer 16. The first dielectric layer 11 includes a first surface 111 and a second surface 112 that are disposed opposite to each other, the first circuit layer 12 is embedded in and exposed on the first surface 111 of the first dielectric layer 11, and the first copper layer 13 is located on the first surface 111 and covers the first circuit layer 12. The metal protection layer 14 is located on the second surface 112, and the metal protection layer 14 covers a portion of the first circuit layer 12 along the stacking direction a of the circuit substrate 10. The second dielectric layer 15 is located at a side of the first dielectric layer 11 away from the first circuit layer 12, the second circuit layer 16 is located at a side of the second dielectric layer 15 away from the first dielectric layer 11, and along the direction a, the projection of the second circuit layer 16 is located at an outer side of the metal protection layer 14.
The first circuit layer 12 is embedded in the first dielectric layer 11, and the first copper layer 13 covers the first circuit layer 12 exposed on the surface of the first dielectric layer 11, so that the first circuit layer 12 can be effectively prevented from being oxidized and damaged.
The material of the first dielectric layer 11 may be, but is not limited to, one of Polyimide (PI), glass fiber epoxy (FR 4), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethylene (PE), and the like.
In some embodiments, the first circuit substrate 10 may be a multi-layer circuit substrate, that is, the first circuit substrate 10 further includes at least one other circuit layer embedded in the first dielectric layer 11 and stacked with the first circuit layer 12.
In this embodiment, the circuit substrate 10 may be manufactured by the following steps:
in step S11, referring to fig. 1, a carrier 20 is provided, the carrier 20 includes a substrate layer 21 and a release layer 22 disposed on at least one surface of the substrate layer 21, and a first copper layer 13 is formed on a surface of the release layer 22 facing away from the substrate layer 21.
The substrate layer 21 is a carrier plate for forming the circuit substrate 10, and the material of the substrate layer 21 is not limited. The release layer 22 serves to temporarily bond the base material layer 21 and the first copper layer 13, the release layer 22 is made of an insulating material, and the release layer 22 may be selected from colloids that are easily separated or removed during subsequent processing.
In this embodiment, the release layers 22 are provided on opposite surfaces of the base material layer 21, and the first copper layer 13 is formed on the surface of each release layer 22.
In step S12, referring to fig. 2 and 3, a first circuit layer 12 is formed on a surface of the first copper layer 13 facing away from the carrier 20.
Specifically, the surface of the first copper layer 13 is covered with a dry film 30, and the first circuit layer 12 is formed by exposing and developing, and electroplating the surface of the first copper layer 13, and finally the undeveloped dry film 30 is removed.
In step S13, referring to fig. 4, a second copper-clad plate 40 is provided, the second copper-clad plate 40 includes a first dielectric layer 11 and a third copper layer 41 located on the surface of the first dielectric layer 11, the surface of the first circuit layer 12 facing away from the carrier 20 is covered with the second copper-clad plate 40 and pressed, and the first circuit layer 12 is embedded in the first dielectric layer 11.
In this embodiment, the number of the second copper clad laminates 40 is two, and the second copper clad laminates 40 are respectively pressed on the surfaces of the first circuit layer 12 on the opposite surfaces of the carrier 20.
In step S14, referring to fig. 5 and 6, a portion of the third copper layer 41 is removed to form the metal protection layer 14. Along the direction a, the projection of the metal protection layer 14 covers a portion of the first wiring layer 12.
The surface of the third copper layer 41 is covered with a dry film 30a, and the dry film 30a is used for removing a portion of the third copper layer 41 after exposure and development, and the remaining portion of the third copper layer 41 (i.e., the metal protection layer 14) is along the direction a, so that the projection of the metal protection layer 14 covers a portion of the first circuit layer 12, and the metal protection layer 14 protects the first circuit layer 12 from damage in the subsequent step of forming the accommodating cavity 60.
Referring to fig. 7 and 8, referring to fig. 9 in combination, at least one third copper-clad plate 50 is provided, each third copper-clad plate 50 includes the second dielectric layer 15 and a fourth copper layer 51 on the surface of the second dielectric layer 15, the surface of the first dielectric layer 11 facing away from the carrier 20 covers the third copper-clad plate 50 and is pressed, and the metal protection layer 14 is embedded in the second dielectric layer 15. The fourth copper layer 51 is patterned to form the second circuit layers 16, and the projection of each second circuit layer 16 is located outside the metal protection layer 14 along the direction a.
In this embodiment, the number of the third copper clad laminate 50 is two, and a layer of the second circuit layer 16 may be formed after a layer of the third copper clad laminate 50 is pressed on the surface of the first dielectric layer 11, as shown in fig. 8. And then, by pressing a third copper clad laminate 50 in the same manner, another second circuit layer 16 is formed, as shown in fig. 8 and 9.
It will be appreciated that two adjacent layers of the second circuit layer 16 and the first circuit layer 12 may be electrically connected to each other by a via (not shown).
Further, the second circuit layer 16 includes a bottom circuit layer 161 and an electroplated circuit layer 162, the bottom circuit layer 161 is located on the surface of the second dielectric layer 15, and the electroplated circuit layer 162 is located on the surface of the bottom circuit layer 161 facing away from the second dielectric layer 15, and in this embodiment, the manufacturing method of the second circuit layer 16 includes:
The surface of the fourth copper layer 52 is covered with a dry film 30a, exposed and developed, and plated to form the plated circuit layer 162 and the underlying circuit layer 161, thereby obtaining the second circuit layer 16. The thickness of the second circuit layer 16 can meet the actual circuit thickness requirement by adopting the electroplating circuit mode in the embodiment.
In step S16, referring to fig. 9 and 10, the carrier 20 is removed to obtain the circuit substrate 10.
In this embodiment, after the carrier 20 is removed, the number of the circuit substrates 10 is two.
Further, the step of fabricating the circuit substrate 10 further includes a step of forming a via hole (not shown) to electrically connect the first circuit layer 12 with the second circuit layer 16 formed later. The step of forming the via hole may be performed before the step of removing the carrier 20, or may be performed after the step of removing the carrier 20.
In step S2, referring to fig. 11, a slot is formed on each of the second dielectric layers 15 to expose the metal passivation layer 14.
A part of the first circuit layer 12 is covered with the metal protection layer 14, and the first circuit layer 12 is prevented from being damaged when the second dielectric layer 15 is removed, thereby protecting the first circuit layer 12.
In the projection area of the metal protection layer 14 on the second dielectric layer 15, the second dielectric layer 15 may be removed by laser, so as to form a precursor of the accommodating cavity 60, and prevent the first circuit layer 12 from being etched by the laser.
In step S3, referring to fig. 12 and 13, the metal protection layer 14 is removed to form a receiving cavity 60.
And covering a dry film 30b on the surface of the second circuit layer 16 facing away from the first circuit layer 12, exposing and developing the dry film 30b, removing the metal protection layer 14 exposed to the dry film 30b, and removing the dry film 30b to form the accommodating cavity 60. The receiving chamber 60 extends through all of the second dielectric layers 15, wherein the second surface 112 of the first dielectric layer 11 forms the bottom of the receiving chamber 60. In addition, the surface of the metal protection layer 14 is flat, and when the metal protection layer 14 is removed to form the accommodating cavity 60, the depth control of the accommodating cavity 60 is more accurate.
It will be appreciated that in other embodiments, the receiving cavity 60 may also be formed by machining.
Step S4 referring to FIG. 14, at least one first element 71 is provided and is received in the receiving cavity 60.
The electrical connection end of the first element 71 faces the first circuit layer 12 to facilitate the electrical connection in the subsequent step.
Referring to fig. 15 and 16, at least one second member 72 is provided and is inserted into the receiving chamber 60 and placed on the first member 71.
The electrical connection end of the second element 72 faces away from the first circuit layer 12.
In this embodiment, before the second element 72 is assembled, the manufacturing method further includes:
A glue 73 is coated on the surface of the first element 71 facing away from the first circuit layer 12. In particular, the glue 73 may be an insulating glue, and the glue 73 may further fix the first element 71 and the second element 72, providing stability of the first element 71 and the second element 72 in the receiving cavity 60.
In step S6, referring to fig. 17, a first copper-clad plate 80 is provided and pressed onto a side of the second circuit layer 16 facing away from the first circuit layer 12, the first copper-clad plate 80 includes a third dielectric layer 81 and a second copper layer 82, and the third dielectric layer 81 is filled in the accommodating cavity 60.
The third dielectric layer 81 flows and fills the region between the second wiring layers 16 and the accommodating chamber 60. The second circuit layer 16, the first element 71 and the second element 72 are all embedded in the third dielectric layer 81. The third dielectric layer 81 can fix the first element 71 and the second element 72.
In this embodiment, the third dielectric layer 81 may be at least one selected from the group consisting of prepreg, epoxy resin, polyurethane, phenolic resin, urea resin, melamine-formaldehyde resin, unsaturated resin, polyimide, and the like.
In step S7, referring to fig. 18 to 20, the first copper layer 13 is patterned to form a third circuit layer 17, the third circuit layer 17 is electrically connected to the first component 71, the second copper layer 82 is patterned to form a fourth circuit layer 18, and the fourth circuit layer 18 is electrically connected to the second component 72, thereby obtaining the circuit board 100.
In the present embodiment, the third wiring layer 17 is formed by exposing, developing, and plating a dry film on the surface of the first copper layer 13. The third circuit layer 17 contacts with part of the first circuit layer 12, two circuits of the first circuit layer 12 buried in and the third circuit layer 17 positioned on the surface of the first medium layer 11 are manufactured on the same medium layer, the other insulating layer is prevented from being added between the two circuit layers, the two circuit layers are not required to be electrically connected through the through holes, the manufacturing process is simpler, the circuit manufacturing efficiency of the circuit board is improved, the cost is lower, the whole thickness of the circuit board is reduced, and the circuit board is thinner.
In this embodiment, before forming the third circuit layer 17, the method further includes forming a via 171 on the first copper layer 13 and the first dielectric layer 11, and forming a conductive post 172 in the via 171 to electrically connect the third circuit layer 17 with the first element 71.
The surface of the second copper layer 82 is covered with a dry film, and before the fourth line layer 18 is formed by exposing, developing and electroplating, the method further includes forming a via 181 on the second copper layer 82 and the third dielectric layer 81, and forming a conductive post 182 in the via 181 to electrically connect the fourth line layer 18 with the second element 72.
In this embodiment, referring to fig. 20, the manufacturing method further includes:
and pressing a fourth copper-clad plate (not shown) on one side of the third circuit layer 17 and/or the fourth circuit layer 18, which is away from the first dielectric layer 11, wherein the fourth copper-clad plate comprises a fourth dielectric layer 90 and a fifth copper layer (not shown), the fifth copper layer is patterned to form a fifth circuit layer 19, and the fifth circuit layer 19 is electrically connected with the third circuit layer 17 and/or the fourth circuit layer 18. It will be appreciated that the fifth circuit layer 19 may be formed in a build-up manner as described above to meet practical requirements.
Referring to fig. 19, the present invention further provides a circuit board 100, where the circuit board 100 includes a circuit substrate 10, a receiving cavity 60, at least one first component 71, at least one second component 72, a third dielectric layer 81, and a fourth circuit layer 18. The circuit substrate 10 includes a first dielectric layer 11, a first circuit layer 12, at least one second dielectric layer 15, a second circuit layer 16, and a third circuit layer 17. The first dielectric layer 11 comprises a first surface 111 and a second surface 112 which are oppositely arranged, the first circuit layer 12 is embedded in and exposed on the first surface 111 of the first dielectric layer 11, the second dielectric layers 15 are arranged on the second surfaces 112 of the first dielectric layer 11, the second circuit layers 12 are arranged on one side, away from the first dielectric layers 11, of each second dielectric layer 15, and the third circuit layer 17 is arranged on the first surface 111 and covers part of the first circuit layers 12. The accommodating cavity 60 is disposed through each second dielectric layer 15, along the stacking direction of the circuit substrate 10, the projection of the accommodating cavity 60 covers a part of the first circuit layers 12, the second circuit layers 16 are located at the outer sides of the accommodating cavity 60, each first element 71 is disposed in the accommodating cavity 60, each first element 71 is electrically connected to the third circuit layer 17, each second element 72 is disposed in the accommodating cavity 60 and disposed on the first element 71, the third dielectric layer 81 is disposed on a side of the second circuit layer 16 facing away from the first circuit layers 12, the third dielectric layer 81 extends into the accommodating cavity 60, the fourth circuit layer 18 is disposed on a side of the third dielectric layer 81 facing away from the second circuit layer 16, and the fourth circuit layer 18 is electrically connected to the second elements 72.
In this embodiment, referring to fig. 20, at least one fourth dielectric layer 90 and at least one fifth circuit layer 19 may be further formed on a side of the third circuit layer 17 and the fourth circuit layer 18 facing away from the first dielectric layer 11, and each of the fifth circuit layers 19 may be electrically connected to the third circuit layer 17 or the fourth circuit layer 18.
The manufacturing method of the circuit board 100 provided by the invention has the advantages that the first circuit layer 12 is buried in the circuit substrate 10, the first circuit layer 12 can be effectively prevented from being oxidized, the metal protection layer 14 is arranged, the first circuit layer 12 can be effectively prevented from being damaged in the process of forming the accommodating cavity 60, the depth control precision of the accommodating cavity 60 can be improved, the glue stripping process is avoided in the process of forming the accommodating cavity 60, the surface of the first circuit layer 12 is prevented from being polluted by residual glue, a plurality of elements can be accommodated in the accommodating cavity 60, double-sided conduction can be realized, the element installation density of the circuit board 100 is improved, the space utilization rate of the circuit board 100 is improved, and the multi-functionalization, the thinness and the shortness of the circuit board 100 are favorably met.
Claims (8)
1. The manufacturing method of the circuit board is characterized by comprising the following steps:
Providing a circuit substrate, wherein the circuit substrate comprises a first dielectric layer, a first circuit layer embedded in and exposed on a first surface of the first dielectric layer, a first copper layer arranged on the first surface and covering the first circuit layer, a metal protection layer arranged on a second surface of the first dielectric layer, which is away from the first circuit layer, at least one second dielectric layer formed on the second surface, and a second circuit layer arranged on one side of each second dielectric layer, which is away from the first dielectric layer, wherein the second dielectric layer covers the metal protection layer, and along the stacking direction of the circuit substrate, the projection of the metal protection layer covers part of the first circuit layer, and the projection of the second circuit layer is positioned outside the metal protection layer;
Slotting on each second dielectric layer to expose the metal protection layer;
removing the metal protection layer to form a containing cavity;
providing at least one first element to be housed in said housing cavity;
providing at least one second element which is inserted into the receiving chamber and is placed on the first element;
Providing a first copper-clad plate which is pressed on one side of the second circuit layer, which is far away from the first circuit layer, wherein the first copper-clad plate comprises a third dielectric layer and a second copper layer, the third dielectric layer is filled in the accommodating cavity, and
Patterning the first copper layer to form a third circuit layer, wherein the third circuit layer is electrically connected with the first element, and is in contact with part of the first circuit layer, the third circuit layer is electrically connected with the first circuit layer, patterning the second copper layer to form a fourth circuit layer, and the fourth circuit layer is electrically connected with the second element, so that the circuit board is obtained,
The manufacturing of the circuit substrate comprises the following steps:
Providing a carrier plate, wherein the carrier plate comprises a substrate layer and a stripping layer positioned on at least one surface of the substrate layer, and forming the first copper layer on the surface of at least one stripping layer away from the substrate layer;
forming the first circuit layer on the surface of the first copper layer, which is away from the carrier plate;
Providing a second copper-clad plate, wherein the second copper-clad plate comprises the first dielectric layer and a third copper layer positioned on the second surface of the first dielectric layer, the second copper-clad plate is covered and pressed on the surface, facing away from the carrier plate, of the first circuit layer, and the first circuit layer is embedded in the first dielectric layer;
Removing part of the third copper layer to form the metal protection layer, wherein the projection of the metal protection layer covers part of the first circuit layer along the stacking direction of the carrier plate;
Providing at least one third copper-clad plate, wherein each third copper-clad plate comprises a second dielectric layer and a fourth copper layer positioned on the surface of the second dielectric layer, covering the third copper-clad plate on the second surface of the first dielectric layer and laminating, embedding a metal protection layer into the second dielectric layer, patterning the fourth copper layer to form a second circuit layer, and positioning the projection of each second circuit layer outside the metal protection layer along the stacking direction of the carrier plate, wherein the metal protection layer is formed by the steps of
Removing the carrier plate to obtain the circuit substrate;
The second circuit layer comprises a bottom circuit layer and an electroplating circuit layer, the bottom circuit layer is positioned on the surface of the second medium layer, the electroplating circuit layer is positioned on the surface of the bottom circuit layer, which is away from the second medium layer, and the manufacturing method of the circuit substrate further comprises the following steps:
Electroplating the surface of the fourth copper layer to form the electroplating circuit layer, and
And patterning the fourth copper layer to form the bottom circuit layer, thereby obtaining the second circuit layer.
2. The method of manufacturing a circuit board according to claim 1, wherein before forming the third wiring layer and the fourth wiring layer, the method further comprises a step of forming a via hole.
3. The method of claim 1, wherein a laser is used to form a slot in each of the second dielectric layers.
4. The method of manufacturing a circuit board according to claim 1, wherein an electrical connection terminal of each of the first elements is directed toward the third circuit layer, and an electrical connection terminal of each of the second elements is directed toward the fourth circuit layer.
5. The method of manufacturing a circuit board according to claim 1, wherein after the first component is loaded into the accommodating chamber, the method further comprises:
And coating colloid on the surface of the first element, which is away from the first medium layer.
6. The method for manufacturing a circuit board according to claim 1, further comprising:
And adding layers on one side of the third circuit layer and/or the fourth circuit layer, which is away from the first medium layer, to form at least one fifth circuit layer, wherein each fifth circuit layer is electrically connected with the third circuit layer and/or the fourth circuit layer.
7. The method of manufacturing a circuit board according to claim 1, wherein the specific step of removing the metal protection layer comprises:
Covering a dry film on the surface of the third circuit layer, which is away from the first circuit layer;
Developing the dry film by exposure to light, removing the metal protective layer exposed to the dry film, and
And removing the dry film.
8. The circuit board manufactured by the manufacturing method of the circuit board according to claim 1, comprising:
a wiring substrate, the wiring substrate comprising:
The first dielectric layer comprises a first surface and a second surface which are oppositely arranged;
A first circuit layer embedded in and exposed to the first surface of the first dielectric layer;
at least one second dielectric layer arranged on the second surface of the first dielectric layer;
A second circuit layer arranged on one side of each second dielectric layer facing away from the first dielectric layer, and
The third circuit layer is arranged on the first surface and is in contact with part of the first circuit layer, and the third circuit layer is electrically connected with the first circuit layer;
The accommodating cavities penetrate through each second medium layer, the projections of the accommodating cavities cover part of the first circuit layers along the stacking direction of the circuit substrates, and the second circuit layers are positioned at the outer sides of the accommodating cavities;
at least one first element, each first element is arranged in the accommodating cavity, and each first element is electrically connected with the third circuit layer;
At least one second element, each of which is disposed in the accommodating cavity and disposed on the first element;
a third dielectric layer arranged on one side of the second circuit layer facing away from the first circuit layer and extending into the accommodating cavity, and
And the fourth circuit layer is arranged on one side of the third dielectric layer, which is away from the second circuit layer, and is electrically connected with the second element.
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| CN202110694227.0A CN115515325B (en) | 2021-06-22 | 2021-06-22 | Circuit board and method for manufacturing the same |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104244582A (en) * | 2013-06-13 | 2014-12-24 | 宏启胜精密电子(秦皇岛)有限公司 | Embedded type high-density interconnection printed circuit board and manufacturing method of embedded type high-density interconnection printed circuit board |
| CN111867248A (en) * | 2019-04-24 | 2020-10-30 | 宏启胜精密电子(秦皇岛)有限公司 | Circuit board and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004235222A (en) * | 2003-01-28 | 2004-08-19 | Airex Inc | Method for manufacturing printed wiring board |
| KR100524963B1 (en) * | 2003-05-14 | 2005-10-31 | 삼성전자주식회사 | Manufacturing method and apparatus for semiconductor device having metal resistor and metal wire |
| CN111434190B (en) * | 2018-11-09 | 2022-08-09 | 庆鼎精密电子（淮安）有限公司 | Rigid-flexible circuit board and manufacturing method thereof |
| CN112218450A (en) * | 2019-07-12 | 2021-01-12 | 宏启胜精密电子(秦皇岛)有限公司 | Circuit board and manufacturing method thereof |
| CN110708897A (en) * | 2019-10-21 | 2020-01-17 | 北大方正集团有限公司 | Circuit board manufacturing method and circuit board |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104244582A (en) * | 2013-06-13 | 2014-12-24 | 宏启胜精密电子(秦皇岛)有限公司 | Embedded type high-density interconnection printed circuit board and manufacturing method of embedded type high-density interconnection printed circuit board |
| CN111867248A (en) * | 2019-04-24 | 2020-10-30 | 宏启胜精密电子(秦皇岛)有限公司 | Circuit board and manufacturing method thereof |
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