TWI857750B - Thermoelectric separation power module with bidirectional heat dissipation ceramic substrate and its manufacturing method - Google Patents

Abstract

A thermoelectric separation power module with a bidirectional heat dissipation ceramic substrate and a manufacturing method thereof, comprising: two double-sided metal-clad ceramic substrates, power transistor grains and insulating sealant, each double-sided metal-clad ceramic substrate comprises a ceramic insulating layer, a three-dimensional conductive layer on the ceramic insulating layer facing each other to form a circuit, and a metal heat conductive layer opposite to the three-dimensional conductive layer and insulated from each other, wherein each power transistor The electrode of the body crystal grain is conductively connected to the three-dimensional conductive layer, and the upper and lower surfaces are respectively thermally connected to each three-dimensional conductive layer. The three-dimensional conductive layer is also equipped with circuit components, wherein at least one conductive column is formed between the circuits of each three-dimensional conductive layer. Finally, the power transistor crystal grain and the conductive column are completely covered with insulating sealant. The bidirectional heat dissipation ceramic substrate of the present invention has good thermal conductivity, simple manufacturing process and low cost.

Description

Thermoelectric separation power module with bidirectional heat dissipation ceramic substrate and manufacturing method

The present invention is a thermoelectric separation power module and a manufacturing method, in particular, a thermoelectric separation power module and a manufacturing method with a bidirectional heat dissipation ceramic substrate.

Over the past few decades, power semiconductors such as MOSFET and IGBT have been continuously innovating in materials, structures, and circuit designs, allowing the performance of electronic products to grow steadily in line with Moore's Law. However, traditional transistors made mainly of silicon (Si), although the raw materials are easy to obtain and the process technology is mature, are gradually unable to meet the needs of today's electric vehicles and 5G communication technologies due to the physical limitations of the silicon material itself. Taking electric vehicles as an example, the inverter inside the vehicle drives the three-phase motor by outputting control signals. The inverter itself can be regarded as a power device module, which needs to use a microcontroller unit (MCU) to transmit control signals to the gate of the power transistor, and further perform pulse width modulation (PWM) on the DC power output from the battery to allow the high-frequency, high-current AC signal to be conducted between the source and drain of the power transistor in the inverter, ultimately providing a three-phase motor for high-power output.

The input signals of the above three-phase motor are three AC signals with a phase difference of 120 degrees. The frequency of the AC signal determines the speed of the motor, and the current of the AC signal directly affects the magnetic force driving the motor. Therefore, it can be understood that high-power electric vehicle motors require high-frequency and high-current AC input signals. For traditional first and second generation semiconductors, for example, silicon has an energy band width of 1.12eV and a breakdown electric field of 0.3MV/cm, which is prone to breakdown under high voltage and high current environments. Third generation semiconductors such as GaN not only have a better energy band width (3.4eV) and a breakdown electric field (3.3MV/cm) to meet high power requirements, but also can use the two-dimensional electron gas (2DEG) generated at the interface due to polarization differences in heterostructures (AlGaN/GaN heterostructure) to form high electron mobility transistors (HEMT), which are very suitable for high frequency signal use. It can be seen that components based on gallium nitride materials can be used in high-frequency, high-power, radiation-resistant and high-temperature environments, including high-power output amplifiers for 5G communication base stations, military radars, rechargeable batteries, and automotive energy management systems.

On the other hand, although the microcontroller (MCU) can transmit the logic signal to the power transistor gate for switching control, when the signal tends to high frequency, the power transistor will gradually be unable to keep up with the switching speed of the signal; the reason is that the gate of the power transistor can be regarded as a capacitor. For a normally off power transistor, if the gate is not given enough charge, the source and drain cannot be turned on; therefore, for high-frequency signals, the gate requires a larger signal input to meet real-time changes. In practice, this problem can be solved by amplifying the control signal in advance through a gate driver chip.

General gate driver chips can be divided into on chip or discrete module: the former can save a lot of space by directly integrating the gate driver chip and power semiconductor into a single chip, but it has to face the problem that the high temperature generated by the power transistor may have an adverse effect on the gate driver chip and the microcontroller; although the latter can properly perform thermal separation, the transmission of high-frequency signals is easily distorted due to parasitic inductance effects due to overly long lines. The impact of the above two problems on power semiconductors cannot be ignored. Once the gate signal produces phase delay, distortion and other problems, it will directly affect the modulation accuracy of the power semiconductor. Taking the three-phase motor used in electric vehicles as an example, if the three input AC signals cannot maintain a 120-degree phase difference with each other, the motor's operating efficiency will be significantly affected.

At present, a power transistor module as shown in FIG. 1 has been proposed. Since gate drivers, shunt detectors and other circuit components need to be packaged together, and multiple power transistor components need to be connected in series and parallel, the connection path is quite complicated. It is necessary to use multiple three-dimensional lead frames 8 that partially overlap each other to successfully provide multiple power transistor chips 7 for connection. Sometimes, it is even necessary to perforate the upper and lower ceramic substrates and manufacture circuits on the outside for connection. On the one hand, during the manufacturing process, the overall structure is complex and there is an overlapping design between the lead frames. The multi-channel three-dimensional lead frame 8 must be processed multiple times in a bottom-up order. When the circuit components and the lower three-dimensional lead frame are already welded at the bottom, the upper three-dimensional lead frame and the welded components are installed at the top. It is necessary to use a low-temperature processing material whose operating temperature is lower than the temperature that the existing components and the solder that has been welded can withstand. Therefore, it is quite inconvenient to arrange the order of the manufacturing processes. In particular, this process is not a semiconductor process. Considering that the total height of the entire package is often only 2mm, it is extremely difficult to ensure that the 3D lead frame and circuit components above can be accurately aligned after the 3D lead frame and circuit components below are properly installed. The installation process is not only slow, but also the difficulty of operation is unnecessarily increased, and the output efficiency and product yield of the product are limited. In addition, the heat conduction area and cross-sectional area of the lead frame are extremely limited, and it is impossible to perform high-efficiency heat dissipation over a large area. Especially when heat energy continues to accumulate, the performance and life of each circuit component packaged in the same module will be affected.

The features and advantages of the present invention are described in detail in the following implementation method. The content is sufficient for anyone familiar with the relevant technology to understand the technical content of the present invention and implement it accordingly. According to the content disclosed in this specification, the scope of the patent application and the drawings, anyone familiar with the relevant technology can easily understand the relevant purposes and advantages of the present invention.

The main purpose of the present invention is to provide a thermoelectric separation power module with a two-way heat dissipation ceramic substrate, ensuring that the upper and lower ceramic insulation layers do not need to be perforated at all, and the metal layer coated on the outer side of the ceramic insulation layer fully conducts heat, providing complete and good heat dissipation efficiency.

Another purpose of the present invention is to provide a thermoelectric separation power module with a bidirectional heat dissipation ceramic substrate. Through the multi-layer three-dimensional conductive layer, the thermal expansion difference between the ceramic insulation layer and the metal above is effectively restrained, reducing the risk of structural degradation caused by interlayer peeling and ensuring the service life of the module.

Another purpose of the present invention is to provide a thermoelectric separation power module with a bidirectional heat dissipation ceramic substrate. The metal layer coated on the inner side of the upper and lower ceramic insulation layers simultaneously performs the functions of electrical and thermal conductivity. Through the precision three-dimensionally formed metal conductive layer, the power transistor grains and circuit components sandwiched between the ceramic substrates can be installed at a time. The manufacturing process is simple and easy to align, which improves the output efficiency and product yield.

The present invention also provides a thermoelectric separation power module with a bidirectional heat dissipation ceramic substrate, which uses an insulating sealant to completely cover the power transistor grains and conductive posts between the metal-clad ceramic plates, so that the high heat generated by the power transistor grains is mainly conducted from the upper and lower ceramic insulation layers and the metal heat conductive layer, which is difficult to interfere with other circuit components, thereby achieving a thermoelectric separation effect.

Another purpose of the present invention is to provide a method for manufacturing a thermoelectric separation power module with a bidirectional heat dissipation ceramic substrate, using a precisely positioned three-dimensional conductive layer to accurately connect the circuits of the upper and lower three-dimensional conductive layers, so that the manufacturing process is simple and precise, and the manufacturing yield and output efficiency are improved.

To achieve the above-mentioned purpose, the present invention is a thermoelectric separation power module with a bidirectional heat dissipation ceramic substrate, a first double-sided metal-clad ceramic substrate, including a first ceramic insulating layer, a first three-dimensional conductive layer formed on the aforementioned ceramic insulating layer, and a first metal heat conductive layer formed on the aforementioned first ceramic insulating layer opposite to the aforementioned first three-dimensional conductive layer and insulated from the aforementioned first three-dimensional conductive layer, wherein the aforementioned first three-dimensional conductive layer is formed with a plurality of layers with different heights; a second double-sided metal-clad ceramic substrate parallel to the above-mentioned first double-sided metal-clad ceramic substrate, including a second ceramic insulating layer, a first three-dimensional conductive layer formed on the aforementioned ceramic insulating layer, and a first metal heat conductive layer formed on the aforementioned first ceramic insulating layer opposite to the aforementioned first three-dimensional conductive layer and insulated from the aforementioned first three-dimensional conductive layer. A second three-dimensional conductive layer on the ceramic insulating layer, and a second metal thermal conductive layer formed on the second ceramic insulating layer opposite to the second three-dimensional conductive layer and insulated from the second three-dimensional conductive layer, wherein the second three-dimensional conductive layer is formed with a plurality of layers with different heights; and at least one power transistor grain, each of the power transistor grains is respectively formed with a plurality of electrodes, each of the electrodes is respectively conductively connected to the first three-dimensional conductive layer or the second three-dimensional conductive layer, and the upper and lower surfaces of each of the power transistor grains are respectively thermally connected to the first three-dimensional conductive layer and the second three-dimensional conductive layer.

According to the above disclosure, the present invention provides a method for manufacturing a thermoelectric separation power module with a double-directional heat dissipation ceramic substrate. The thermoelectric separation power module with a double-directional heat dissipation ceramic substrate includes a first double-sided metal-clad ceramic substrate and a second double-sided metal-clad ceramic substrate parallel to the first double-sided metal-clad ceramic substrate. The first double-sided metal-clad ceramic substrate includes a first ceramic insulating layer, a first three-dimensional conductive layer formed on the ceramic insulating layer, and a first metal heat conductive layer formed on the first ceramic insulating layer opposite to the first three-dimensional conductive layer and insulated from the first three-dimensional conductive layer. The second double-sided metal-clad ceramic substrate includes a second ceramic insulating layer, a second three-dimensional conductive layer formed on the ceramic insulating layer, and a second metal heat conducting layer formed on the second ceramic insulating layer opposite to the second three-dimensional conductive layer and insulated from the second three-dimensional conductive layer. The manufacturing method comprises the following steps: a) forming a circuit on the first three-dimensional conductive layer, wherein the first three-dimensional conductive layer is formed with a plurality of layers with different heights; b) mounting at least one power transistor die on the circuit of the first double-sided metal-clad ceramic substrate, so that the power transistor die is heat-conductingly connected to the first three-dimensional conductive layer; c) heat-conductingly bonding the second double-sided metal-clad ceramic substrate to the power transistor die with the second three-dimensional conductive layer facing the power transistor die; and d) injecting insulating glue to completely cover and encapsulate the power transistor die. Wherein step a) may further include the following sub-steps: a1) forming a seed layer on the aforementioned ceramic insulating layer; and a2) sequentially forming a plurality of thickening layers on the aforementioned seed layer.

Since the first and second heat dissipation ceramic substrates are based on the first and second ceramic insulation layers in the center and are covered with metal on both sides, but the ceramic insulation layer does not need to be perforated, only the inner sides facing each other are used as the conductive circuit and bear the responsibility of heat conduction, while the metal coating on the outer side of the ceramic insulation layer is completely insulated from the inner circuit, there is no circuit, and it only bears the role of heat conduction or Further connect the heat sink fins and other structures; thereby, the structure of the ceramic substrate is simple and easy to manufacture. Once the heat sink fins or heat pipes are installed, they can be installed more conveniently and more tightly combined with each other to achieve a good thermal conductivity effect; in particular, the inner three-dimensional conductive layer can be manufactured by gradually increasing the thickness. Not only is the manufacturing process mature and the precision is excellent, but the two heat sinks are also The bonding of thermal ceramic substrates has also become simple, accurate and reliable; in particular, because of the various layers of different heights, on the one hand, the problem of thermal stress can be effectively solved, so that the metal circuit through which the large current passes has a thinner seed layer, so that the part connected to the ceramic insulating layer can exert ductility, and the thickening layer above the seed layer can have a thicker height than the seed layer, so that the material of the metal conductive layer is simple, and high-priced metals such as molybdenum can be avoided, reducing manufacturing costs; between the two heat dissipation ceramic substrates, the power transistor grains and the surrounding circuit components are completely encapsulated with insulating sealant, so that the power module disclosed by the present invention can achieve thermal and electrical separation at the same time, and effectively improve the product yield and output efficiency, achieving the above-mentioned effects of this invention.

1. 1’: The first double-sided metal-ceramic substrate

10, 10’: First ceramic insulating layer

12, 12’, 12”: The first three-dimensional conductive layer

12D, 12D’: Drain lead-out section

12G, 12G’: Gate lead section

12S, 12S’: Source lead-out section

14, 14’: First metal thermal conductive layer

120: First circuit

120”: Conducting circuit

122”, 322: Conductor column

124’: Corresponding block

2, 2’, 2”: Power transistor chips

20D, 20D’, 20D”: Drain

20G, 20G’, 20”: Gate

20S, 20S’, 20S”: Source

3, 3’: The second double-sided metal-ceramic substrate

30, 30’: Second ceramic insulation layer

32, 32”: Second stereo conductor layer

320: Second circuit

321: Gate pin

321’: First level

322’: Second level

34, 34’: Second metal thermal conductive layer

5, 5”: Insulation sealant

60~63: Steps

Figure 1 is a schematic side view of a heat dissipation structure of a conventional power transistor module.

Figure 2 is a perspective view of the main structure of the first preferred embodiment of the power transistor module of the present invention, illustrating how to use a large area of thermal conductive contact to achieve good heat dissipation and module flattening effects.

Figures 3 and 4 are partial side views of the embodiment of Figure 2, illustrating the bonding relationship between the first and second double-sided metal-ceramic substrates and the power transistor grains.

FIG5 is a perspective view of the main structure of the second preferred embodiment of the power transistor module of the present invention, illustrating how to use a large area of thermal conductive contact to achieve good heat dissipation and module flattening effect.

Figures 6 and 7 are partial side views of the embodiment of Figure 5, illustrating the bonding relationship between the first and second double-sided metal-ceramic substrates and the power transistor grains.

Figure 8 is a schematic side view of the main structural part of the third preferred embodiment of the power transistor module of the present invention, illustrating the structure of each double-sided metal ceramic substrate and power transistor grain.

FIG9 is a schematic diagram of the top double-sided metal-ceramic substrate of the embodiment of FIG8, which illustrates the three-dimensional conductive layer circuit pattern corresponding to the positions of the poles of the power transistor grain and the heat conduction block on the top of the power transistor grain.

FIG10 is a schematic diagram of a series/parallel circuit of multiple power transistor chips in the embodiment of FIG8 .

Figure 11 is a flow chart of a preferred embodiment of the manufacturing method of the present invention.

The relevant technical content, features and effects of this case will be clearly presented with the detailed description of the preferred embodiment with reference to the drawings. The same components in each embodiment will be marked with similar numbers.

The first preferred embodiment of the thermoelectric separation power module of the power transistor module of the present invention is shown in Figures 2 to 4, and mainly includes a first double-sided metal-clad ceramic substrate 1, a power transistor grain 2 and a second double-sided metal-clad ceramic substrate 3, wherein the first and second double-sided metal-clad ceramic substrates 1, 3 are respectively based on a ceramic insulating layer 10, 30 with a thickness of 0.1 to 1 mm, and metal is respectively coated on both sides of the first and second ceramic insulating layers 10, 30, in this example, copper is used as an example. Since the first and second ceramic insulating layers 10, 30 are complete and non-perforated structures during future assembly, the circuit portion is confined to the inner sides facing each other, and the copper coating on the outer sides of the first and second ceramic insulating layers 10, 30 is only used for heat dissipation, and even further heat sink fins (not shown) are installed to provide large-area heat conduction. Even if a device such as a heat sink fin is to be installed, there is no need to specially design the shape and structure of the outer copper-clad layer and the heat sink fin, so that the heat dissipation contact area is large, the structure is simple and easy to manufacture, and the combination is easy and stable. Therefore, the copper-clad layer on the outer side of the first and second ceramic insulation layers 10 and 30 is defined as the first metal heat conductive layer 14 and the second metal heat conductive layer 34 respectively.

As for the copper-clad layers facing each other on the inner sides of the first and second ceramic insulating layers 10, 30, they need to bear the conductive circuit structure, and a part of the area thereof helps to conduct the heat generated by the power transistor grain 2 to the corresponding ceramic insulating layer and the metal heat conductive layer. Therefore, the metal-clad layers facing each other on the inner sides of the first and second ceramic insulating layers 10, 30 are defined as the first three-dimensional conductive layer 12 and the second three-dimensional conductive layer 3 respectively. 2. Similarly, in step 60 of FIG. 11, the first three-dimensional conductive layer 12 and the second three-dimensional conductive layer 32 are formed according to the pre-planned method, such as sputtering, on the aforementioned inner sides of the first and second ceramic insulating layers 10 and 30 to form a seed layer, layout the circuit pattern, and then gradually thicken the layers, by forming a plurality of thickening layers of different heights on the seed layer, to form the first circuit 120 and the second circuit 320. And as shown in FIG. 3, the first three-dimensional conductive layer 12 in this example also includes a source pad and a drain pad formed simultaneously in the circuit 120 for conducting the matching power transistor grain 2.

Then in step 61, the power transistor die 2, the gate driver (not shown) and other circuit components will be mounted on the bottom and top circuits in this example, respectively, and the source, drain and gate of the power transistor die 2 will be connected to the source pad, drain pad and gate pad of the first circuit 120 on the bottom side or the second circuit 320 on the top side, respectively. The power transistor grain 2 in this example is a GaN transistor. Since the present invention directly uses unpackaged bare crystal grains, the drain 20D of the power transistor grain 2 in this example is located at the lower side of the figure, and the source 20S and the gate 20G are located at the upper side. Since the source and gate of the power transistor grain 2 are located at the upper side, the source 20S and the gate 20G are guided through the second three-dimensional conductive layer 32 of the second double-sided metal-ceramic substrate 3 above, and are connected to the source lead-out part 12S and the gate lead-out part 12G respectively; the three-dimensional conductive layer 12 below is formed with a pad for the drain 20D to be soldered and mounted, and is conductively connected to the drain lead-out part 12D.

Since the thickness of the bare die is only 50 to 100 μm, in this example, the source 20S and the gate 20G are respectively guided to different blocks of the first three-dimensional conductive layer 12 through the source pin (not labeled) and the gate pin 321 of the second three-dimensional conductive layer 32 above, and then to the source lead-out portion 12S and the gate lead-out portion 12G welded on the first three-dimensional conductive layer 12. Not only the cross section of the guide path The large area is conducive to controlling the current density during the transmission process, and the overall height of the module is quite thin, especially the power transistor die is sandwiched between the double-sided metal-clad ceramic substrates. As long as the second double-sided metal-clad ceramic substrate has a sufficient top area for the surface mounting machine to absorb, it can be easily absorbed and moved. In particular, the circuit layer area of the first and second three-dimensional conductive layers 12 and 32 is large, and other circuit components such as gate drivers and shunt detectors can also be installed in the module and surface mounted together. Because the three-dimensional conductive layer can be thickened to make the cross-sectional area of the current much larger than that of the general lead frame, even if the source and drain need to provide a large current of tens of amperes, the current density in the three-dimensional conductive layer can still be greatly reduced, and the heat generation is further reduced.

Of course, the circuit components mentioned here are not limited to gate drivers for driving the power transistor die 2 to conduct or disconnect, and may also include other thermistors or other matching components such as in this example. Then, in step 62, the second double-sided metal-ceramic substrate 3 is placed on the first double-sided metal-ceramic substrate 1 below, the power transistor die 2 and other circuit components, so that the first and second double-sided metal-ceramic substrates 1 and 3 are combined in a manner that the first and second three-dimensional conductive layers 12 and 32 face each other, and the first metal thermal conductive layer 14 and the second metal thermal conductive layer 34 are respectively arranged on the outer sides of the first and second ceramic insulating layers 10 and 30 and are insulated from the first and second three-dimensional conductive layers 12 and 32.

After the first and second double-sided metal-clad ceramic substrates on the upper and lower sides are butted, step 63 is to inject the insulating sealant 5 to completely cover and encapsulate the power transistor grain 2 between the first and second metal-clad ceramic substrates. Since the thermal conductivity of the insulating sealant here is much lower than that of the ceramic insulating layer and the metal thermal conductive layer, the heat generated by the power transistor grain will be restricted to be conducted toward the upper and lower sides with the smallest thermal resistance, especially when only a single layer is provided. The thickness of the power transistor die and the entire module is only about 2 to 4 mm. Not only are the thermal conductivity coefficients of all structures in the upper and lower directions very high, but the thermal resistance is also very low, making the heat flow transfer smooth and further conducted by structures such as heat sink fins. The heat energy transferred laterally will also be limited by the thermal resistance of the insulating sealant, and will rarely affect other circuit components in the package. It is not easy to accumulate and cause internal temperature rise, thereby achieving the thermoelectric separation emphasized by this invention.

Of course, as those familiar with the art can easily understand, power transistors have many different forms, as shown in the second preferred embodiment of the present invention in Figures 5 to 7. In this embodiment, the source 20S', drain 20D' and gate 20G' of the power transistor grain 2' are all formed on the same side of the top surface of the grain. Therefore, in this embodiment, the first three-dimensional conductive layer 12' on the bottom side of the grain will have a corresponding block 124' that is simply used for heat conduction to help transfer the heat energy generated by the grain upward to the ceramic insulation layer and metal thermal conductive layer above. As for the circuit on the top side, it includes a source pad, a drain pad and a gate pad for conducting from the above-mentioned source 20S', drain 20D' and gate 20G', and a first layer 321' and a second layer 322' as a conducting column, thereby forming a transmission path with a large transmission cross-section to conduct the current from the source 20S', drain 20D' and gate 20G'. The input and gate signals are connected to different blocks on the first three-dimensional conductive layer 12', and the source lead-out portion 12S', the drain lead-out portion 12D' and the gate lead-out portion 12G' are respectively welded to the above-mentioned different blocks to achieve transmission, while the block 124' in the first three-dimensional conductive layer 12' is not responsible for conduction but is dedicated to the bottom and top welding and heat conduction of the power transistor grain. Similarly, based on the fact that there are no through holes inside and outside the first and second ceramic insulating layers 10', 30', the first and second metal thermal conductive layers on the outside have simple and flat structures, which is convenient for good thermal conductive bonding when other thermal conductive structures are to be further set.

Since the power transistor grain 2' itself generates high heat during operation, the present invention simultaneously contacts the power transistor grain 2' over a large area through the first and second three-dimensional conductive layers 12', 32' of the first and second double-sided metal-ceramic substrates 1', 3' on the upper and lower sides, and also conducts heat energy through the first and second ceramic insulating layers 10', 30' and the first and second metal heat-conducting layers 14', 34' over a large area, ensuring that the heat energy inside the module is efficiently conducted away without rapidly accumulating inside to cause a temperature rise, which not only makes the overall module operating environment good, but also effectively prolongs the service life of the power transistor grain and other circuit components inside. Especially in the case of a structure where the three-dimensional conductive layer is thickened by stacking, the thickness of the copper layer at the pad where the large current passes can be precisely increased, which can reduce the current density compared to the previous lead frame. In addition, in terms of material, part of the thickened layer can also be replaced with molybdenum-copper alloy, tungsten-copper alloy or molybdenum-copper-molybdenum metal stacking to limit the thermal expansion of the single copper and solve the thermal stress problem.

As further shown in the third preferred embodiment of the present invention in FIG. 8 and FIG. 9 , multiple power transistor grains 2” may be installed in the same module, and the source 20S” and the drain 20D” of each power transistor grain 2” are respectively led out from the source pad and the drain pad of the bottom circuit 120”. Similarly, the gate pad in this example is also connected in parallel to the first three-dimensional conductive layer 12” on the upper side and driven by the gate driver together. Obviously, since in this example, four power transistor chips are used as a group as shown in Figures 9 and 10, the four chips are connected in parallel with each other, and are connected in series with another group of four power transistor chips (not shown), the source, drain and gate of each chip must form a jumper structure, which cannot be formed on a single plane and must be staggered through a three-dimensional circuit. The shunt detector is a chip resistor, which detects the output current of each power transistor chip 2" through a conductive circuit 120" and a conductive column 122". The filling method of the insulating sealant 5" is the same as above and will not be elaborated. It is worth noting that at this time, not only the conductive pillars are electrically connected to the corresponding circuits on the upper and lower sides, but in this example, a second three-dimensional conductive layer 32" is cleverly set in the top three-dimensional conductive layer to simply conduct heat energy above the power transistor die 2, where the top of the power transistor die without any current flowing through it will also abut against the corresponding heat conduction block of the upper circuit, pressing and tightly conducting heat to the power transistor die, so that the heat energy generated by the power transistor die can be effectively conducted from the top in addition to the first three-dimensional conductive layer below.

Of course, those familiar with the technical field can easily understand that the above embodiments are only examples and are not limiting. For example, the electrode configuration of the power transistor grain can also be located on the top and bottom sides respectively, not limited to a single side. In addition, the conductive column is not necessarily formed at the same time as the aforementioned circuit, and the formation of the circuit is not limited to the use of sputtering seed layer and then thickening. As long as different hierarchical structures of different heights can be achieved, the installation and connection requirements of power transistors and other circuit components can be met. Since the overall height of the module is quite thin, especially when sandwiched between double-sided metal-clad ceramic substrates, as long as there is enough top area for surface mounting machine to absorb, it can be easily absorbed and moved, and surface mounted together with other circuit components.

As can be seen from the above, since the space between the two double-sided metal-clad ceramic substrates is very thin, and the three-dimensional conductive layers facing each other have a large area of conductive connection or contact above and below the power transistor grains, the heat generated by the power transistor grains can be smoothly discharged through the insulating ceramic layer with a high thermal conductivity coefficient and the thermal conductive metal layer, so as to maintain the temperature of the working environment not too high. In addition, in order to form layers of different heights on the three-dimensional conductive layer, the three-dimensional conductive layer responsible for conductive connection can choose an appropriate thickness, such as direct copper coating, or alloy, stacking method, which not only effectively reduces the current density, but also reduces thermal stress damage. In addition to the good heat conduction channels in the up and down directions, the sides of the power transistor die are completely covered by the insulation sealant with poor thermal conductivity, so that the heat energy cannot easily affect other circuit components, which is significantly better than the previous wire frame design. Most importantly, due to the simple structure and precise structural assembly, the manufacturing cost, output efficiency and product yield can be significantly improved.

The above embodiments are only for illustrative purposes to illustrate the principle and efficacy of the present invention, and are not intended to limit the present invention. Anyone familiar with this technology may modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the scope of the patent application described below.

1: The first double-sided metal-ceramic substrate

10: First ceramic insulation layer

12: The first three-dimensional conductive layer

12D: Drain lead

12G: Gate lead section

12S: Source lead-out section

120: First circuit

2: Power transistor chips

20G: Gate

20S: Source

3: The second double-sided metal-ceramic substrate

5: Insulation sealant

Claims (8)

A thermoelectric separation power module with a bidirectional heat dissipation ceramic substrate comprises: a first double-sided metal-clad ceramic substrate, comprising a first ceramic insulating layer, a first three-dimensional conductive layer formed on the ceramic insulating layer, and a first metal heat conductive layer formed on the first ceramic insulating layer opposite to the first three-dimensional conductive layer and insulated from the first three-dimensional conductive layer, wherein the first three-dimensional conductive layer is formed with a plurality of layers with different heights; a second double-sided metal-clad ceramic substrate parallel to the first double-sided metal-clad ceramic substrate, comprising a second ceramic insulating layer, a first three-dimensional conductive layer formed on the ceramic insulating layer, and a first metal heat conductive layer formed on the first ceramic insulating layer. A second three-dimensional conductive layer on the first three-dimensional conductive layer, and a second metal heat conductive layer formed on the second ceramic insulating layer opposite to the second three-dimensional conductive layer and insulated from the second three-dimensional conductive layer, wherein the second three-dimensional conductive layer is formed with a plurality of layers with different heights; and at least one power transistor grain, each of the power transistor grains is respectively formed with a plurality of electrodes, each of the electrodes is respectively conductively connected to the first three-dimensional conductive layer or the second three-dimensional conductive layer, and the upper and lower surfaces of each of the power transistor grains are respectively thermally connected to the first three-dimensional conductive layer and the second three-dimensional conductive layer. The thermoelectric separation power module with a dual-directional heat dissipation ceramic substrate as described in claim 1 further includes an insulating sealant for completely encapsulating the power transistor grains between the dual-sided metal-ceramic substrates. As described in claim 1, the thermoelectric separation power module with a bidirectional heat dissipation ceramic substrate, wherein the thickness of the aforementioned ceramic insulation layer is 0.1 to 1 mm. Thermoelectric separation power module with bidirectional heat dissipation ceramic substrate as described in claim 1, wherein the power transistor grains are an even number and are divided into at least two groups of grains connected in series, and the power transistor grains in each of the above-mentioned grain groups are connected in parallel. The thermoelectric separation power module with a bidirectional heat dissipation ceramic substrate as described in claim 1 further includes a gate driver mounted on the aforementioned first three-dimensional conductive layer or the aforementioned second three-dimensional conductive layer and used to drive the aforementioned power transistor grain. As described in claim 1, the thermoelectric separation power module with a bidirectional heat dissipation ceramic substrate, wherein at least one conductive column is formed between the first three-dimensional conductive layer and the second three-dimensional conductive layer. A method for manufacturing a thermoelectric separation power module with a double-directional heat dissipation ceramic substrate, wherein the thermoelectric separation power module with a double-directional heat dissipation ceramic substrate comprises a first double-sided metal-clad ceramic substrate and a second double-sided metal-clad ceramic substrate parallel to the first double-sided metal-clad ceramic substrate; wherein the first double-sided metal-clad ceramic substrate comprises a first ceramic insulating layer, a first three-dimensional conductive layer formed on the ceramic insulating layer, and a first metal heat conductive layer formed on the first ceramic insulating layer opposite to the first three-dimensional conductive layer and insulated from the first three-dimensional conductive layer; the second double-sided metal-clad ceramic substrate comprises a second ceramic insulating layer, a second three-dimensional conductive layer formed on the ceramic insulating layer, and a first metal heat conductive layer formed on the first ceramic insulating layer opposite to the first three-dimensional conductive layer and insulated from the first three-dimensional conductive layer. The second three-dimensional conductive layer is formed on the second ceramic insulating layer and is insulated from the second three-dimensional conductive layer. The manufacturing method includes the following steps: a) forming a circuit on the first three-dimensional conductive layer, and the first three-dimensional conductive layer is formed with a plurality of layers with different heights; b) mounting at least one power transistor die on the circuit of the first double-sided metal-ceramic substrate, so that the power transistor die is thermally connected to the first three-dimensional conductive layer; c) thermally bonding the second double-sided metal-ceramic substrate to the power transistor die with the second three-dimensional conductive layer facing the power transistor die; and d) injecting insulating glue to completely cover and encapsulate the power transistor die. The method for manufacturing a thermoelectric separation power module with a bidirectional heat dissipation ceramic substrate as described in claim 7, wherein the aforementioned step a) further includes the following sub-steps: a1) forming a seed layer on the aforementioned ceramic insulation layer; and a2) sequentially forming a plurality of thickening layers on the aforementioned seed layer.

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