WO2018047485A1

WO2018047485A1 - Power module and inverter device

Info

Publication number: WO2018047485A1
Application number: PCT/JP2017/026653
Authority: WO
Inventors: 清太岩橋
Original assignee: ローム株式会社
Priority date: 2016-09-06
Filing date: 2017-07-24
Publication date: 2018-03-15
Also published as: JPWO2018047485A1

Abstract

A power module (10) is provided with: a lower ceramic substrate (21D); a semiconductor device Q1 which is mounted on the lower ceramic substrate (21D) and generates heats during operation; an upper ceramic substrate (21U) disposed on the semiconductor device Q1 so as to face the lower ceramic substrate (21D); a bridge section (35C) which transmits an electrical signal and is connected to an electrode pattern (24D2), one end of which is disposed on the semiconductor device Q1 and the other end of which is formed on the lower ceramic substrate (21D); and a post section (35T), one end of which is disposed on the semiconductor device Q1 and the other end of which is connected to the upper ceramic substrate (21U), the post section (35T) conducting heat from the semiconductor device Q1 to a second insulation substrate (22U). A power module and inverter device capable of efficiently dissipating heat are provided.

Description

Power module and inverter device

This embodiment relates to a power module and an inverter device.

As one of power modules, a power semiconductor module in which a power element (chip) including a semiconductor device such as an insulated gate bipolar transistor (IGBT) is molded with a resin has been known. Yes. Since the semiconductor device generates heat in the operation state, it is general to dissipate heat by disposing a heat sink or a cooler such as a heat sink or fin on the back surface side to cool the semiconductor device.

In particular, in a double-sided cooling structure in which coolers are arranged on both upper and lower sides of a module, a configuration in which a metal block is arranged on a chip to be electrically and thermally connected to the upper surface side is common.

JP 2007-31441 A JP 2013-179229 A JP 2010-140969 A

However, in this double-sided cooling structure, when the electrical and thermal paths are the same path, heat generated by Joule heat hinders heat dissipation and deteriorates the characteristics.

This embodiment provides a power module and an inverter device that can efficiently dissipate heat.

According to one aspect of the present embodiment, a first insulating substrate, a semiconductor device mounted on the first insulating substrate and generating heat during operation, and the semiconductor device facing the first insulating substrate A second insulating substrate disposed; one end disposed on the semiconductor device; the other end connected to an electrode pattern formed on the first insulating substrate to transmit an electrical signal; and the semiconductor There is provided a power module including one end disposed on a device, the other end connected to the second insulating substrate, and a heat conduction path layer that conducts heat of the semiconductor device to the second insulating substrate.

According to another aspect of the present embodiment, a first insulating substrate having a front surface and a back surface, a semiconductor device mounted on the front surface side of the first insulating substrate and generating heat during operation, and the semiconductor device A second insulating substrate disposed opposite to the first insulating substrate and having a front surface and a back surface; and a second insulating substrate disposed on a surface opposite to the surface facing the semiconductor device of the second insulating substrate. 1 cooler, one end disposed on the semiconductor device, the other end connected to an electrode pattern formed on the first insulating substrate and transmitting an electrical signal, and one end on the semiconductor device A heat conduction path layer that is connected to the second insulating substrate and conducts heat of the semiconductor device to the first cooler, wherein the electrical conduction path layer is the heat conduction path layer. The electrode pattern from the side Power module comprising a block structure integral to be connected is provided.

According to another aspect of the present embodiment, the first insulating substrate, the semiconductor device mounted on the first insulating substrate and generating heat during operation, the semiconductor device on the first insulating substrate, A second insulating substrate disposed oppositely, a first cooler disposed on a surface of the second insulating substrate opposite to the surface facing the semiconductor device, and one end disposed on the semiconductor device; The other end side is connected to the electrode pattern formed on the first insulating substrate and transmits an electric signal, and the second insulating substrate is laminated on the second insulating substrate side of the electric conduction layer. There is provided a power module including a heat conduction path layer connected to a substrate and conducting heat of the semiconductor device to the first cooler.

Further, according to another aspect of the present embodiment, an inverter device that performs power conversion using a power module in which a circuit including a semiconductor device connected between a power supply terminal and a reference terminal is formed, The power module includes a first insulating substrate, the semiconductor device mounted on the first insulating substrate and generating heat during operation, and a surface opposite to the surface facing the semiconductor device on the semiconductor device, A second insulating substrate disposed opposite to the first insulating substrate, one end connected to an electrode pad formed on the semiconductor device, and the other end connected to an electrode pattern formed on the first insulating substrate An electric conduction path layer for passing a current from the semiconductor device to the electrode pattern without passing through the second insulating substrate, one end being disposed on the semiconductor device, and the other end being the front side A heat conduction path layer connected to the second insulation substrate side and conducting heat of the semiconductor device to the second insulation substrate, at least the semiconductor device, the electrical conduction path layer, and the heat conduction path layer; An inverter device is provided that includes a mold resin that seals a part of each terminal.

According to this embodiment, it is possible to provide a power module and an inverter device that can efficiently dissipate heat.

FIG. 3 is a schematic cross-sectional structure diagram of the power module according to the first embodiment, taken along line II in FIG. (A) The typical plane block diagram which permeate | transmits and shows a part of power module which concerns on 1st Embodiment, (b) The typical circuit representation figure of the power module which concerns on 1st Embodiment. The typical cross-section figure of the power module which concerns on the comparative example 1. FIG. (A) A power module according to a first modification of the first embodiment, which is a schematic cross-sectional structure diagram taken along the line II-II in FIG. 4 (b), and (b) the first embodiment. The typical plane block diagram which permeate | transmits and shows a part of power module which concerns on a 1st modification. FIG. 5A is a power module according to a second modification of the first embodiment, and is a schematic cross-sectional structure diagram taken along the line III-III in FIG. 5B. FIG. 5B is a diagram of the first embodiment. The typical plane block diagram which permeate | transmits and shows a part of power module which concerns on a 2nd modification. (A) A power module according to a third modification of the first embodiment, which is a schematic cross-sectional structure diagram taken along the line IV-IV in FIG. 6 (b), and (b) the first embodiment. The typical plane block diagram which permeate | transmits and shows a part of power module which concerns on a 3rd modification. (A) A power module according to the second embodiment, which is a schematic sectional view taken along line VV in FIG. 7 (b), and (b) one of the power modules according to the second embodiment. The typical plane block diagram which permeate | transmits and shows a part. (A) A power module according to the third embodiment, which is a schematic sectional view taken along line VI-VI in FIG. 8 (b), and (b) one of the power modules according to the third embodiment. The typical plane block diagram which permeate | transmits and shows a part. The typical bird's-eye view block diagram of the power module which concerns on 3rd Embodiment. The figure shown about the specific example of the material of each structure part, thickness, and heat conductivity by making the power module which concerns on 3rd Embodiment into a model case. The power module which concerns on 3rd Embodiment is made into a model case, and the result at the time of simulating about thermal resistance is shown, (a) Simulation at the time of applying SiC (Silicon Carbide) to a post part Results, (b) Simulation results when Cu (Copper) is applied to the post part. The typical cross-section figure of the power module which concerns on the 1st modification of 3rd Embodiment. (A) A power module according to a second modification of the third embodiment, which is a schematic cross-sectional structure diagram taken along line VII-VII in FIG. 13 (b), and (b) the third embodiment. The typical plane block diagram which permeate | transmits and shows a part of power module which concerns on a 2nd modification. (A) A power module according to a third modification of the third embodiment, which is a schematic sectional view taken along line VIII-VIII of FIG. 14 (b), and (b) of the third embodiment. The typical plane block diagram which permeate | transmits and shows a part of power module which concerns on a 3rd modification. FIG. 15A is a power module according to a fourth modification of the third embodiment, and is a schematic cross-sectional structure diagram taken along line IX-IX in FIG. 15B. FIG. 15B is a diagram of the third embodiment. The typical plane block diagram which permeate | transmits and shows a part of power module which concerns on a 4th modification. FIG. 18 is a schematic cross-sectional structure diagram of the power module according to the fourth embodiment, taken along line XX of FIG. (A) The typical plane block diagram which permeate | transmits and shows a part of power module which concerns on 4th Embodiment, (b) The typical circuit representation figure of the power module which concerns on 4th Embodiment. The typical cross-section figure of the power module which concerns on the comparative example 2. FIG. The typical cross-section figure of the power module which concerns on the 1st application example of embodiment. The typical cross-section figure of the power module which concerns on the 2nd application example of embodiment. The typical cross-section figure of the power module which concerns on the 3rd application example of embodiment. The typical cross-section figure of the power module which concerns on the 4th example of application of embodiment. It is an example of the power module which concerns on embodiment, Comprising: The typical circuit representation figure of SiC MOSFET (Metal | Oxide | Semiconductor | Field | Effect | Transistor) of a one-in-one type (1? In? 1) module. It is an example of the power module which concerns on embodiment, and is a detailed circuit representation figure of SiC MOSFET of 1? In? 1 module. It is an example of the power module which concerns on embodiment, Comprising: The typical circuit representation figure of SiC MOSFET of a two-in-one type (2 （in 1) module. FIG. 3 is a schematic cross-sectional structure diagram of a SiC MOSFET that is an example of a semiconductor device applicable to the power module according to the embodiment and includes a source pad electrode SP and a gate pad electrode GP. FIG. 5 is a schematic cross-sectional structure diagram of an IGBT including an emitter pad electrode EP and a gate pad electrode GP, which is an example of a semiconductor device applicable to the power module according to the embodiment. FIG. 4 is a schematic cross-sectional structure diagram of a SiC DI (Double-Implanted) MOSFET, which is an example of a semiconductor device applicable to the power module according to the embodiment. It is an example of the semiconductor device applicable to the power module which concerns on embodiment, Comprising: The typical cross-section figure of SiC T (Trench) MOSFET. The circuit structural example which applied the SiC MOSFET and connected the snubber capacitor between the power supply terminal PL and the ground terminal NL in the circuit structure of the three-phase alternating current inverter comprised using the power module which concerns on embodiment. The typical circuit block diagram which applied SiC MOSFET in the three-phase alternating current inverter comprised using the power module which concerns on embodiment.

Next, the present embodiment will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness of each component and the planar dimensions is different from the actual one. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. In addition, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

Further, the embodiment described below exemplifies an apparatus and method for embodying the technical idea, and does not specify the material, shape, structure, arrangement, etc. of each component. This embodiment can be modified in various ways within the scope of the claims.

[Embodiment]
(First embodiment)
A schematic cross-sectional structure of a power module (hereinafter referred to as “PM”) 10 according to the first embodiment is expressed as shown in FIG. FIG. 1 illustrates a case where the present invention is applied to a 1 in 1 (one in one type) module type PM 10.

Further, FIG. 2A shows a schematic plan configuration showing a part of the PM 10 according to the first embodiment, and FIG. 2B shows a semiconductor device (chip) Q1. A schematic circuit configuration of the PM 10 according to the first embodiment when a SiC MOSFET is applied is shown.

Note that the schematic cross-sectional structure of the PM 10 shown in FIG. 1 is, for example, along the line II in FIG. Further, in the schematic planar pattern configuration of FIG. 2A, the description of the upper cooler (first cooler) 30U and the upper ceramic substrate (second insulating substrate) 21U is omitted. As an example of the semiconductor device Q1, for example, a case where up to five chips (MOSFETs) Q that can be connected in parallel are mounted in one module is illustrated.

Here, in the following description, the upper ceramic substrate 21U side of the PM 10 is defined as the U (UP) side, and the lower ceramic substrate (first insulating substrate) 21D side is defined as the D (DOWN) side. This definition is the same in the description of the comparative example described later.

As shown in FIGS. 1 and 2, the PM 10 according to the first embodiment is disposed on the semiconductor module 20 in which the semiconductor device Q <b> 1 is sealed with the mold resin 33 and the upper surface 20 a on the U side of the semiconductor module 20. An upper cooler 30U and a lower cooler (second cooler) 30D disposed on the lower surface 20b on the D side of the semiconductor module 20 facing the upper surface 20a are provided.

As shown in FIG. 1, the semiconductor module 20 includes an upper ceramic substrate 21U and a lower ceramic substrate 21D that are arranged to face the semiconductor device Q1, and a conduction path layer 35 that is arranged on the upper surface of the semiconductor device Q1. A mold resin 33, a positive power input terminal electrode P, and a negative power input terminal electrode N are provided.

The lower ceramic substrate 21D includes a conductive layer 23D and a conductive layer 24D (first electrode pattern 24D1 and second electrode pattern 24D2) in which a metal foil such as copper (for example, a first copper plate layer) is laminated via an insulating layer 22D. The upper ceramic substrate 21U includes a conductive layer 23U and a conductive layer 24U in which a metal foil such as copper (for example, a second copper plate layer) is laminated via an insulating layer 22U.

In the upper ceramic substrate 21U and the lower ceramic substrate 21D, the first conductive layer 24D and the second conductive layer 24U face each other and are arranged substantially in parallel.

As the upper ceramic substrate 21U and the lower ceramic substrate 21D, for example, an AMB (Active Metal Brazed, Active Metal Bond) substrate or the like is applicable. Alternatively, for example, an organic insulating resin layer may be applied instead of a DBC (Direct Bonding Copper) substrate, a DBA (Direct Brazed Aluminum) substrate, or a DBC substrate.

On the first electrode pattern 24D1, the D side of the semiconductor device Q1 is mounted and the base end portion of the positive power supply input terminal electrode P is joined. On the second electrode pattern 24D2, the negative power supply input terminal electrode The base end portion of N is joined, and the distal end side of the bridge portion (electric conduction path layer) 35C of the conduction path layer 35 is connected.

As shown in FIG. 2B, when an SiC MOSFET is applied, G1 is a gate terminal (gate signal lead terminal) of the semiconductor device Q1, and D1 is a semiconductor device Q1 connected to the positive power supply input terminal electrode P. The drain terminal S1 is a source terminal of the semiconductor device Q1 connected to the negative power supply input terminal electrode N.

Here, the conduction path layer 35 includes, for example, a bridge part 35C for establishing the electrical path C and a post part (thermal conduction path layer) 35T for establishing the heat dissipation path T.

In the PM 10 according to the first embodiment, the base end side of the conductive path layer 35, for example, the base end side of the post portion 35T is connected to the upper surface (U side) of the semiconductor device Q1. Further, the front end side of the post portion 35T is connected to the conductive layer 24U on the D side of the upper ceramic substrate 21U. The post portion 35T has, for example, a columnar electrode structure with a substantially rectangular plane, and has a substantially uniform thickness on the distal end side and the proximal end side.

That is, the conductive path layer 35 extends in a horizontal direction from an I-shaped post portion 35T disposed substantially perpendicular to the upper ceramic substrate 21U or the lower ceramic substrate 21D and, for example, a middle portion of the side surface thereof. And a bridge portion 35C having a substantially L-shaped (or inverted L-shaped) plug structure that is deformed to the lower ceramic substrate 21D side for connection to the second electrode pattern 24D2.

The bridge portion 35 </ b> C is not limited to a substantially L-shape, and may be provided with a substantially U-shaped (or inverted U-shaped) plug structure, for example.

As the conduction path layer 35, for example, the bridge portion 35C and the post portion 35T may have an integrated block structure, or the bridge portion 35C and the post portion 35T may have a separate divided structure. good.

Further, as the conductive path layer 35, for example, a layered structure in which the post part 35T is laminated on the bridge part 35C may be provided.

Further, as the conductive path layer 35, for example, the bridge part 35C and the post part 35T may be provided with the same constituent member, or the bridge part 35C and the post part 35T may be provided with different constituent members.

Further, as the conductive path layer 35, for example, the bridge portion 35C may include one component member or a plurality of component members.

Further, as the conduction path layer 35, for example, the post portion 35T may include one component member, or may include a plurality of component members, or may include a plurality of layer electrode structures.

The post portion 35T includes, for example, any of an I shape, a square shape, an inverted trapezoidal shape, an inverted tapered shape, or an inverted step tapered shape in a cross-sectional view.

As the conductive path layer 35 applicable to the PM 10 according to the first embodiment, for example, the bridge portion 35C includes Cu (Copper), and the post portion 35T includes SiC or Cu.

That is, as the bridge portion 35C, a member having higher electrical conductivity than the post portion 35T, for example, any one of Cu, Al (aluminum), and Ag (silver) is desirable, and the post portion 35T is more than the bridge portion 35C. A member having high thermal conductivity, for example, SiC (silicon carbide), Cu, Ag, carbon, or graphite is desirable.

Further, it is desirable that the conduction path layer 35 has a vertical size A smaller than a horizontal size B, for example, as shown in FIG. This is because the cooling performance is improved and the heat dissipation characteristics are improved.

Here, the semiconductor device Q1 is mounted on the first electrode pattern 24D1 of the conductive layer 24D on the lower ceramic substrate 21D. Basically, the semiconductor device Q1 is arranged such that the U side is a source electrode (source pad electrode) and the D side is a drain electrode (for other semiconductor devices Q1, Q2, Q3, Q4, Q5, and Q6, which will be described later). Is the same).

The semiconductor device Q1 may be mounted on the lower ceramic substrate 21D in a flip chip.

Further, as shown in FIG. 2A, the semiconductor device Q1 is not limited to being connected in parallel up to 5 chips (MOSFET Q × 5), and a part of the 5 chips may be used for a diode.

In the semiconductor module 20 applicable to the PM 10 according to the first embodiment, the U-side conductive layer 23U on the upper ceramic substrate 21U and the D-side conductive layer 23D on the lower ceramic substrate 21D are exposed to the outside. In this way, the outer periphery of the semiconductor device Q1 is sealed with the mold resin 33.

The lower cooler 30D is joined to the D-side conductive layer 23D (lower surface 20b) of the lower ceramic substrate 21D exposed from the mold resin 33, and the U-side conductive layer 23U of the upper ceramic substrate 21U exposed from the mold resin 33. The upper cooler 30U is joined to the (upper surface 20a).

As the upper cooler 30U and the lower cooler 30D, for example, an air-cooled heat radiator such as a heat sink, a heat radiation fin, or a heat radiation pin, or a water-cooled cooler can be applied.

That is, the PM 10 according to the first embodiment includes a first insulating substrate 21D, a semiconductor device Q1 mounted on the first insulating substrate 21D and generating heat during operation, and the first insulating substrate 21D on the semiconductor device Q1. The second insulating substrate 21U disposed opposite to the semiconductor device Q1, one end disposed on the semiconductor device Q1, and the other end connected to the electrode pattern 24D2 formed on the first insulating substrate 21D to transmit an electric signal A path layer (bridge portion 35C) and a heat conduction path layer having one end disposed on the semiconductor device Q1 and the other end connected to the second insulating substrate 21U to conduct the heat of the semiconductor device to the second insulating substrate side (Post part 35T).

In addition, the first cooling for cooling the heat from the heat conduction path layer 35T via the second insulating substrate 22U, which is disposed on the surface opposite to the surface facing the first insulating substrate 22D of the second insulating substrate 22U. An instrument 30U may be further provided.

Further, a second cooler 30D is disposed on the surface of the first insulating substrate 22D opposite to the surface on which the semiconductor device Q1 is mounted to cool the heat of the semiconductor device Q1 via the first insulating substrate 22D. You may have.

The first insulating substrate 22D further includes a first conductive layer 24D disposed on a surface side on which the semiconductor device Q1 is mounted and having a first electrode pattern 24D1 and a second electrode pattern 24D2, and the semiconductor device Q1 The electric conduction path layer 35C is mounted on the first electrode pattern 24D1, and connects between the pad electrode formed on the upper surface of the semiconductor device Q1 and the second electrode pattern 24D2.

Further, the second insulating substrate 22U is further provided with a second conductive layer 24U disposed on the surface facing the first insulating substrate 22D and facing the first conductive layer 24D, and the heat conduction path layer 35T is formed of the semiconductor device Q1. The pad electrode disposed on the upper surface and the second conductive layer 24U are connected, and the heat of the semiconductor device Q1 can be conducted to the second insulating substrate 22U side.

The PM 10 according to the first embodiment includes a first insulating substrate 22D having a front surface and a back surface, a semiconductor device Q1 mounted on the front surface side of the first insulating substrate 22D and generating heat during operation, and the semiconductor device Q1. The second insulating substrate 22U is disposed opposite to the first insulating substrate 22D and has a front surface and a back surface, and the first insulating substrate 22U is disposed on the surface opposite to the surface facing the semiconductor device Q1. The cooler 30U, one end disposed on the semiconductor device Q1, and the other end connected to the electrode pattern 24D2 formed on the first insulating substrate 22D to transmit an electrical signal, and one end to the semiconductor device A heat conduction path layer 35T disposed on Q1 and having the other end connected to the second insulating substrate 22U to conduct the heat of the semiconductor device Q1 to the first cooler 30U. 5C may have a block structure integral connected from the side of the heat conducting path layer 35T to the electrode pattern 24d2.

Thus, according to PM10 which concerns on 1st Embodiment, the conduction path layer 35 which has the bridge | bridging part 35C and the post part 35T is arrange | positioned on the upper surface of the semiconductor device Q1, and the heat dissipation path | route T and the electrical path | route C Therefore, it is possible to provide a structure that can dissipate heat more efficiently.

That is, by arranging the post part 35T and the bridge part 35C on the upper surface of the semiconductor device Q1 in the PM10 having a so-called double-sided cooling structure in which the upper cooler 30U and the lower cooler 30D are arranged above and below the semiconductor module 20, The heat of the semiconductor device Q1 is mainly effectively led to the upper cooler 30U side along the post part 35T, and the current of the semiconductor device Q1 is mainly sent along the bridge part 35C to the second electrode pattern 24D2. Will be effectively guided to the side.

Thereby, in the PM 10 according to the first embodiment, the semiconductor device Q1 can be efficiently cooled in the vertical direction.

Therefore, according to the first embodiment, it is possible to provide the PM 10 that can efficiently dissipate heat.

Note that the PM 10 according to the first embodiment is not limited to the double-sided cooling structure, and may be a single-sided (upper surface) cooling structure in which the upper cooler 30U is disposed only on the semiconductor module 20, for example, The device 30D can be omitted.

(Comparative Example 1)
A schematic cross-sectional structure of PM10A according to Comparative Example 1 is expressed as shown in FIG.

In the case of PM10A according to Comparative Example 1, for example, as shown in FIG. 3, a columnar electrode (metal block) 36 is provided between the upper surface (U side) of the semiconductor device Q1 and the conductive layer 24U on the D side of the upper ceramic substrate 21U. Thus, the columnar electrode (metal block) 37 connects the conductive layer 24U on the D side of the upper ceramic substrate 21U and the second electrode pattern 24D2 of the conductive layer 24D on the U side of the lower ceramic substrate 21D, respectively. .

That is, in the PM 10A according to the comparative example 1, the heat of the semiconductor device Q1 is mainly guided to the upper cooler 30U side via the columnar electrode 36 (heat radiation path T1), and the current of the semiconductor device Q1 is Then, after being led to the upper ceramic substrate 21U side via the columnar electrode 36, it is led to the second electrode pattern 24D2 side via the columnar electrode 37 (electrical path C1).

Thus, in the PM10A having the double-sided cooling structure, when the metal block 36 is disposed on the semiconductor device Q1 and is connected to the upper ceramic substrate 21U thermally and electrically, the electric path C1 is one of the heat dissipation paths T1. Therefore, the heat generated by Joule heat hinders heat dissipation and causes deterioration of characteristics.

(First modification of the first embodiment)
A schematic cross-sectional structure of the PM 10 according to the first modification of the first embodiment is expressed as shown in FIG. 4A, and a part of the PM 10 corresponding to the II-II line in FIG. A schematic planar pattern configuration that is transmitted through is represented as shown in FIG.

That is, the PM 10 according to the first modification of the first embodiment is the same as the PM 10 according to the first embodiment except for the configuration of the conductive path layer 351.

In the case of the PM 10 according to the first modification of the first embodiment, as shown in FIGS. 4A and 4B, the conductive path layer 351 is provided with respect to the upper ceramic substrate 21U or the lower ceramic substrate 21D. An I-shaped post portion 351T arranged substantially vertically, for example, extending horizontally from the base end side along the upper surface of the semiconductor device Q1, and the lower portion for connection with the second electrode pattern 24D2 A bridge portion 351C having a substantially L-shaped (or inverted L-shaped) plug structure that is deformed to the ceramic substrate 21D side.

According to the first modification of the first embodiment, the heat dissipation path T and the electrical path C are separated as in the case of the PM 10 according to the first embodiment. It is possible to provide a possible structure, and it is possible to provide the PM 10 that can efficiently dissipate heat.

As the conductive path layer 351, for example, as in the case of the conductive path layer 35 applied to the PM 10 according to the first embodiment, for example, the bridge portion 351C and the post portion 351T have an integrated block structure, or It may have a separate structure.

Further, as the conductive path layer 351, for example, a layered structure in which the post portion 351T is stacked on the bridge portion 351C may be provided.

Further, as the conductive path layer 351, for example, the bridge portion 351C and the post portion 351T may be provided with the same constituent member or different constituent members.

Further, as the conduction path layer 351, for example, the bridge portion 351C may include one component member or a plurality of component members.

Further, as the conductive path layer 351, for example, the post portion 351T may include one component member, a plurality of component members, or a plurality of layer electrode structures.

As the post portion 351T, for example, in a cross-sectional view, the post portion 351T has any one of an I shape, a square shape, an inverted trapezoidal shape, an inverted tapered shape, or an inverted step tapered shape.

In the conductive path layer 351, for example, the bridge portion 351C includes Cu, and the post portion 351T includes SiC or Cu.

In addition, as in the first embodiment, the conductive path layer 351 desirably has a size A in the vertical direction smaller than a size B in the horizontal direction.

(Second modification of the first embodiment)
A schematic cross-sectional structure of the PM 10 according to the second modification of the first embodiment is expressed as shown in FIG. 5A, and a part of the PM 10 corresponding to the line III-III in FIG. A schematic plane pattern configuration that is shown through is expressed as shown in FIG.

That is, the PM 10 according to the second modification of the first embodiment is the same as the PM 10 according to the first embodiment except for the configuration of the conductive path layer 352.

In the case of the PM 10 according to the second modification of the first embodiment, as shown in FIGS. 5A and 5B, the conductive path layer 352 is provided with respect to the upper ceramic substrate 21U or the lower ceramic substrate 21D. The I-shaped post portion 352T arranged substantially vertically, for example, extends horizontally from the front end side along the lower surface of the second conductive layer 24U, and is connected to the second electrode pattern 24D2. And a bridge portion 352C having a substantially L-shaped (or inverted L-shaped) plug structure that is deformed to the lower ceramic substrate 21D side.

According to the second modification of the first embodiment, the heat dissipation path T and the electric path C are separated as in the case of the PM 10 according to the first embodiment. It is possible to provide a possible structure, and it is possible to provide the PM 10 that can efficiently dissipate heat.

As the conductive path layer 352, as in the case of the conductive path layer 35 applied to the PM 10 according to the first embodiment, for example, the bridge portion 352C and the post portion 352T have an integrated block structure, or It may have a separate structure.

Further, as the conductive path layer 352, for example, a layered structure in which the post portion 352T is stacked on the bridge portion 352C may be provided.

Further, as the conductive path layer 352, for example, the bridge portion 352C and the post portion 352T may be provided with the same constituent member or different constituent members.

Further, as the conductive path layer 352, for example, the bridge portion 352C may include one component member or a plurality of component members.

Further, as the conductive path layer 352, for example, the post portion 352T may include one component member, a plurality of component members, or a plurality of layer electrode structures.

As the post portion 352T, for example, in a cross-sectional view, the post portion 352T has any one of an I shape, a square shape, an inverted trapezoidal shape, an inverted tapered shape, or an inverted step tapered shape.

In the conductive path layer 352, for example, the bridge portion 352C includes Cu, and the post portion 352T includes SiC or Cu.

In addition, as in the first embodiment, the conductive path layer 352 desirably has a size A in the vertical direction smaller than a size B in the horizontal direction.

(Third Modification of First Embodiment)
A schematic cross-sectional structure of the PM 10 according to the third modification example of the first embodiment is expressed as shown in FIG. 6A, and a part of the PM 10 corresponding to the IV-IV line in FIG. A schematic plane pattern configuration that is transmitted through is represented as shown in FIG.

That is, the PM 10 according to the third modification of the first embodiment is the same as the PM 10 according to the first embodiment except for the configuration of the conductive path layer 353.

In the case of the PM 10 according to the third modification of the first embodiment, as shown in FIGS. 6A and 6B, the conductive path layer 353 is provided with respect to the upper ceramic substrate 21U or the lower ceramic substrate 21D. An I-shaped post portion 353T arranged substantially vertically, and, for example, in the horizontal direction along the upper surface of the semiconductor device Q1 and the lower surface of the conductive layer 24U with its width (height from the base end side to the tip end side) And a bridge portion 353C having a substantially L-shaped (or inverted L-shaped) plug structure that is extended and deformed toward the lower ceramic substrate 21D for connection to the second electrode pattern 24D2.

According to the third modification of the first embodiment, the heat dissipation path T and the electrical path C are separated as in the case of the PM 10 according to the first embodiment. It is possible to provide a possible structure, and it is possible to provide the PM 10 that can efficiently dissipate heat.

As the conductive path layer 353, as in the case of the conductive path layer 35 applied to the PM 10 according to the first embodiment, for example, the bridge portion 353C and the post portion 353T are integrated block structure, or It may have a separate structure.

Further, as the conductive path layer 353, for example, a layered structure in which the post portion 353T is stacked on the bridge portion 353C may be provided.

Further, as the conductive path layer 353, for example, the bridge portion 353C and the post portion 353T may be provided with the same constituent member or different constituent members.

Further, as the conduction path layer 353, for example, the bridge portion 353C may include one component member or a plurality of component members.

Further, as the conductive path layer 353, for example, the post portion 353T may include one constituent member, a plurality of constituent members, or a plurality of layer electrode structures.

As the post portion 353T, for example, in a cross-sectional view, the post portion 353T has any one of an I shape, a square shape, an inverted trapezoidal shape, an inverted tapered shape, or an inverted step tapered shape.

In the conductive path layer 353, for example, the bridge portion 353C includes Cu, and the post portion 353T includes SiC or Cu.

In addition, as in the first embodiment, the conduction path layer 353 preferably has a size A in the vertical direction smaller than a size B in the horizontal direction.

(Second Embodiment)
A schematic cross-sectional structure of the PM 10 according to the second embodiment is represented as shown in FIG. 7A, and shows a part of the PM 10 corresponding to the line VV in FIG. 7A. A schematic planar pattern configuration is expressed as shown in FIG.

That is, the PM 10 according to the second embodiment is the same as the PM 10 according to the first embodiment except for the configuration of the conductive path layer 35.

In the case of the PM 10 according to the second embodiment, as shown in FIGS. 7A and 7B, the conductive path layer 35 is disposed substantially perpendicular to the upper ceramic substrate 21U or the lower ceramic substrate 21D. The I-shaped post portion 35T, and, for example, a bridge portion 35C that is independent (divided) from the post portion 35T and has a substantially U-shaped (or inverted U-shaped) plug structure.

According to the second embodiment, the heat dissipation path T and the electrical path C are separated as in the case of the PM 10 according to the first embodiment, so that the structure can dissipate heat more efficiently. Therefore, it is possible to provide the PM 10 that can efficiently dissipate heat.

As the conduction path layer 35, for example, the bridge portion 35C includes Cu, and the post portion 35T includes SiC (or Cu). That is, the bridge portion 35C and the post portion 35T may be provided with the same constituent member or different constituent members.

Further, as the conduction path layer 35, for example, the bridge portion 35C may include one component member or a plurality of component members.

Further, as the conductive path layer 35, for example, the post portion 35T may be provided with one constituent member, a plurality of constituent members, or a plurality of layer electrode structures.

In addition, as in the first embodiment, the conduction path layer 35 desirably has a vertical size A smaller than a horizontal size B.

(Third embodiment)
A schematic cross-sectional structure of the PM 10 according to the third embodiment is represented as shown in FIG. 8A, and shows a part of the PM 10 corresponding to the VI-VI line of FIG. 8A. A schematic planar pattern configuration is expressed as shown in FIG.

Also, a schematic bird's-eye view configuration that shows a part of the PM 10 according to the third embodiment is shown as shown in FIG.

That is, the PM 10 according to the third embodiment is the same as the PM 10 according to the first embodiment except for the configuration of the conductive path layer 35.

In the case of the PM 10 according to the third embodiment, as shown in FIGS. 8A and 8B, the conductive path layer 35 is extended in the horizontal direction along the upper surface of the semiconductor device Q1, for example. A bridge portion 35C having a substantially L-shaped (or inverted L-shaped) plug structure deformed to the lower ceramic substrate 21D side for connection to the second electrode pattern 24D2, and an upper surface of the semiconductor device Q1 Corresponding I-shaped post portions 35T are disposed on the base end side of the bridge portion 35C.

That is, the PM 10 according to the third embodiment includes a first insulating substrate 22D, a semiconductor device Q1 mounted on the first insulating substrate 22D and generating heat during operation, and the first insulating substrate 22D on the semiconductor device Q1. A second insulating substrate 22U disposed opposite to the semiconductor device Q1, a first cooler 30U disposed on the surface of the second insulating substrate 22U opposite to the surface facing the semiconductor device Q1, and one end on the semiconductor device Q1 The other end side is connected to the electrode pattern 24D2 formed on the first insulating substrate 22D to transmit an electric signal, and the electric conduction path layer 35C is laminated on the second insulating substrate 22U side of the electric conduction path layer 35C. The heat conduction path layer 35T connected to the second insulating substrate 22U and conducting the heat of the semiconductor device Q1 to the first cooler 30U may be provided.

According to the third embodiment, the heat dissipation path T and the electrical path C are separated as in the case of the PM 10 according to the first embodiment, so that the structure can dissipate heat more efficiently. Therefore, it is possible to provide the PM 10 that can efficiently dissipate heat.

(simulation result)
Here, the result of analyzing the thermal resistance _Rth will be described using the PM 10 according to the third embodiment as an example.

The simulation compared the case where the post portion 35T is made of SiC and the case where the post portion 35T is made of Cu.

In PM10 used for the simulation, for example, as shown in FIG. 8B, the size (W1) of the first electrode pattern 24D1 and the second electrode pattern 24D2 is 10 mm square, and the size (W2) of the semiconductor device Q1. Was 5 mm square.

Further, the distance (W3) between the first electrode pattern 24D1 and the second electrode pattern 24D2 and the distance (W4) from the end of the semiconductor device Q1 of the post portion 35T were set to 1 mm and 1 mm, respectively.

Note that the details of the PM 10 are more specifically defined, for example, as shown in FIG.

The upper cooler 30U and the lower cooler 30D employ, for example, a heat sink, and the material is Al, the thickness is 1 mm, and the thermal conductivity is 2.37 (W / mK).

In the upper ceramic substrate 21U / lower ceramic substrate 21D, for example, the material of the conductive layer 23U / conductive layer 23D is Cu, the thickness is 0.3 mm, and the thermal conductivity is 402 (W / mK). The material of 22D is SiN (silicon nitride film), the thickness is 0.3 mm, the thermal conductivity is 90 (W / mK), the material of the conductive layer 24U / conductive layer 24D is Cu, the thickness is 0.3 mm, the thermal conductivity Was 402 (W / mK).

In the conductive path layer 35, for example, when the material of the post portion 35T is SiC, the thickness is 1.0 mm, the thermal conductivity is 450 (W / mK), and when the material is Cu, the thickness is 1 0.0 mm and thermal conductivity of 402 (W / mK).

For example, the bridge portion 35C is made of Cu, has a thickness of 0.1 mm, and a thermal conductivity of 402 (W / mK).

For the chip Q1, the main material was SiC, the thickness was 0.35 mm, and the thermal conductivity was 450 (W / mK).

As other conditions, the heat generation amount of the entire chip was 700 W, the peripheral heat insulation, and the outer surface temperature of the upper cooler 30U and the lower cooler 30D serving as boundary conditions were 65 ° C.

When the simulation was actually performed under such conditions, the analysis result of the thermal resistance when the post portion 35T is made of SiC is expressed as shown in FIG. The analysis result about the thermal resistance in the case of the configuration is expressed as shown in FIG.

That, PM10 of case where the post portion 35T of SiC, as shown in FIG. 11 (a), an evaluation junction temperature Tjmax is 182.565 ° C., the thermal resistance R _th is 0.168 (W / K) It is. In contrast, PM10 of case where the post portion 35T of Cu, as shown in FIG. 11 (b), evaluation junction temperature Tjmax is the 184.869 ° C., the thermal resistance R _th is 0.171 (W / K).

From this result, it can be seen that, for example, by configuring the post portion 35T with SiC, the thermal resistance can be improved by about 2% as compared with the case of configuring with the Cu.

Therefore, in the PM 10 according to the third embodiment, for example, the bridge portion 35C and the post portion 35T divide the heat dissipation path T and the electrical path C and configure the post portion 35T with SiC (bridge portion). 35C is composed of Cu), and further improvement in thermal resistance is possible.

(First modification of the third embodiment)
A schematic cross-sectional structure of the PM 10 according to the first modification of the third embodiment is expressed as shown in FIG.

That is, the PM 10 according to the first modification of the third embodiment is the same as the PM 10 according to the third embodiment except for the configuration of the conductive path layer 35.

In the case of the PM 10 according to the first modification of the third embodiment, as shown in FIG. 12, the conduction path layer 35 has, for example, a substantially U-shaped (or substantially inverted U-shaped) plug structure. The bridge portion 35C and a square post portion 35T arranged in a stacked manner on a part of the upper surface of the bridge portion 35C are provided.

Also in the first modification of the third embodiment, for example, the post portion 35T of the conduction path layer 35 is made of SiC (the bridge portion 35C is made of Cu), so that the thermal resistance can be further improved. Become.

(Second modification of the third embodiment)
A schematic cross-sectional structure of the PM 10 according to the second modification of the third embodiment is expressed as shown in FIG. 13A, and a part of the PM 10 corresponding to the VII-VII line in FIG. A schematic plane pattern configuration that is transmitted through is represented as shown in FIG.

That is, the PM 10 according to the second modification of the third embodiment is the same as the PM 10 according to the third embodiment except for the configuration of the conductive path layer 35.

In the case of the PM 10 according to the second modification of the third embodiment, as shown in FIGS. 13A and 13B, the conductive path layer 35 has, for example, a substantially U shape (or an inverted U shape). ) A bridge portion 35C having a plug structure and a square post portion 35T stacked on the entire surface of the bridge portion 35C.

Also in the second modified example of the third embodiment, for example, by configuring the post portion 35T of the conductive path layer 35 with SiC (the bridge portion 35C is configured with Cu), it is possible to further improve the thermal resistance. Become.

(Third Modification of Third Embodiment)
A schematic cross-sectional structure of the PM 10 according to the third modification of the third embodiment is represented as shown in FIG. 14A, and a part of the PM 10 corresponding to the line VIII-VIII in FIG. A schematic plane pattern configuration shown through is represented as shown in FIG.

That is, the PM 10 according to the third modification of the third embodiment is the same as the PM 10 according to the third embodiment except for the configuration of the conductive path layer 35.

In the case of the PM 10 according to the third modification of the third embodiment, as shown in FIGS. 14A and 14B, the conductive path layer 35 has, for example, a substantially L shape (or an inverted L shape). ) A bridge portion 35C having a plug structure and a square post portion 35T stacked on the entire surface of the bridge portion 35C.

Also in the third modification of the third embodiment, for example, the post part 35T of the conductive path layer 35 is made of SiC (the bridge part 35C is made of Cu), so that the thermal resistance can be further improved. Become.

(Fourth modification of the third embodiment)
A schematic cross-sectional structure of the PM 10 according to the fourth modification example of the third embodiment is represented as shown in FIG. 15A, and a part of the PM 10 corresponding to the IX-IX line in FIG. A schematic plane pattern configuration shown through is represented as shown in FIG.

That is, the PM 10 according to the fourth modification of the third embodiment is the same as the PM 10 according to the third embodiment except for the configuration of the conductive path layer 35.

In the case of the PM 10 according to the fourth modified example of the third embodiment, as shown in FIGS. 15A and 15B, the conductive path layer 35 is, for example, substantially U-shaped (or inverted U-shaped). ) A bridge portion 35C having a plug structure having a shape, and a post portion having a substantially L-shaped (or inverted L-shaped) plug structure, which is arranged so as to cover one side surface and an upper surface of the bridge portion 35C. 35T.

Also in the fourth modification of the third embodiment, for example, the post part 35T of the conductive path layer 35 is made of SiC (the bridge part 35C is made of Cu), so that the thermal resistance can be further improved. Become.

In the first to third embodiments described above, the semiconductor power device is used and applied to a 1 いずれ in 1 module type power module. However, for example, 2 in 1 (two-in-one) Type) module, 4 in 1 (four-in-one type) module, 6 in 1 (six-in-one type) module, 7 in 1 (seven-in-one type) module with snubber capacitor etc. in 6 in 1 module, 8 in 1 (eight) It can also be applied to a power module that constitutes any one of an in-one type module, a 12 in 1 (twelve-in-one type) module, or a 14 in 1 (fourteen-in-one type) module.

(Fourth embodiment)
A schematic cross-sectional structure of the PM 10 according to the fourth embodiment is expressed as shown in FIG. FIG. 16 illustrates a case where the present invention is applied to a 2-in-1 module type PM10.

Also, FIG. 17A shows a schematic plan configuration showing a part of the PM 10 according to the fourth embodiment, and FIG. 17B shows a semiconductor device (chip) Q 1. A schematic circuit configuration when a SiC MOSFET is applied is shown as Q4.

Note that the schematic cross-sectional structure of the PM 10 shown in FIG. 16 is, for example, along the line XX in FIG. In addition, in the schematic planar pattern configuration of FIG. 17A, the description of the upper cooler (first cooler) 30U and the upper ceramic substrate (second insulating substrate) 21U is omitted.

The PM 10 according to the fourth embodiment is the same as the PM 10 according to the first embodiment except for the configuration of the semiconductor module 20 (semiconductor devices Q1 and Q4).

That is, the PM 10 according to the fourth embodiment includes a semiconductor module 20 in which semiconductor devices Q1 and Q4 in which a plurality of chips are connected in parallel are sealed with a mold resin 33, as shown in FIGS.

The semiconductor device Q1 is disposed on the first electrode pattern 24D1 of the conductive layer 24D on the lower ceramic substrate 21D, and the semiconductor device Q4 is disposed on the second electrode pattern 24D2 of the conductive layer 24D on the lower ceramic substrate 21D. .

Here, the lower ceramic substrate 21D has

conductive layers

23D and 24D (first electrode pattern 24D1 and second electrode pattern 24D2) in which a metal foil such as copper (for example, a first copper plate layer) is laminated via an insulating layer 22D. A third electrode pattern 24D3, gate

signal electrode patterns

1 and 5, and source signal electrode patterns 3 and 7) are provided.

On the other hand, the upper ceramic substrate 21U has

conductive layers

23U and 24U (first electrode pattern 24U1 and second electrode pattern 24U2) in which a metal foil such as copper (for example, a second copper plate layer) is laminated via an insulating layer 22U. Is provided.

The lower ceramic substrate 21D and the upper ceramic substrate 21U are arranged such that the first conductive layer 24D and the second conductive layer 24U face each other.

As shown in FIG. 17B, the SiC MOSFETs Q1 and Q4 are connected in series between the power supply input terminal electrodes P and N, and the connection point between the SiC MOSFETs Q1 and Q4 is used as the output terminal OUT (output terminal electrode O). In such a case, G1 is a gate terminal (lead terminal for gate signal) of the semiconductor device Q1, D1 is a drain terminal of the semiconductor device Q1, and S1 is a source terminal of the semiconductor device Q1. Similarly, G4 is a gate terminal (lead terminal for gate signal) of the semiconductor device Q4, D4 is a drain terminal of the semiconductor device Q4, and S4 is a source terminal of the semiconductor device Q4.

For PM10 according to the fourth embodiment, the upper surface of the semiconductor device Q1 (U side) is a base end side of the conductive path layers 35 _1, for example, the connection base end side of the post portion 35T of the I-shaped Has been. Further, the tip side of the post portion 35T is connected to the first electrode pattern 24U1 of the second conductive layer 24U on the D side of the upper ceramic substrate 21U.

Further, for example, the bridge portion 35C extending in a horizontal direction from a middle portion of the side surface of the post portion 35T and having a substantially L-shaped (or inverted L-shaped) plug structure has a lower ceramic substrate on the tip side. It is connected to the second electrode pattern 24D2 of the U-side conductive layer 24D on 21D.

Similarly, the upper surface (U side) of the semiconductor device Q4 is a base end side of the conductive path layers 35 _2, for example, the base end side of the post portion 35T of the I-shape is connected. Further, the tip side of the post portion 35T is connected to the second electrode pattern 24U2 of the conductive layer 24U on the D side of the upper ceramic substrate 21U.

Further, for example, the bridge portion 35C extending in a horizontal direction from a middle portion of the side surface of the post portion 35T and having a substantially L-shaped (or inverted L-shaped) plug structure has a lower ceramic substrate on the tip side. The U-side conductive layer 24D on the 21D is connected to the third electrode pattern 24D3.

Even PM10 in the 2 in 1 module type, as in the case of 1 in 1 module type, for example, the post portion 35T of the conductive path layers 35 _1, 35 ₄ by configuring the SiC (bridge portion 35C is Further, the thermal resistance can be further improved.

That is, according to the fourth embodiment, since the heat dissipation path T and the electrical path C are separated for each of the semiconductor devices Q1 and Q4, it is possible to provide a structure that can dissipate heat more efficiently. PM10 capable of radiating heat can be provided.

As the conduction path layers 35 ₁ and 35 ₄ , for example, the bridge part 35C and the post part 35T are integrated as in the case of the conduction path layer 35 applied to the PM 10 according to the first embodiment. It may be provided with a block structure or a separate type divided structure.

Further, as the conductive path layers 35 ₁ and 35 ₄ , for example, the bridge portion 35C and the post portion 35T may be provided with the same constituent member or different constituent members.

Moreover, as the conduction path layers 35 ₁ and 35 ₄ , for example, a layered structure in which post portions 35T are stacked on the bridge portion 35C may be provided.

Further, as the conductive path layers 35 ₁ and 35 ₄ , for example, the bridge portion 35C may include one component member or a plurality of component members.

Further, as the conductive path layers 35 ₁ and 35 ₄ , for example, the post portion 35T may include one component member, a plurality of component members, or a plurality of layer electrode structures.

In the conduction path layers 35 ₁ and 35 ₄ , the bridge portion 35C includes Cu, and the post portion 35T includes SiC or Cu.

Further, the conductive path layers 35 ₁ and 354 ₄ desirably have a vertical size A smaller than a horizontal size B, as in the first embodiment.

(Comparative Example 2)
A schematic cross-sectional structure of PM10A according to Comparative Example 2 is expressed as shown in FIG. The basic structure is the same as that of the PM 10 according to the fourth embodiment.

In the case of PM10A according to Comparative Example 2, for example, as shown in FIG. 18, between the upper surfaces (U side) of the semiconductor devices Q1 and Q4 and the first and second electrode patterns 24U1 and 24U2 on the D side of the upper ceramic substrate 21U. The first and second electrode patterns 24U1 and 24U2 on the D side of the upper ceramic substrate 21U and the second and third electrodes on the U side of the lower ceramic substrate 21D by the columnar electrodes (metal blocks) 36 ₁ and 36 ₂ The patterns 24D2 and 24D3 are connected by columnar electrodes (metal blocks) 37 ₁ and 37 ₂ , respectively.

That is, in the PM 10A according to the comparative example 2, the heat of the semiconductor devices Q1 and Q4 is mainly led to the upper cooler 30U side through the

columnar electrodes

36 ₁ and 36 ₂ , but the semiconductor devices Q1 and Q4 The current is mainly guided to the upper ceramic substrate 21U side through the

columnar electrodes

36 ₁ and 36 ₂ and then the second electrode pattern 24D2 and the third electrode pattern 24D3 side through the

columnar electrodes

37 ₁ and 37 _2. Will be led to.

Therefore, in the case of this comparative example 2, since there are many portions where the electric path is the same as the heat dissipation path, similarly to the case of the comparative example 1, the heat generated by Joule heat hinders heat dissipation, and the characteristics deteriorate. Invite.

In the first to fourth embodiments described above, the semiconductor power device includes a Si-based IGBT, a Si-based MOSFET, a SiC-based MOSFET, a SiC-based IGBT, a hybrid element of a SiC-based MOSFET and a SiC-based IGBT, GaN Any one of the system FETs or a plurality of these different ones may be provided.

(Application example)
(First application example)
A schematic cross-sectional structure of the power module according to the first application example of the present embodiment is expressed as shown in FIG.

That is, as shown in FIG. 19, for example, the post part 35T stacked on the bridge part 35C may be configured to have an inverted trapezoidal shape.

(Second application example)
A schematic cross-sectional structure of the power module according to the second application example of the present embodiment is expressed as shown in FIG.

That is, as shown in FIG. 20, for example, the post part 35 </ b> T stacked on the bridge part 35 </ b> C may be configured to have an inversely tapered shape.

(Third application example)
A schematic cross-sectional structure of a power module according to the third application example of the present embodiment is expressed as shown in FIG.

That is, as shown in FIG. 21, for example, the post part 35T stacked on the bridge part 35C may be configured to have a reverse step taper shape.

(Fourth application example)
A schematic cross-sectional structure of the power module according to the fourth application example of the present embodiment is expressed as shown in FIG.

That is, as shown in FIG. 22, for example, the post portion 35T stacked on the bridge portion 35C may be configured to have a structure in which a plurality of layer electrodes are stacked in a reverse step taper shape.

(Specific examples of power modules)
Hereinafter, specific examples of the power module according to the embodiment will be described.

FIG. 23 is a schematic circuit representation of a SiC MOSFET of 1 in 1 module, which is a PM 50 according to the embodiment.

FIG. 23 shows a diode DI connected in reverse parallel to the MOSFET Q. The main electrode of the MOSFET Q is represented by a drain terminal DT and a source terminal ST. The diode DI may be omitted by using a parasitic diode, or a Schottky diode may be connected in parallel with the diode DI.

In addition, the detailed circuit representation of the SiC MOSFET of 1 in 1 module in the PM 50 according to the embodiment is expressed as shown in FIG.

The PM 50 according to the embodiment has, for example, a 1 in 1 module configuration. In other words, a single MOSFET Q formed by connecting a plurality of MOSFETs in parallel is built in one module. As an example, five chips (MOSFETs × 5) can be mounted, and up to five MOSFETs Q can be connected in parallel. A part of the five chips can be mounted for the diode DI.

More specifically, as shown in FIG. 24, a sense MOSFET Qs is connected in parallel to the MOSFET Q. The sense MOSFET Qs is formed as a fine transistor in the same chip as the MOSFET Q.

24, SS is a source sense terminal, CS is a current sense terminal, and G is a gate signal terminal. Also in the embodiment, in the semiconductor device Q, a sense MOSFET Qs is formed as a fine transistor in the same chip.

(Circuit configuration)
Moreover, it is the power module 50T which concerns on embodiment, Comprising: The typical circuit expression of SiC MOSFET of 2 in 1 module is represented as shown in FIG.

Here, for example, the semiconductor module 20 is applicable to the PM 10 according to the fourth embodiment, and is a semiconductor package device in which two semiconductor devices Q1 and Q4 are sealed in one mold resin 33, so-called two. The in 1 type module will be described.

As the semiconductor devices Q1 and Q4, the circuit configuration of a 2-in-1 module 50T to which an SiC MOSFET is applied is expressed as shown in FIG. 25, for example.

That is, as shown in FIG. 25, the 2-in-1 module 50T has a configuration of a half-bridge built-in module in which two SiC MOSFETs Q1 and Q4 are built in as one module.

Here, the module can be regarded as one large transistor, but the built-in transistor may be one chip or a plurality of chips as shown in FIG. 2 or FIG. In addition, the modules include 1 in 1, 2 in 1, 4 in 1, 6 in 1, etc. For example, on one module, a module including two sets of modules shown in FIG. A module containing two sets of in 1 is called a 6 in 1 module having three sets of 4 in 1 and 2 in 1.

As shown in FIG. 25, the 2-in-1 module 50T includes two SiC MOSFETs Q1 and Q4 and diodes D1 and D4 connected in reverse parallel to the SiC MOSFETs Q1 and Q4 as a single module.

25, G1 is a lead terminal for a gate signal of the SiC MOSFET Q1, and S1 is a lead terminal for a source signal of the SiC MOSFET Q1. Similarly, G4 is a lead terminal for the gate signal of the SiC MOSFET Q4, and S4 is a lead terminal for the source signal of the SiC MOSFET Q4.

P is a positive power input terminal electrode, N is a negative power input terminal electrode, and O is an output terminal electrode.

The same applies to the semiconductor devices Q2 and Q5 applied to the semiconductor module 20 applicable to the PM 10 according to the fourth embodiment, and the semiconductor devices Q3 and Q6 applied to the semiconductor module 20, and detailed description thereof is omitted. .

(Device structure)
4 is an example of semiconductor devices Q1 and Q4 applied to the semiconductor module 20 applicable to the PM 10 according to the first to fourth embodiments, and is a schematic diagram of the SiC MOSFET 110 including the source pad electrode SP and the gate pad electrode GP. The cross-sectional structure is expressed as shown in FIG.

As shown in FIG. 26, SiC MOSFET 110 includes a semiconductor substrate 126 made of an n ⁻ high resistance layer, a p body region 128 formed on the surface side of semiconductor substrate 126, and a source formed on the surface of p body region 128. Connected to region 130, gate insulating film 132 disposed on the surface of semiconductor substrate 126 between p body region 128, gate electrode 138 disposed on gate insulating film 132, source region 130, and p body region 128 Source electrode 134, n ⁺ drain region 124 disposed on the back surface opposite to the front surface of semiconductor substrate 126, and drain electrode 136 connected to n ⁺ drain region 124.

The gate pad electrode GP is connected to the gate electrode 138 disposed on the gate insulating film 132, and the source pad electrode SP is connected to the source electrode 134 connected to the source region 130 and the p body region 128. Further, as shown in FIG. 26, the gate pad electrode GP and the source pad electrode SP are disposed on a passivation interlayer insulating film 144 that covers the surface of the SiC MOSFET 110.

Note that, although not shown, a fine transistor structure may be formed in the semiconductor substrate 126 below the gate pad electrode GP and the source pad electrode SP.

Furthermore, as shown in FIG. 26, even in the central transistor structure, the source pad electrode SP may be extended and disposed on the interlayer insulating film 144 for passivation.

In FIG. 26, the SiC MOSFET 110 is composed of a planar gate type n-channel vertical SiC MOSFET. However, as shown in FIG. 29 described later, the trench gate type n-channel vertical SiC T (Trench) MOSFET 110 is used. It may be configured.

Alternatively, as the semiconductor devices Q1 and Q4 applied to the semiconductor module 20 applicable to the PM 10 according to the first to fourth embodiments, a GaN-based FET or the like can be employed instead of the SiC MOSFET 110.

The same applies to the semiconductor devices Q2 and Q5 applied to the semiconductor module 20 applicable to the PM 10 according to the first to fourth embodiments and the semiconductor devices Q3 and Q6 applied to the semiconductor module 20.

Furthermore, the semiconductor devices Q1 to Q6 applied to the semiconductor module 20 applicable to the PM 10 according to the first to fourth embodiments have a wide band gap of, for example, 1.1 eV to 8 eV. A semiconductor called a mold can be used.

Similarly, it is an example of the semiconductor devices Q1 and Q4 applied to the semiconductor module 20 applicable to the PM 10 according to the first to fourth embodiments, and includes an IGBT 110A including the emitter pad electrode EP and the gate pad electrode GP. A schematic cross-sectional structure is expressed as shown in FIG.

As shown in FIG. 27, IGBT 110A includes a semiconductor substrate 126 made of an n ⁻ high resistance layer, a p body region 128 formed on the surface side of semiconductor substrate 126, and an emitter region formed on the surface of p body region 128. 130E, a gate insulating film 132 disposed on the surface of the semiconductor substrate 126 between the p body regions 128, a gate electrode 138 disposed on the gate insulating film 132, and the emitter regions 130E and the p body regions 128. Emitter electrode 134E, p ⁺ collector region 124P disposed on the back surface opposite to the surface of semiconductor substrate 126, and collector electrode 136C connected to p ⁺ collector region 124P.

The gate pad electrode GP is connected to the gate electrode 138 disposed on the gate insulating film 132, and the emitter pad electrode EP is connected to the emitter electrode 134E connected to the emitter region 130E and the p body region 128. In addition, as shown in FIG. 27, the gate pad electrode GP and the emitter pad electrode EP are disposed on a passivation interlayer insulating film 144 that covers the surface of the IGBT 110A.

Although not shown, a fine-structure IGBT structure may be formed in the semiconductor substrate 126 below the gate pad electrode GP and the emitter pad electrode EP.

Furthermore, as shown in FIG. 27, also in the IGBT structure in the central portion, the emitter pad electrode EP may be arranged to extend on the interlayer insulating film 144 for passivation.

27, the IGBT 110A is composed of a planar gate type n-channel vertical IGBT, but may be composed of a trench gate type n-channel vertical IGBT or the like.

As the semiconductor devices Q1 to Q6, SiC power devices such as SiC DIMOSFET and SiC TMOSFET, or GaN power devices such as GaN high electron mobility transistors (HEMT) are applicable. In some cases, power devices such as Si-based MOSFETs and IGBTs are also applicable.

―SiC DIMOSFET―
28 is an example of a semiconductor device applied to the semiconductor module 20 applicable to the PM 10 according to the first to fourth embodiments, and a schematic cross-sectional structure of the SiC DIMOSFET 110 is expressed as shown in FIG.

As shown in FIG. 28, the SiC DIMOSFET 110 applied to the semiconductor module 20 applicable to the PM 10 according to the first to fourth embodiments includes a semiconductor substrate 126 made of an n ⁻ high resistance layer, a semiconductor substrate 126 P body region 128 formed on the front surface side, n ⁺ source region 130 formed on the surface of p body region 128, and gate insulating film 132 disposed on the surface of semiconductor substrate 126 between p body regions 128, The gate electrode 138 disposed on the gate insulating film 132, the source electrode 134 connected to the source region 130 and the p body region 128, and the n + drain region disposed on the back surface opposite to the surface of the semiconductor substrate 126. 124 and a drain electrode 136 connected to the n ⁺ drain region 124.

In FIG. 28, SiC DIMOSFET 110 has a p body region 128 and an n ⁺ source region 130 formed on the surface of p body region 128 formed by double ion implantation (DII), and source pad electrode SP is connected to source region 130. And to the source electrode 134 connected to the p body region 128.

Although not shown, the gate pad electrode GP is connected to the gate electrode 138 disposed on the gate insulating film 132. Further, as shown in FIG. 28, the source pad electrode SP and the gate pad electrode GP are arranged on the passivation interlayer 144 so as to cover the surface of the SiC DIMOSFET 110.

As shown in FIG. 28, in the SiC DIMOSFET, a depletion layer as shown by a broken line is formed in a semiconductor substrate 126 made of an n − high resistance layer sandwiched between p body regions 128. A channel resistance R _{JFET due} to the JFET) effect is formed. A body diode BD is formed between the p body region 128 and the semiconductor substrate 126 as shown in FIG.

―SiC TMOSFET―
29 is an example of a semiconductor device applied to the semiconductor module 20 applicable to the PM 10 according to the first to fourth embodiments, and a schematic cross-sectional structure of the SiC TMOSFET 110 is expressed as shown in FIG.

As shown in FIG. 29, an SiC TMOSFET 110 applied to the semiconductor module 20 applicable to the PM 10 according to the first to fourth embodiments includes an n-layer semiconductor substrate 126N and a surface side of the semiconductor substrate 126N. The formed p body region 128, the n ⁺ source region 130 formed on the surface of the p body region 128, the gate insulating film 132 and the interlayer in the trench formed through the p body region 128 and reaching the semiconductor substrate 126N. Tr + gate electrode 138TG formed through insulating

films

144U and 144B, source electrode 134 connected to source region 130 and p body region 128, and n + disposed on the back surface opposite to the surface of semiconductor substrate 126N A drain region 124 and a drain electrode 136 connected to the n ⁺ drain region 124 are provided. .

In FIG. 29, SiC TMOSFET 110 has a trench gate electrode 138TG formed through a gate insulating film 132 and interlayer insulating

films

144U and 144B in a trench penetrating p body region 128 and extending to semiconductor substrate 126N. Electrode SP is connected to source electrode 134 connected to source region 130 and p body region 128.

Although not shown, the gate pad electrode GP is connected to the trench gate electrode 138TG disposed on the gate insulating film 132. Further, as shown in FIG. 29, the source pad electrode SP and the gate pad electrode GP are disposed on the passivation interlayer insulating film 144U so as to cover the surface of the SiC TMOSFET 110.

In the SiC TMOSFET, the channel resistance R _JFET associated with the junction FET (JFET) effect like the SiC DIMOSFET is not formed. A body diode BD is formed between the p body region 128 and the semiconductor substrate 126N, as in FIG.

(Application examples)
A three-phase AC inverter 140 configured using the PM 10 according to the first to fourth embodiments, using a SiC MOSFET as a semiconductor device, and a snubber capacitor between a power supply terminal PL and a ground (reference) terminal NL A circuit configuration example in which C is connected is expressed as shown in FIG. The inductance L represents the inductance of the wiring.

When the PM 10 according to the first to fourth embodiments is connected to the power supply E, a large surge voltage Ldi / dt is generated due to the high switching speed of the SiC MOSFET due to the inductance L of the connection line. For example, assuming that the current change di = 300 A and the time change dt = 100 nsec accompanying switching, di / dt = 3 × 10 ⁹ (A / s).

The value of the surge voltage Ldi / dt varies depending on the value of the inductance L, but the surge voltage Ldi / dt is superimposed on the power source E. The surge voltage Ldi / dt can be absorbed by the snubber capacitor C connected between the power supply terminal PL and the ground terminal NL.

The inverter device to which PM10 according to the present embodiment is applied may have the following configuration, for example. In other words, the inverter device performs power conversion using the power module PM10 in which a circuit including the semiconductor device Q1 connected between the power supply terminal PL and the reference terminal NL is formed, and the power module PM10 includes the first insulation. The substrate 22D, the semiconductor device Q1 mounted on the first insulating substrate 22D and generating heat during operation, and the semiconductor device Q1 facing the first insulating substrate 22D on the side opposite to the surface facing the semiconductor device Q1 The second insulating substrate 22U arranged in this manner and one end connected to the electrode pad formed on the semiconductor device Q1, and the other end connected to the electrode pattern 24D2 formed on the first insulating substrate 22D, the semiconductor device Q1 Current conduction path layer 35C that flows current from the first electrode to the electrode pattern 24D2 without passing through the second insulating substrate 22U, and one end of which is a semiconductor device. And the other end side is connected to the second insulating substrate 22U side, and includes a heat conduction path layer 35T for transferring the heat of the semiconductor device Q1 to the second insulating substrate 22U, and at least the semiconductor device Q1 and the electric conduction The road layer 35C, the heat conduction path layer 35T, and a mold resin for sealing a part of each terminal may be provided.

(Concrete example)
Next, with reference to FIG. 31, a three-phase AC inverter 140 configured using PM MOSFETs according to the first to fourth embodiments by applying SiC MOSFET as a semiconductor device will be described.

As shown in FIG. 31, a three-phase AC inverter 140 includes a PM 152 driven by a gate drive unit 150, a three-phase AC motor unit 154 connected to the output of each PM, and a power supply or storage battery that supplies power to the circuit. (E) 146 and a converter 148 that converts power of the power source 146 and supplies power to each PM. PM 152 is connected to an inverter circuit that outputs U-phase, V-phase, and W-phase corresponding to U-phase, V-phase, and W-phase of three-phase AC motor unit 154.

Here, the gate drive unit 150 is connected to each gate of each of the SiC MOSFETs Q1 and Q4, the SiC MOSFETs Q2 and Q5, and the SiC MOSFETs Q3 and Q6.

The PM 152 is connected between a plus terminal (+) P and a minus terminal (−) N of a converter 148 to which a power source or a storage battery (E) 146 is connected, and includes SiC MOSFETs Q 1 and Q 4, Q 2 and Q 5 having inverter configurations, and Q3 and Q6 are provided. Free wheel diodes D1 to D6 are connected in antiparallel between the source and drain of the SiC MOSFETs Q1 to Q6, respectively.

As described above, according to the present embodiment, a power module and an inverter device capable of efficiently dissipating heat can be realized. That is, in the power module, since the heat dissipation path T and the electrical path C are separated, a structure capable of efficiently dissipating heat can be achieved.

In particular, in the case where the PM according to each embodiment is for in-vehicle use, for example, more efficient heat dissipation is possible, so while ensuring higher safety with higher performance and higher functionality, Development of a highly efficient system becomes possible.

In the present embodiment, the mold type power module may be, for example, a mold type power module having a four-terminal structure.

Further, the semiconductor module applicable to the PM according to the present embodiment is not limited to a resin-molded mold type power module, but can also be applied to a power module (semiconductor package device) packaged by a case type package. It is.

[Other embodiments]
Although several embodiments have been described as described above, the discussion and drawings that form part of the disclosure are illustrative and should not be construed as limiting. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art. For example, in the circuits shown in FIGS. 30 and 31, instead of the source, drain, and gate of each MOSFET, a circuit in which the emitter, collector, and gate of the IGBT are connected to each other may be used. The lower cooler may be omitted by simply using a circuit board on which each PM is mounted.

Thus, the present embodiment includes various embodiments that are not described here.

The PM of the present embodiment can be used in various semiconductor module manufacturing technologies such as IGBT modules, diode modules, and MOS modules (Si, SiC, GaN), and HEV (Hybrid Electric Vehicle) / EV with particularly large heat generation. It can be applied to inverters for (Electric インバータ Vehicle), inverters and converters for industrial use, and can be applied to a wide range of application fields.

DESCRIPTION OF

SYMBOLS

1, 5 ... Gate

signal electrode pattern

3, 7 ... Source signal electrode pattern 10 ... Power module (PM)
DESCRIPTION OF SYMBOLS 20 ... Semiconductor module 21D ... Lower ceramic substrate 21U ... Upper

ceramic substrate

23D, 24D ... Conductive layer 23U * 24U ... Conductive layer 24D1, 24U1 ... 1st electrode pattern 24D2, 24U2 ... 2nd electrode pattern 24D3 ... 3rd electrode pattern 30D ... Lower cooler 30U ... Upper cooler 33 ...

Mold resin

35, 35 ₁ , 35 ₂ , 351, 352, 353, 353C ...

Conductive path layer

35C, 351C, 352C ... Bridge part (electrically conductive path layer)
35T, 351T, 352T, 353T ... post part (thermal conduction path layer)
Q1, Q2, Q3, Q4, Q5, Q6 ... Semiconductor device P ... Positive power supply input terminal electrode N ... Negative power supply input terminal electrode O ... Output terminal electrode PL ... Power supply terminal NL ... Reference terminal

Claims

A first insulating substrate;
A semiconductor device mounted on the first insulating substrate and generating heat during operation;
A second insulating substrate disposed on the semiconductor device to face the first insulating substrate;
One end is disposed on the semiconductor device and the other end is connected to an electrode pattern formed on the first insulating substrate to transmit an electric signal; and
One end is disposed on the semiconductor device, the other end is connected to the second insulating substrate, and a heat conduction path layer that conducts heat of the semiconductor device to the second insulating substrate is provided. module.
A first cooler disposed on a surface of the second insulating substrate opposite to the surface facing the first insulating substrate and configured to cool the heat from the heat conduction path layer through the second insulating substrate; The power module according to claim 1, further comprising:
A second cooler disposed on the surface of the first insulating substrate opposite to the surface on which the semiconductor device is mounted to cool the heat of the semiconductor device via the first insulating substrate; The power module according to claim 2, wherein the power module is a power module.
A first conductive layer disposed on a surface side of the first insulating substrate on which the semiconductor device is mounted and further including a first electrode pattern and a second electrode pattern;
The semiconductor device is mounted on the first electrode pattern,
The power module according to any one of claims 1 to 3, wherein the electrical conduction path layer connects a pad electrode formed on an upper surface of the semiconductor device and the second electrode pattern. .
A second conductive layer disposed on a surface of the second insulating substrate facing the first insulating substrate and facing the first conductive layer;
The heat conduction path layer connects between a pad electrode disposed on an upper surface of the semiconductor device and the second conductive layer, and conducts heat of the semiconductor device to the second insulating substrate side. The power module according to any one of claims 1 to 4.
The power according to any one of claims 1 to 5, wherein the electric conduction path layer includes an integrated block structure connected to the first insulating substrate from a side surface of the heat conduction path layer. module.
The electric conduction path layer and the heat conduction path layer have a laminated structure in which the heat conduction path layer is laminated on the second insulating substrate side of the electric conduction path layer. The power module according to any one of claims.
The power module according to any one of claims 1 to 5, wherein the electric conduction path layer and the heat conduction path layer have separate-type divided structures.
The power module according to any one of claims 1 to 6, wherein the electric conduction path layer and the heat conduction path layer include the same constituent members.
The power module according to any one of claims 1 to 5, wherein the electric conduction path layer and the heat conduction path layer include different constituent members.
The power module according to any one of claims 1 to 10, wherein the electric conduction path layer includes a U-shaped plug structure or an L-shaped plug structure.
The power module according to claim 10, wherein the electrical conduction path layer includes a member having a higher electrical conductivity than the heat conduction path layer.
The power module according to claim 12, wherein the electric conduction path layer comprises any one of copper, aluminum, and silver.
The heat conduction path layer has any one of an I shape, a square shape, an inverted trapezoidal shape, an inverted tapered shape, or an inverted step tapered shape. Power module.
The power module according to claim 14, wherein the heat conduction path layer includes a plurality of constituent members.
The power module according to claim 15, wherein the heat conduction path layer includes a plurality of layer electrode structures.
The power module according to claim 10, wherein the heat conduction path layer includes a member having a higher thermal conductivity than the electric conduction path layer.
The power module according to claim 17, wherein the heat conduction path layer includes any one of silicon carbide, copper, silver, carbon, and graphite.
The power module according to claim 12 or 17, wherein the electrical conduction path layer comprises copper, and the thermal conduction path layer comprises silicon carbide or copper.
The power module according to any one of claims 1 to 19, wherein the first insulating substrate and the second insulating substrate include a ceramic substrate.
The vertical size of each of the heat conduction path layer and the electric conduction path layer is smaller than the size in the horizontal direction of the heat conduction path layer and the electric conduction path layer. The power module according to item 1.
The semiconductor device is used to configure any one of a one-in-one module, a two-in-one module, a four-in-one module, a six-in-one module, a seven-in-one module, an eight-in-one module, a twelve-in-one module, or a fourteen-in-one module. Item 22. The power module according to any one of Items 1 to 21.
The semiconductor device includes any one of Si-based IGBT, Si-based MOSFET, SiC-based MOSFET, SiC-based IGBT, SiC-based MOSFET and SiC-based IGBT, GaN-based FET, or a different plurality thereof. The power module according to any one of claims 1 to 22, wherein:
A first insulating substrate having a front surface and a back surface;
A semiconductor device mounted on the surface side of the first insulating substrate and generating heat during operation;
A second insulating substrate disposed on the semiconductor device opposite to the first insulating substrate and having a front surface and a back surface;
A first cooler disposed on a surface of the second insulating substrate opposite to the surface facing the semiconductor device;
One end is disposed on the semiconductor device and the other end is connected to an electrode pattern formed on the first insulating substrate to transmit an electric signal, and an electric conduction path layer.
One end is disposed on the semiconductor device, the other end is connected to the second insulating substrate, and a heat conduction path layer that conducts heat of the semiconductor device to the first cooler, and
The power module according to claim 1, wherein the electric conduction path layer includes an integrated block structure connected to the electrode pattern from a side surface of the heat conduction path layer.
A first insulating substrate;
A semiconductor device mounted on the first insulating substrate and generating heat during operation;
A second insulating substrate disposed on the semiconductor device to face the first insulating substrate;
A first cooler disposed on a surface of the second insulating substrate opposite to the surface facing the semiconductor device;
One end is disposed on the semiconductor device and the other end is connected to an electrode pattern formed on the first insulating substrate to transmit an electric signal, and an electric conduction path layer.
A heat conduction path layer disposed on the second insulation substrate side of the electrical conduction path layer and connected to the second insulation substrate to conduct heat of the semiconductor device to the first cooler. A featured power module.
An inverter device that performs power conversion using a power module in which a circuit including a semiconductor device connected between a power supply terminal and a reference terminal is formed,
The power module is
A first insulating substrate;
The semiconductor device mounted on the first insulating substrate and generating heat during operation;
A second insulating substrate disposed on the semiconductor device opposite to the first insulating substrate on a side opposite to the surface facing the semiconductor device;
One end is connected to an electrode pad formed on the semiconductor device, the other end is connected to an electrode pattern formed on the first insulating substrate, and the current from the semiconductor device is not passed through the second insulating substrate. An electrically conductive path layer flowing through the electrode pattern;
One end is disposed on the semiconductor device, the other end is connected to the second insulating substrate side, and a heat conduction path layer that transfers heat of the semiconductor device to the second insulating substrate,
An inverter device comprising: at least the semiconductor device, the electric conduction path layer, the heat conduction path layer, and a mold resin that seals a part of each terminal.