TWI852755B - Hot plugging control system - Google Patents

Abstract

A hot plugging control system, comprising: a main board, including a CPU, at least one hot plugging chip, and a plurality of MB connectors, wherein the CPU and the hot plugging chip are electronically connected, and the hot plugging chip and the MB connectors are electronically connected; and a plurality of back planes, each including: a BP connector, and a control chip, wherein the control chip and the BP connector are electronically connected, and BP connectors and MB connectors are electronically connected correspondingly; wherein the main board and back planes are I2C communicating two-ways via the hot plugging chip; wherein when at least one hard disk and one back plane are connected, the CPU being communicating with the hard disk.

Description

Hot Swap Control System

The present invention relates to a hot-swap control system, and more particularly to a hot-swap control system that uses a bus circuit for communication between integrated circuits.

Please refer to the first figure, which is a schematic diagram of the existing technology of the hot plug control system. The so-called hot plug (Hot Plugging, or Hot Swapping, also known as hot replacement) refers to the state of plugging and unplugging while the power is on, that is, the action of plugging or unplugging the hardware can be performed while the computer host is still running without turning off the power. As long as there is an appropriate design, it can be carried out without causing the computer host or its peripheral equipment to burn out.

Generally speaking, in the prior art, the hot-swap function design architecture is that the source central processing unit (CPU) 11 located on the motherboard 1 performs hot-swap inter-circuit bus (I2C, also known as the Inter-Integrated Circuit Bus) communication. First, the low-speed sideband connector 12 located on the motherboard 1 is connected to each backplane 3 through the sideband transmission line 2. Plane, abbreviated as BP) (only one is marked in the figure) to achieve physical layer connection; and when the small backplane of the unit (for example, 2 NVMe backplanes) needs to be combined into multiple backplanes (for example, 14 NVMe backplanes), a large number of backplanes 3 (for example, seven backplanes) are required. Therefore, the complex programmable logic elements (CPLC) of the seven backplanes 3 are Device, referred to as CPLD) (not shown in the figure), for example, if the PCA9555 chip is used, the bus circuit addresses between the integrated circuits need to be different, so there will be a need for more firmware (generally referred to as FW) for control, or the need for the design of multiple special transmission lines, such as the need for a special design of transmission line 2 with a one-to-seven interface as shown in the first figure, which increases the complexity of the structure and the increase in cost.

In view of the structural complexity and cost problems that may arise in the prior art, the present invention adopts necessary technical means to solve the problems of the prior art, which is to provide a hot-swap control system, including: a motherboard, including a central processing unit, at least one hot-swap chip, and a plurality of motherboard connectors, wherein the central processing unit and the hot-swap chip are interconnected in telecommunication, and the hot-swap chip and the plurality of motherboard connectors are interconnected in telecommunication; and a plurality of backplanes, each backplane comprising: a backplane connector, and a control chip, wherein the control chip and the backplane connector are interconnected by telecommunication, and the plurality of backplane connectors are correspondingly interconnected by telecommunication with a plurality of mainboard connectors; wherein the mainboard and the plurality of backplanes can perform bidirectional communication of an integrated circuit bus circuit through a hot-swappable chip, and when at least one hard drive is connected to one of the backplanes, the central processing unit can communicate with the hard drive.

In an auxiliary technical means derived from the above necessary technical means, each backplane control chip includes an inter-IC bus circuit address, and each inter-IC bus circuit address is the same.

In an auxiliary technical means derived from the above necessary technical means, the corresponding telecommunication connections between the plurality of backplane connectors and the plurality of mainboard connectors are connected to each other one-to-one through a plurality of transmission lines.

As described above, since the hot-swap control system of the present invention utilizes a hot-swap chip added to the motherboard as a switch to perform bus circuit communication between integrated circuits, the present invention can effectively achieve the same standardized design of transmission lines and firmware (with the same address) of complex programmable logic components through this design.

The specific embodiments of the present invention will be further described by the following embodiments and drawings.

Please refer to the second figure, which is a circuit diagram of the hot swap control system provided by the preferred embodiment of the present invention.

In accordance with the Non-Volatile Memory In an application scenario where a small number of hard disks are combined to meet the needs of combining a backplane 6 (only one is marked in the figure) of a NVMe (NVMe Express) protocol, the present invention utilizes a hot-swappable integrated circuit bus circuit of the source to expand through a hot-swappable chip 42 (only one is marked in the figure) of the integrated circuit bus circuit as a switch, so as to achieve the same standardization of the firmware (with the same address) of a transmission line 5 (only one is marked in the figure) and a complex scalable logic element 61 (only one is marked in the figure), so that a backplane (not shown in the figure) of a hard disk that complies with the non-volatile memory communication protocol can be hot-swapped.

As shown in the figure, a hot-swap control system of the present invention is disclosed, which includes: a main board 4 (Multilayer Printed Board, MLB for short, also called multi-layer board), and a plurality of backplanes 6.

The motherboard 4 includes a central processing unit 41, at least one hot-swap chip 42, and a plurality of motherboard connectors, wherein the central processing unit 41 and the hot-swap chip 42 are connected to each other by telecommunication, and the hot-swap chip 42 and the plurality of motherboard connectors are connected to each other by telecommunication. The hot-swap chip is a PCA9545 chip. The motherboard connector is a high-speed connector, such as an MCIO connector 43 (Mini Cool Edge IO, referred to as MCIO) (only one is marked in the figure).

In addition, there are a plurality of backplanes 6, and the backplane 6 is a device that complies with the non-volatile memory express (NVMe) communication protocol. Each backplane 6 includes: a backplane connector, and a control chip, wherein the control chip and the backplane connector are interconnected by telecommunication, and the plurality of backplane connectors and the plurality of motherboard connectors are correspondingly interconnected by telecommunication. The backplane connector is also a high-speed connector, such as an MCIO connector 62 (only one is marked in the figure). The control chip as mentioned above is a complex programmable logic element 61, and the control chip 61 of each backplane 6 includes an inter-IC bus circuit address, and each inter-IC bus circuit address is the same. In addition, the multiple backplane connectors and the multiple mainboard connectors are correspondingly connected to each other in a one-to-one manner through multiple transmission lines 5, that is, these multiple transmission lines 5 are all one-to-one transmission lines.

Among them, the motherboard 4 and multiple backplanes 6 can perform bidirectional communication of an integrated circuit bus circuit through a hot-swappable chip 42, and when at least one hard drive (not shown in the figure) is connected to one of the backplanes 6, the central processing unit 41 can communicate with the hard drive. However, preferably, the same backplane 6 can be connected to two of the aforementioned hard drives at the same time for communication.

The working principle of the present invention is roughly described as follows. At the motherboard 4 end, the hot-swappable integrated circuit bus circuit of the central processing unit 41 uses the hot-swappable chip 42 (such as the PCA9545 chip) of the integrated circuit bus circuit as a switch to expand a multi-channel system management bus (System Management Bus, abbreviated as SMBUS). Since the backplane 6 that complies with the non-volatile memory communication protocol itself needs to have a high-speed PCIe interface MCIO connector 43 to connect to the MCIO connector 62 of each backplane 6.

In addition, the signal of the system management bus can be defined in the pin pins of the sideband of the MCIO connectors 43 and 62, and the transmission line 5 is connected to the MCIO connector 43 of the motherboard 4 and the corresponding MCIO connector 62 of the backplane 6 in a one-to-one manner. The definition of the pin pins of the transmission line 5 can be unified to achieve a simplified method of the transmission line 5, and the address of the bus circuit between the integrated circuits of the complex programmable logic element 61 is written in the firmware (for example, the address is 0x40). Because the hot-swappable chip 42 of the source bus circuit between the integrated circuits will expand the bus as a switch, and the basic input/output system (Basic Input/Output System) of the computer host After reading, the BIOS will close the relevant channel, so there will be no address duplication problem at the same address.

For example, when there are eight channels in total, you can use the different time sequences of the external hard drives inserted into the backplane to stagger the buffering. When one channel is connected, the other channels will wait first, so there will be no problem of address duplication.

In addition, when at least two external hard disk backplanes are communicating at the same time, the corresponding MCIO connectors 43 and 62 will be different. At this time, the central processor 41 can still distinguish which external hard disk backplane is hot-plugging for subsequent communication connection operations.

In summary, since the hot-swap control system of the present invention utilizes a hot-swap chip 42 added to the motherboard 4 as a switch to perform bus circuit communication between integrated circuits, the present invention can effectively achieve the same standardized design of the transmission line 5 and the firmware (with the same address) of the complex programmable logic element 61 through this design. Therefore, the present invention has the following advantages:

Advantage 1: The stub design of the branching routing of the bus circuit between integrated circuits is reduced, which can improve signal quality and increase the reliability of hot plugging. Advantage 2: There is no need for the sideband transmission line 2 of the backplane 3 as in the prior art of the first figure, but only a few transmission lines 5 of the same specification are needed to achieve the purpose, which can effectively reduce costs. Advantage 3: The firmware of the complex programmable logic element 61 is unified and fixed, and the material number of the hot plug control chip 42 is relatively easy to control. Advantage 4: The number of bus circuit addresses between integrated circuits can be unlimited, and there is no limit on the upper limit of 8 addresses like some other chips.

The above detailed description of the preferred specific embodiments is intended to more clearly describe the features and spirit of the present invention, but is not intended to limit the scope of the present invention by the preferred specific embodiments disclosed above. On the contrary, the purpose is to cover various changes and arrangements with equivalents within the scope of the patent application for the present invention.

1: Motherboard 11: Central Processing Unit 12: Connectors 2: Transmission Lines 3: Backplane 4: Motherboard 41: Central Processing Unit 42: Hot Swappable Chip 43: MCIO Connector 5: Transmission Lines 6: Backplane 61: Complex Scalable Logic Components 62: MCIO Connector

The first figure is a schematic diagram showing the prior art of a hot-swap control system; and The second figure is a circuit schematic diagram showing the hot-swap control system provided by a preferred embodiment of the present invention.

4: Motherboard

41: Central Processing Unit

42: Hot-swappable chips

43:MCIO connector

5: Transmission line

6: Back panel

61: Complex programmable logic components

62:MCIO connector

Claims (9)

A hot-swap control system, the system comprises: a mainboard, including: a central processing unit, at least one hot-swap chip, and a plurality of mainboard connectors, wherein the central processing unit and the hot-swap chip are mutually connected in telecommunication, and the hot-swap chip and the plurality of mainboard connectors are mutually connected in telecommunication; and a plurality of backplanes, each of the backplanes comprises: a backplane connector, and a control chip, the control chip comprises an inter-IC bus circuit address, wherein the control chip and the backplane connector are mutually connected in telecommunication, and the plurality of backplane connectors are mutually connected in telecommunication. The plurality of motherboard connectors are connected to each other in correspondence to form a plurality of channels respectively, and each of the bus circuit addresses between the integrated circuits is the same; wherein the motherboard and the plurality of backplanes can use the hot-swap chip as a switch to perform bidirectional communication of the bus circuit between the integrated circuits, and when at least one hard drive is connected to one of the backplanes, the central processor can communicate with the hard drive through the corresponding channel between the corresponding backplane connector and the motherboard connector, and the corresponding channel will be closed after the communication is completed. A hot-swap control system as described in claim 1, wherein the hot-swap chip is a PCA9545 chip. The hot-swap control system as described in claim 1, wherein the motherboard connector and the backplane connector are both high-speed connectors. A hot-swap control system as described in claim 3, wherein the high-speed connector is an MCIO connector. A hot-swap control system as described in claim 1, wherein the control chip is a complex programmable logic element. As described in claim 1, the hot-swap control system, wherein the corresponding telecommunication connections between the plurality of backplane connectors and the plurality of motherboard connectors are connected to each other one-to-one through a plurality of transmission lines. A hot-swap control system as described in claim 6, wherein the plurality of transmission lines are one-to-one transmission lines. A hot-swap control system as described in claim 1, wherein the backplane is a device that complies with the non-volatile memory express (NVMe) communication protocol. A hot-swap control system as described in claim 1, wherein the backplane can be connected to two hard drives at the same time.

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