TWI850376B - Semiconductor device - Google Patents

Abstract

The present disclosure provides a semiconductor device which includes an active structure and a first semiconductor layer. The active structure includes an active region and a first dopant having a first conductivity type. The active region has a topmost surface and a bottommost surface. The first dopant distributes from the topmost surface to the bottommost surface. The first semiconductor layer is located under the active structure and includes a second dopant having a second conductivity type. The active region includes a quaternary semiconductor material. The quaternary semiconductor material includes arsenic (As).

Description

Semiconductor components

The present invention relates to semiconductor devices, and in particular to semiconductor light-emitting devices, such as light-emitting diodes.

Semiconductor components have a wide range of uses, and the development and research of related materials are also ongoing. For example, III-V semiconductor materials containing group III and group V elements can be applied to various optoelectronic semiconductor components such as light emitting diodes (LEDs), laser diodes (LDs), photodetectors or solar cells, or can be power components such as switches or rectifiers, which can be used in lighting, medical, display, communication, sensing, power supply systems and other fields. As one of the semiconductor light-emitting components, the light-emitting diode has the advantages of low power consumption and long life, so it is widely used in various fields. With the development of technology, there is still a lot of demand for technical research and development of semiconductor components.

The present invention provides a semiconductor device, which includes an active structure and a first semiconductor layer. The active structure includes an active region and a first dopant with a first conductivity type. The active region has an uppermost surface and a lowermost surface. The first dopant is distributed from the uppermost surface to the lowermost surface. The first semiconductor layer is located under the active structure and includes a second dopant with a second conductivity type. The active region includes a quaternary semiconductor material. The quaternary semiconductor material includes arsenic (As).

The following embodiments will be accompanied by drawings to illustrate the concept of the present invention. In the drawings or descriptions, similar or identical components will be described using similar or identical reference numerals, and unless otherwise specified, the shapes or sizes of the components in the drawings are only examples and are not limited thereto. It should be noted that components not shown or described in the drawings may be forms known to those skilled in the art.

Unless otherwise specified, the general formula InGaAs represents In _z1 Ga _1-z1 As, where 0>z1>1; the general formula InAlAs represents In _z2 Al _1-z2 As, where 0>z2>1; InGaAsP represents In _z3 Ga _1-z3 As _z4 P _1-z4 , where 0>z3>1, 0>z4>1; AlGaInAs represents (Al _z5 Ga _(1-z5) ) _z6 In _1-z6 As, where 0>z5>1, 0>z6>1; the general formula AlGaInP represents (Al _z7 Ga _(1-z7) ) _z8 In _1-z8 P, where 0>z7>1, 0>z8>1. The composition and dopant of each layer included in the semiconductor device disclosed herein can be analyzed by any suitable method, such as secondary ion mass spectrometer (SIMS), and the thickness of each layer can also be analyzed by any suitable method, such as transmission electron microscopy (TEM) or scanning electron microscope (SEM). In addition, each dopant mentioned in the disclosed content can be intentionally added or unintentionally added. Intentional addition is, for example, by in-situ doping during epitaxial growth and/or by implanting P-type or N-type dopant after epitaxial growth. Unintentional addition is, for example, generated during the manufacturing process.

It should be understood by those skilled in the art that other components may be added to the embodiments described below. For example, unless otherwise specified, a similar description of "a first layer (or structure) is located on a second layer (or structure)" may include an embodiment in which the first layer (or structure) is in direct contact with the second layer (or structure), and may also include an embodiment in which the first layer (or structure) and the second layer (or structure) are not in direct contact with each other with other structures between them. In addition, it should be understood that the upper and lower positional relationship of each layer (or structure) may change due to observation from different directions. In addition, in the present disclosure, the description that a layer or structure “substantially consists of X” means that the main component of the layer or structure is X, but does not exclude that the layer or structure contains dopants or unavoidable impurities.

FIG. 1 is a top view of the structure of a semiconductor device 100 according to an embodiment of the present disclosure. FIG. 2 is a schematic diagram of the cross-sectional structure of the semiconductor device 100 along the A-A' line of FIG. 1. As shown in FIG. 1, the semiconductor device 100 is a rectangle when viewed from above. In one embodiment, the length and width of the semiconductor device 100 may be greater than or equal to 100 μm and less than or equal to 500 μm, such as 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm. In one embodiment, the length and width of the semiconductor device 100 are substantially equal. As shown in FIG. 2 , the semiconductor device 100 of the present embodiment includes a substrate 10, an active structure 12, a first semiconductor layer 14, a second semiconductor layer 16, a first electrode 18, and a second electrode 20. In some embodiments, the first semiconductor layer 14, the active structure 12, and the second semiconductor layer 16 can be grown on the substrate 10 or bonded to the substrate 10 by an epitaxial method, that is, the substrate 10 can be a growth substrate or a non-growth substrate. The substrate 10 can be used to support semiconductor stacks and other layers or structures thereon. The active structure 12 is located on the first side 10a of the substrate 10. The second electrode 20 is located on the second side 10b of the substrate 10. In the present embodiment, the second electrode 20 is adjacent to the substrate 10 and directly contacts the surface of the substrate 10. The first semiconductor layer 14 is located below the active structure 12. As shown in FIG. 2 , the first semiconductor layer 14 is located between the substrate 10 and the active structure 12. The second semiconductor layer 16 is located on the active structure 12. The first electrode 18 is located on the second semiconductor layer 16. The semiconductor device 100 can emit radiation when in operation.

In one embodiment, the substrate 10 is a growth substrate and can be a conductive substrate, which can include conductive materials such as gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), gallium phosphide (GaP), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN), germanium (Ge) or silicon (Si). The substrate 10 can be transparent, semi-transparent or opaque to the above radiation. For example, when the radiation emitted by the semiconductor device 100 is greater than 1000 nm, the substrate 10 preferably has a transmittance greater than 30% or an absorptivity less than 30% to the above radiation. In some embodiments, the substrate 10 may have a thickness greater than or equal to 60 µm and less than or equal to 250 µm, such as 100 µm, 130 µm, 140 µm, 150 µm, 160 µm, 170 µm, 180 µm, 200 µm, or 230 µm.

The semiconductor device 100 may include a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multiple quantum wells (MQW) structure. The radiation emitted by the semiconductor device 100 may be coherent or incoherent visible light or invisible light, preferably red light or infrared light, such as near infrared light (NIR). When the radiation is near-infrared light, it may have a peak wavelength between 800 nm and 2000 nm (inclusive), for example, about 810 nm, 850 nm, 910 nm, 940 nm, 1050 nm, 1070 nm, 1100 nm, 1200 nm, 1300 nm, 1400 nm, 1450 nm, 1500 nm, 1550 nm, 1600 nm, 1650 nm, 1700 nm, etc. In one embodiment, the semiconductor device 100 can only emit incoherent radiation but cannot emit coherent radiation, that is, the semiconductor device 100 does not have a threshold current (Ith).

In this embodiment, the active structure 12 includes a first confinement layer 120, a second confinement layer 122, and an active region 124 located between the first confinement layer 120 and the second confinement layer 122. The active structure 12 may have a first width w1, and the substrate 10 may have a second width w2 greater than the first width w1. In one embodiment, the first confinement layer 120, the active region 124, and the second confinement layer 122 all include ternary or quaternary semiconductor materials. The ternary or quaternary semiconductor materials may include aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P), or indium (In), such as InGaAs, InGaAsP, or AlGaInAs. In one embodiment, the first confinement layer 120, the active region 124 and the second confinement layer 122 all contain arsenic (As). Preferably, the first confinement layer 120, the active region 124 and the second confinement layer 122 are substantially composed of a quaternary semiconductor material, such as InGaAsP or AlGaInAs.

In one embodiment, the first confinement layer 120 comprises In _x1 Ga _1-x1 As _y1 P _1-y1 , wherein 0>x1>1, 0>y1>1; preferably, 0.5≤x1≤0.9 or/and 0.1≤y1≤0.4. In one embodiment, the second confinement layer 122 comprises In _x2 Ga _1-x2 As _y2 P _1-y2 , wherein 0>x2>1, 0>y2>1; preferably, 0.5≤x2≤0.9 or/and 0.1≤y2≤0.4. In one embodiment, the active region 124 comprises In _x3 Ga _1-x3 As _y3 P _1-y3 , wherein 0>x3>1, 0>y3>1; preferably, 0.5≤x3≤0.9 or/and 0.5≤y3≤0.9. In one embodiment, x1>x3 and x2>x3, y3>y1 and y3>y2. Preferably, the band gap of the first confinement layer 120 and the second confinement layer 122 is greater than the band gap of the active region 124. In one embodiment, the first confinement layer 120 has a first thickness t1, the second confinement layer 122 has a second thickness t2 and the active region 124 has a third thickness t3, and the third thickness t3 may be greater than the first thickness t1 and/or the second thickness t2. In one embodiment, the third thickness t3 may be more than 3 times and less than 10 times the first thickness t1 or the second thickness t2, for example, 4 times, 5 times, 6 times, 7 times, 8 times, 9 times. By having a relatively thick active region 124, the light-emitting volume of the semiconductor element can be increased, thereby improving the light-emitting efficiency. In one embodiment, the first thickness t1 and the second thickness t2 may be less than or equal to 90 nm and greater than 1 nm, for example, 80 nm, 70 nm, 60 nm, 50 nm, 40 nm, 30 nm, 20 nm or 10 nm. In some embodiments, under a fixed operating current, the forward voltage (vf) value of the semiconductor element with the first thickness t1 or the second thickness t2 greater than 90 nm may be larger than that of the semiconductor element with the first thickness t1 or the second thickness t2 not greater than 90 nm.

The first semiconductor layer 14 and the second semiconductor layer 16 are respectively located on both sides of the active structure 12 and are adjacent to the active structure 12. In one embodiment, the first semiconductor layer 14 has a fourth thickness t4, and the second semiconductor layer has a fifth thickness t5 that is greater than or equal to the fourth thickness t4. In one embodiment, the fifth thickness t5 may be more than 2 times and less than 10 times the fourth thickness t4, for example, 3 times, 4 times, 5 times, 6 times, 7 times, 8 times, 9 times. The first semiconductor layer 14 and the second semiconductor layer 16 may respectively include binary, ternary or quaternary III-V semiconductor materials, preferably aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P) or indium (In), and may not include nitrogen (N). Preferably, the first semiconductor layer 14 and the second semiconductor layer 16 respectively include at least two selected from the group consisting of aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P) and indium (In).

In one embodiment, the first semiconductor layer 14 and the second semiconductor layer 16 include binary or ternary semiconductor materials, such as InP, GaAs, InGaAs or InAlAs. Preferably, the first semiconductor layer 14 and the second semiconductor layer 16 are substantially composed of binary or ternary semiconductor materials (such as InP, GaAs, InGaAs or InAlAs). In one embodiment, the first semiconductor layer 14 and the second semiconductor layer 16 can be doped by in-situ doping during epitaxial growth and/or by implanting the dopant after epitaxial growth. The second semiconductor layer 16 can include a first dopant to have a first conductivity type. The first semiconductor layer 14 may include a second dopant to have a second conductivity type. The second conductivity type is different from the first conductivity type. The first conductivity type is, for example, a p-type and the second conductivity type is, for example, an n-type to provide holes or electrons, or the first conductivity type is, for example, an n-type and the second conductivity type is, for example, a p-type to provide electrons or holes. In one embodiment, the first dopant or the second dopant may be magnesium (Mg), zinc (Zn), silicon (Si) or tellurium (Te).

In one embodiment, the active structure 12 includes a first dopant. Specifically, the first dopant is distributed at least in the active region 124. In one embodiment, the active region 124 has an uppermost surface and a lowermost surface, and the first dopant is distributed from the uppermost surface to the lowermost surface of the active region 124. In some embodiments, the active region 124 includes a plurality of well layers and a plurality of barrier layers stacked alternately, and the first dopant is distributed in each well layer and each barrier layer. Furthermore, the aforementioned uppermost surface is the upper surface of the uppermost layer (well layer or barrier layer) in the active region 124, and the aforementioned lowermost surface is the lower surface of the lowermost layer (well layer or barrier layer) in the active region 124. Preferably, the first dopant is continuously distributed in the active structure 12 (as shown by line S1 in region II in FIG. 4 ). In one embodiment, the distribution range of the first dopant in the active structure 12 may be between the first confinement layer 120 and the second confinement layer 122 (including both). In other words, in one embodiment, the first confinement layer 120, the active region 124, and the second confinement layer 122 all have the first dopant. In one embodiment, the distribution range of the first dopant in the active structure 12 is only located in the active region 124 and the second confinement layer 122, and the first confinement layer 120 does not have the first dopant. In one embodiment, the distribution range of the first dopant in the active structure 12 is only located in the active region 124, and the second confinement layer 122 and the first confinement layer 120 do not have the first dopant. In the active region 124, the doping concentration of the first dopant may be in the range of 5x10 ¹⁵ cm ^-3 to 1.5x10 ¹⁸ cm ^-3 , preferably less than or equal to 1x10 ¹⁸ cm ^-3 , more preferably less than or equal to 5x10 ¹⁷ cm ^-3 , and further preferably greater than or equal to 1x10 ¹⁶ cm ^-3 , more preferably greater than or equal to 5x10 ¹⁶ cm ^-3 , and more preferably greater than or equal to 1x10 ¹⁷ cm ^-3 . In some embodiments, by including the first dopant in the active structure 12, the device characteristics can be further improved, such as increasing the light emission efficiency. Specifically, the first dopant can enter the first confinement layer 120, the active region 124 and/or the second confinement layer 122 from the second semiconductor layer 16 by diffusion, that is, the first dopant is not intentionally added to the first confinement layer 120, the active region 124 and/or the second confinement layer 122, for example, the first dopant is not added at all during the process of forming the first confinement layer 120, the active region 124 and/or the second confinement layer 122 by epitaxial deposition. Alternatively, the first dopant can also be intentionally added to the first confinement layer 120, the active region 124 and/or the second confinement layer 122. In another embodiment, the active structure 12 may be substantially composed of the active region 124, that is, the active structure 12 does not include the first confinement layer 120 and the second confinement layer 122. This simplifies the manufacturing process and helps to stabilize the device production. In this case, the first dopant may be continuously and uninterruptedly distributed in the active region 124 by diffusion or intentional addition.

As mentioned above, the first semiconductor layer 14 can provide electrons or holes. In addition, the first semiconductor layer 14 can also serve as a window layer (light extraction layer) to increase the light extraction efficiency. According to one embodiment, the doping concentration of the second dopant in the first semiconductor layer 14 can be in the range of 1x10 ¹⁵ cm ^-3 to 1x10 ¹⁹ cm ^-3 , preferably less than or equal to 1x10 ¹⁸ cm ^-3 , more preferably less than or equal to 5x10 ¹⁷ cm ^-3 , and further preferably greater than or equal to 1x10 ¹⁶ cm ^-3 . In some embodiments, the maximum value of the doping concentration of the second dopant in the first semiconductor layer 14 is greater than or equal to the maximum value of the doping concentration of the first dopant in the active region 124. The doping concentration of the first dopant in the first semiconductor layer 14 is less than or equal to the doping concentration of the second dopant. Preferably, the doping concentration of the first dopant is less than the doping concentration of the second dopant at all locations in the first semiconductor layer 14 (see FIG. 4 ). In one embodiment, the doping concentration of the first dopant in the second semiconductor layer 16 may be less than or equal to the maximum value of the doping concentration of the second dopant in the first semiconductor layer 14. In one embodiment, the doping concentration of the first dopant in the second semiconductor layer 16 is greater than or equal to the doping concentration of the first dopant in the active region 124. The doping concentration of the first dopant in the second semiconductor layer 16 may be in the range of 1x10 ¹⁷ cm ^-3 to 1x10 ¹⁹ cm ^-3 , preferably greater than or equal to 5x10 ¹⁷ cm ^-3 , more preferably greater than or equal to 1x10 ¹⁸ cm ^-3 , and preferably less than or equal to 5x10 ¹⁸ cm ^-3 .

The first electrode 18 and the second electrode 20 are used to electrically connect to an external power source and the active structure 12. The first electrode 18 may include a main electrode 18a and a plurality of extended electrodes 18b. As shown in FIG. 1 , the main electrode 18a is located at the center of the semiconductor element 100, and the plurality of extended electrodes 18b surround the outer side of the main electrode 18a and are connected to the main electrode 18a. In this embodiment, each extended electrode 18b is in a T-shape. The materials of the first electrode 18 and the second electrode 20 may include metal oxide materials, metals or alloys. The metal oxide material includes indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO) or indium zinc oxide (IZO). The metal can be listed as germanium (Ge), benzium (Be), zinc (Zn), gold (Au), platinum (Pt), titanium (Ti), aluminum (Al), or nickel (Ni), copper (Cu), etc. The alloy may include at least two selected from the group consisting of the above metals, such as germanium gold nickel (GeAuNi), benzene gold (BeAu), germanium gold (GeAu), zinc gold (ZnAu), etc.

Figure 3 is a schematic diagram of the cross-sectional structure of a semiconductor element 200 of an embodiment of the present disclosure. The difference between the semiconductor element 200 of this embodiment and the semiconductor element 100 is that it further includes a window layer 17 and an intermediate layer 24. The window layer 17 is located between the second semiconductor layer 16 and the first electrode 18, and can be used as a light extraction layer to improve the luminous efficiency of the element. The window layer 17 may include binary, ternary or quaternary semiconductor materials, preferably aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P) or indium (In), and may not include nitrogen (N). For example, it includes phosphorus (P), indium (In), gallium (Ga) or arsenic (As). For example, the window layer 17 may include InP, GaAs, InAlAs or AlGaInAs. The window layer 17 and the second semiconductor layer 16 may include the same or different binary, ternary or quaternary III-V semiconductor materials. Preferably, the window layer 17 is substantially composed of a binary, ternary or quaternary semiconductor material, such as InP, GaAs, InAlAs or AlGaInAs. The window layer 17 may also include a first dopant. Preferably, the dopant concentration of the first dopant in the window layer 17 is higher than the dopant concentration of the first dopant in the second semiconductor layer 16. In one embodiment, the window layer 17 may have a first region and a second region (not shown), the first region is closer to the first electrode 18 than the second region, and the doping concentration of the first dopant in the first region is preferably higher than the doping concentration of the first dopant in the second region. In this way, the electrical contact characteristics between the window layer 17 and the first electrode 18 can be further improved.

The middle layer 24 may be located between the second semiconductor layer 16 and the active structure 12, for example, between the second semiconductor layer 16 and the second confinement layer 122. The middle layer 24 may include a binary semiconductor material, preferably aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P) or indium (In), and may not include nitrogen (N). For example, phosphorus (P), indium (In) or gallium (Ga), arsenic (As). In one embodiment, the middle layer 24 and the second semiconductor layer 16 include the same binary III-V semiconductor material, such as InP or GaAs. Preferably, the middle layer 24 is substantially composed of a binary semiconductor material, such as InP or GaAs. In some embodiments, when the intermediate layer 24 and the second semiconductor layer 16 include the same semiconductor material, the interface between the intermediate layer 24 and the second semiconductor layer 16 may not be obvious under SEM or TEM analysis, that is, the intermediate layer 24 and the second semiconductor layer 16 have a structure similar to a single layer as a whole.

In some embodiments, the intermediate layer 24 may also include a first dopant. The first dopant, for example, enters the intermediate layer 24 from the second semiconductor layer 16 by diffusion, that is, the first dopant is not intentionally added to the intermediate layer 24. For example, the first dopant is not added at all during the process of forming the intermediate layer 24 by epitaxial deposition. Specifically, the intermediate layer 24 may serve as a diffusion control layer to adjust the diffusion distance of the first dopant toward the active structure 12 and the first semiconductor layer 14. In some embodiments, when the first dopant diffuses excessively through the active structure 12 to the first semiconductor layer 14, resulting in a high dopant concentration (e.g., above 1x10 ¹⁷ cm ^-3 ) of the first dopant in the first semiconductor layer 14, device failure may occur. Therefore, it is preferred that the dopant concentration of the first dopant in the first semiconductor layer 14 is lower than 1x10 ¹⁷ cm ^-3 , and more preferably lower than 5x10 ¹⁶ cm ^-3 . In some embodiments, the intermediate layer 24 may have a thickness within a range of 30 nm to 250 nm, for example, approximately 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, 200 nm, 210 nm, 220 nm, 230 nm or 240 nm.

In some embodiments, when the thickness of the intermediate layer 24 is less than 30 nm, the effect of controlling diffusion is not significant, so that the first dopant with a high dopant concentration (e.g., 1x10 ¹⁷ cm ^-3 or more) exists in the first semiconductor layer 14. In some embodiments, for example, when the active structure 12 is substantially composed of the active region 124 (i.e., the active structure 12 does not include the first confinement layer 120 and the second confinement layer 122), the thickness of the intermediate layer 24 is preferably within the range of 100 nm to 250 nm, and more preferably within the range of 150 nm to 250 nm. Thereby, the semiconductor device can have better light-emitting efficiency. In some embodiments, when the active structure 12 includes the first confinement layer 120, the active region 124, and the second confinement layer 122, when the thickness of the intermediate layer 24 exceeds 150 nm, the peak wavelength of the radiation emitted by the semiconductor device may be shifted, so it is preferred that the thickness of the intermediate layer 24 is within a range of less than 150 nm. Based on the above, by providing the intermediate layer 24, it is easier to control the doping concentration variation of the first dopant in the active structure 12 to adjust the photoelectric characteristics of the device.

FIG. 4 is a SIMS image of the epitaxial structure of the semiconductor device 200. Referring to FIG. 4, region I may correspond to the second semiconductor layer 16 and the intermediate layer 24, region II may correspond to the active structure 12, and region III may correspond to the first semiconductor layer 14. Line S1 in FIG. 4 represents the doping concentration curve of the first dopant, and line S2 represents the doping concentration curve of the second dopant. In this embodiment, the first semiconductor layer 14, the intermediate layer 24, and the second semiconductor layer 16 all contain In and P, and the active structure 12 contains In, Ga, As, and P. In this embodiment, the intermediate layer 24 and the second semiconductor layer 16 are substantially composed of the same semiconductor material, so the interface between the intermediate layer 24 and the second semiconductor layer 16 is not obvious under SEM or TEM analysis and presents a structure similar to a single layer.

As shown in FIG. 4 , the first dopant is mainly distributed in regions I and II, and the dopant concentration of the first dopant in region I is greater than the dopant concentration of the first dopant in region II. The second dopant is mainly distributed in region III, and the maximum concentration _CM of the second dopant in region III is greater than the maximum concentration _BM of the first dopant in region II. In region III, the dopant concentration of the first dopant is significantly less than the maximum concentration _CM of the second dopant. In region III, the dopant concentration of the first dopant is, for example, less than 1/10 of the maximum concentration _CM of the second dopant. Region III can be divided into a first region R1 (left side) close to region II and a second region R2 (right side) far from region II. As shown in FIG. 4 , in the first region R1, the doping concentration of the first dopant is less than or equal to the doping concentration of the second dopant; in the second region R2, the doping concentration of the second dopant is less than or equal to the doping concentration of the first dopant. The doping concentration of the first dopant in region III may be less than 1×10 ¹⁷ cm ^-3 .

In some embodiments, the semiconductor device 200 may also have a form including the window layer 17 but not the intermediate layer 24, or only including the intermediate layer 24 but not the window layer 17. The positions, relative relationships, material compositions, and structural variations of other layers or structures in this embodiment have been described in detail in the previous embodiments and will not be repeated here.

FIG. 5 is a schematic diagram of the cross-sectional structure of a semiconductor device 300 according to an embodiment of the present disclosure. The difference between the semiconductor device 300 of the present embodiment and the semiconductor device 100 is that the semiconductor device 300 further includes an intermediate layer 24, a contact layer 26, and a transition layer (transient layer) 28. In this embodiment, the contact layer 26 is located between the second semiconductor layer 16 and the first electrode 18. By providing the contact layer 26, the electrical contact characteristics between the second semiconductor layer 16 and the first electrode 18 can be further improved. The contact layer 26 may include a binary or ternary semiconductor material, preferably aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P) or indium (In), and may not include nitrogen (N). In one embodiment, the contact layer 26 and the second semiconductor layer 16 include at least one common element, for example, both include indium (In), gallium (Ga) or arsenic (As). In one embodiment, the contact layer 26 includes a ternary III-V semiconductor material, and the second semiconductor layer 16 includes a binary III-V semiconductor material. In one embodiment, the contact layer 26 includes a binary III-V semiconductor material, and the second semiconductor layer 16 includes a ternary III-V semiconductor material. In one embodiment, the contact layer 26 includes GaAs or InGaAs. Preferably, the contact layer 26 is substantially composed of a binary or ternary semiconductor material (such as GaAs or InGaAs). The contact layer 26 may further include a third dopant, and the dopant concentration of the third dopant in the contact layer 26 may be greater than the dopant concentration of the first dopant in the second semiconductor layer 16. The contact layer 26 may have the same conductivity type (p-type or n-type) as the second semiconductor layer 16. The third dopant may be magnesium (Mg), zinc (Zn), silicon (Si), or tellurium (Te), and may be the same as or different from the first dopant. The doping concentration of the third dopant in the contact layer 26 may be greater than or equal to 1×10 ¹⁸ cm ⁻³ , preferably greater than or equal to 2×10 ¹⁸ cm ⁻³ , such as greater than or equal to 4×10 ¹⁸ cm ⁻³ , and may be less than or equal to 2×10 ¹⁹ cm ⁻³ , preferably less than or equal to 1×10 ¹⁹ cm ⁻³ .

Specifically, the thickness of the transition layer 28 may be greater than that of the contact layer 26. In one embodiment, the transition layer 28 comprises a quaternary semiconductor material, preferably aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P) or indium (In), and may not contain nitrogen (N). Preferably, the transition layer 28 is substantially composed of a quaternary semiconductor material. In one embodiment, the transition layer 28 and the contact layer 26 contain at least two or more of the same elements, for example, selected from the group consisting of indium (In), gallium (Ga) and arsenic (As). The transition layer 28 may include the same quaternary semiconductor material as the active region 124. In one embodiment, the transition layer 28 comprises In _x4 Ga _1-x4 As _y4 P _1-y4 , wherein 0>x4>1, 0>y4>1. Preferably, 0.5≤x4≤0.9, 0.5≤y4≤0.9. In one embodiment, when the transition layer 28 comprises In _x4 Ga _1-x4 As _y4 P _1-y4 and the active region 124 comprises In _x3 Ga _1-x3 As _y3 P _1-y3 , preferably x4≥x3 and y4≥y3. In one embodiment, the transition layer 28 may further comprise a fourth dopant. The doping concentration of the fourth dopant in the transition layer 28 may be greater than or equal to the doping concentration of the first dopant in the second semiconductor layer 16. The transition layer 28 has the same conductivity type (p-type or n-type) as the second semiconductor layer 16. The fourth dopant may be magnesium (Mg), zinc (Zn), silicon (Si) or tellurium (Te), and may be the same as or different from the first dopant.

In some embodiments, the semiconductor device 300 may include the contact layer 26 but not the transition layer 28, or include only the transition layer 28 but not the contact layer 26. The positions, relative relationships, material compositions, and structural variations of other layers or structures in this embodiment have been described in detail in the previous embodiments and will not be described again here.

FIG. 6 is a schematic diagram of a cross-sectional structure of a semiconductor device 400 according to an embodiment of the present disclosure. The difference between the semiconductor device 400 of this embodiment and the semiconductor device 200 is that the semiconductor device 400 further includes a reflective structure 30 and an adhesive layer 40. In this embodiment, the substrate 10 is a non-growth substrate, and the first semiconductor layer 14, the second semiconductor layer 16, the active structure 12, the other semiconductor layers and the reflective structure 30 are bonded to the substrate 10 through the adhesive layer 40.

The reflective structure 30 is located between the adhesive layer 40 and the first semiconductor layer 14. Specifically, the reflective structure 30 can be a single layer or multiple layers. In one embodiment, the reflective structure 30 can reflect the radiation emitted by the semiconductor element 400 to emit it outside the semiconductor element 400 toward the second semiconductor layer 16. The material of the reflective structure 30 is conductive and can include metal or alloy. Metals are, for example, copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel (Ni), platinum (Pt), or tungsten (W). The alloy can include at least two selected from the group consisting of the above metals. In one embodiment, the reflective structure 30 includes at least a first metal layer, a second metal layer, and a third metal layer (not shown). The first metal layer may be adjacent to the first semiconductor layer 14, the second metal layer may be adjacent to the adhesive layer 40, and the third metal layer may be located between the first metal layer and the second metal layer. According to one embodiment, the materials of the first metal layer, the second metal layer, and the third metal layer may include aluminum (Al), gold (Au), silver (Ag), titanium (Ti), or platinum (Pt), respectively. Preferably, the first metal layer, the second metal layer, and the third metal layer are substantially composed of aluminum (Al), gold (Au), silver (Ag), titanium (Ti), or platinum (Pt), respectively. Preferably, the materials of the first metal layer, the second metal layer and the third metal layer are different. In one embodiment, the reflective structure 30 may include a conductive Bragg reflector structure (Distributed Bragg Reflector structure, DBR).

The adhesive layer 40 is used to connect the substrate 10 and the reflective structure 30. In one embodiment, the adhesive layer 40 may include more than two sub-layers (not shown). The material of the adhesive layer 40 is conductive and may include a transparent conductive material, metal or alloy. The transparent conductive material includes but is not limited to indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), zinc oxide (ZnO), gallium phosphide (GaP), indium caesium oxide (ICO), indium tungsten oxide (IWO), indium titanium oxide (ITiO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium aluminum zinc oxide (GAZO), graphene or a combination of the above materials. The metal includes but is not limited to copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel (Ni), platinum (Pt) or tungsten (W). The alloy may include at least two selected from the group consisting of the above metals.

In another embodiment, similar to FIG. 6 , the intermediate layer 24 is not located between the second semiconductor layer 16 and the active structure 12 , but is located between the first semiconductor layer 14 and the active structure 12 , for example, the intermediate layer 24 is located between the first semiconductor layer 14 and the first confinement layer 120 . In this case, the distribution of the first dopant and the second dopant in the first semiconductor layer 14 and the intermediate layer 24 may correspond to region I shown in FIG. 4 , the distribution of the first dopant and the second dopant in the active structure 12 may correspond to region II shown in FIG. 4 , and the distribution of the first dopant and the second dopant in the second semiconductor layer 16 may correspond to region III shown in FIG. 4 , that is, the first dopant enters the intermediate layer 24 and the active structure 12 from the first semiconductor layer 14 by diffusion, or enters the intermediate layer 24 and the active structure 12 by doping, for example. The intermediate layer 24 can be used as a diffusion control layer to adjust the diffusion distance of the first dopant toward the active structure 12 and the second semiconductor layer 16.

FIG. 7 is a schematic diagram of a cross-sectional structure of a semiconductor device 500 according to an embodiment of the present disclosure. The semiconductor device 500 is similar to the semiconductor device 400. The semiconductor device 500 further includes an insulating layer 32 located between the reflective structure 30 and the first semiconductor layer 14. As shown in FIG. 7, the insulating layer 32 may cover a portion of the lower surface of the first semiconductor layer 14. In this embodiment, the width of the first semiconductor layer 14 is greater than the width of the active structure 12. The material of the insulating layer 32 may include an oxide insulating material or a non-oxide insulating material. For example, the oxide insulating material may include silicon oxide (SiO _x ) or a similar material; the non-oxide insulating material may include silicon nitride (SiN _x ), benzocyclobutene (BCB), cycloolefin copolymer (COC) or fluorocarbon polymer, calcium fluoride (CaF ₂ ) or magnesium fluoride (MgF ₂ ). In this embodiment, the first electrode 18 and the insulating layer 32 do not overlap in the vertical direction. In one embodiment, the insulating layer 32 does not overlap with the main electrode 18 a in the first electrode 18 in the vertical direction but overlaps with the extension electrode 18 b in the vertical direction.

As shown in FIG. 7 , the semiconductor device 500 may further include a conductive layer 34 covering the insulating layer 32. In this embodiment, the conductive layer 34 and the contact portion of the first semiconductor layer 14 may form a current path. The conductive layer 34 may include a transparent conductive material, metal or alloy. The transparent conductive material includes but is not limited to indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), zinc oxide (ZnO), gallium phosphide (GaP), indium caesium oxide (ICO), indium tungsten oxide (IWO), indium titanium oxide (ITiO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium aluminum zinc oxide (GAZO), graphene or a combination of the above materials. The metal includes but is not limited to copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel (Ni), platinum (Pt) or tungsten (W). The alloy may include at least two selected from the group consisting of the above metals.

In some embodiments, the semiconductor device 500 may also have a form including only the insulating layer 32 but not the conductive layer 34, or may have only the conductive layer 34 but not the insulating layer 32. The positions, relative relationships, material compositions, and structural variations of other layers or structures in this embodiment have been described in detail in the previous embodiments and will not be repeated here.

FIG. 8 is a schematic diagram of a semiconductor device package structure 600 according to an embodiment of the present disclosure. Referring to FIG. 8 , the package structure 600 includes a semiconductor device 60, a package substrate 61, a carrier 63, bonding wires 65, a contact structure 66, and a package material layer 68. The package substrate 61 may include ceramic or glass materials. The package substrate 61 has a plurality of through holes 62. The through holes 62 may be filled with conductive materials such as metals to facilitate electrical conduction and/or heat dissipation. The carrier 63 is located on the surface of one side of the package substrate 61 and also includes conductive materials such as metals. The contact structure 66 is located on the surface of the other side of the package substrate 61. In this embodiment, the contact structure 66 includes a first contact pad 66a and a second contact pad 66b, and the first contact pad 66a and the second contact pad 66b can be electrically connected to the carrier 63 through the through hole 62. In one embodiment, the contact structure 66 can further include a thermal pad (not shown), for example, located between the first contact pad 66a and the second contact pad 66b.

The semiconductor element 60 is located on the carrier 63. The semiconductor element 60 can be the semiconductor element described in any embodiment of the present disclosure (such as semiconductor elements 100, 200, 300, 400, 500). In this embodiment, the carrier 63 includes a first portion 63a and a second portion 63b, and the semiconductor element 60 is electrically connected to the second portion 63b of the carrier 63 via a bonding wire 65. The material of the bonding wire 65 can include metals, such as gold, silver, copper, aluminum, or an alloy containing at least any of the above elements. The packaging material layer 68 covers the semiconductor element 60 and has the effect of protecting the semiconductor element 60. Specifically, the packaging material layer 68 can include a resin material such as epoxy, silicone, etc. The packaging material layer 68 may further include a plurality of wavelength conversion particles (not shown) to convert the first light emitted by the semiconductor element 60 into a second light. The wavelength of the second light is greater than that of the first light.

Based on the above, according to the embodiments of the present disclosure, a semiconductor device can be provided, which has good epitaxial quality and optoelectronic characteristics, such as further improvement in luminous efficiency, wavelength stability and device reliability. Specifically, the semiconductor device of the present disclosure can be applied to products in the fields of lighting, medical treatment, display, communication, sensing, power supply system, etc., such as lamps, monitors, mobile phones, tablet computers, car dashboards, televisions, computers, wearable devices (such as watches, bracelets, necklaces, etc.), traffic signs, outdoor displays, medical equipment, etc.

Although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the relevant technical field should understand that some modifications or changes can be made without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the definition of the scope of the attached patent application. In addition, the contents of the above embodiments can be combined or replaced with each other under appropriate circumstances, and are not limited to the specific embodiments described. For example, the relevant parameters of a specific component disclosed in an embodiment or the connection relationship between a specific component and other components can also be applied to other embodiments, and all fall within the scope of protection of the present invention.

100, 200, 300, 400, 500, 60: semiconductor element 10: substrate 10a: first side 10b: second side 12: active structure 14: first semiconductor layer 16: second semiconductor layer 17: window layer 18: first electrode 18a: main electrode 18b: extension electrode 20: second electrode 24: intermediate layer 26: contact layer 28: transition layer 30: reflective structure 32: insulating layer 34: conductive layer 40: adhesive layer 61: packaging substrate 62: through hole 63: carrier 63a: First part 63b: second part 65: bonding line 66: contact structure 66a: first contact pad 66b: second contact pad 68: packaging material layer 120: first confinement layer 122: second confinement layer 124: active area 600: packaging structure R1: first region R2: second regions S1, S2: line t1: first thickness A-A': line t2: second thickness t3: third thickness t4: fourth thickness t5: fifth thickness w1: first width w2: second width I, II, III: regions B _M , C _M : maximum concentration

FIG. 1 is a top view of a semiconductor device structure according to an embodiment of the present disclosure.

FIG. 2 is a schematic diagram of the cross-sectional structure of the semiconductor element in FIG. 1 along line A-A’.

FIG. 3 is a schematic diagram of a cross-sectional structure of a semiconductor device according to an embodiment of the present disclosure.

FIG. 4 is a SIMS image of the epitaxial structure of a semiconductor device portion according to an embodiment of the present disclosure.

FIG. 5 is a schematic diagram of a cross-sectional structure of a semiconductor device according to an embodiment of the present disclosure.

FIG6 is a schematic diagram of a cross-sectional structure of a semiconductor device according to an embodiment of the present disclosure.

FIG. 7 is a schematic diagram of a cross-sectional structure of a semiconductor device according to an embodiment of the present disclosure.

FIG. 8 is a schematic diagram of a semiconductor device packaging structure according to an embodiment of the present disclosure.

100:Semiconductor components

10: Base

10a: First side

10b: Second side

12: Active structure

14: First semiconductor layer

16: Second semiconductor layer

18: First electrode

20: Second electrode

120: The first limit layer

122: Second limit layer

124: Active area

t1: first thickness

t2: Second thickness

t3: The third thickness

t4: fourth thickness

t5: fifth thickness

w1: first width

w2: second width

Claims (10)

A semiconductor element comprises: an active structure comprising an active region and a first dopant having a first conductivity type, the active region having an uppermost surface and a lowermost surface, and the first dopant being distributed from the uppermost surface to the lowermost surface; and a first semiconductor layer located under the active structure and comprising a second dopant having a second conductivity type; wherein the active region comprises a quaternary semiconductor material, and the quaternary semiconductor material comprises arsenic (As). A semiconductor device as described in claim 1, wherein the maximum value of the doping concentration of the second dopant in the first semiconductor layer is greater than or equal to the maximum value of the doping concentration of the first dopant in the active region. A semiconductor device as described in item 1 of the patent application, wherein the quaternary semiconductor material is InGaAsP or AlGaInAs. A semiconductor device as described in claim 1, wherein the semiconductor device has a double heterostructure or a multiple quantum well structure. The semiconductor device as claimed in claim 1, wherein in the active region, the doping concentration of the first dopant is less than or equal to 5×10 ¹⁷ cm ^-3 . The semiconductor device as described in claim 1 further comprises a second semiconductor layer located on the active structure. The semiconductor device as described in claim 6 further includes an intermediate layer located between the second semiconductor layer and the active structure. A semiconductor device as described in claim 7, wherein the intermediate layer comprises a binary semiconductor material. As described in item 1 of the patent application scope, the active structure further includes a first confinement layer and a second confinement layer, the active region is located between the first confinement layer and the second confinement layer, and the first dopant is distributed in the first confinement layer and the second confinement layer. As described in item 1 of the patent application scope, the active region includes a plurality of well layers and a plurality of barrier layers stacked alternately, and the first dopant is distributed in each of the well layers and each of the barrier layers.

Images