CN220569701U - Semiconductor element and semiconductor assembly - Google Patents
Semiconductor element and semiconductor assembly Download PDFInfo
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- CN220569701U CN220569701U CN202222719593.XU CN202222719593U CN220569701U CN 220569701 U CN220569701 U CN 220569701U CN 202222719593 U CN202222719593 U CN 202222719593U CN 220569701 U CN220569701 U CN 220569701U
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Abstract
本实用新型公开一种半导体元件,其包括一外延结构具有一第一外延叠层、一接触部、一绝缘部及一第一电极。第一外延叠层具有第一半导体结构、第二半导体结构位于第一半导体结构上、第一活性区位于第一半导体结构与第二半导体结构之间。接触部接触第一半导体结构且具有第一宽度的开口。绝缘部接触接触部且具有第二宽度的第一孔隙。第一电极位于第二半导体结构上且包含电极垫及延伸电极。其中,开口、第一孔隙与电极垫于一垂直方向上重叠,接触部与延伸电极于一垂直方向上重叠,且第一宽度不同于第二宽度。
The utility model discloses a semiconductor element, which includes an epitaxial structure having a first epitaxial stack, a contact part, an insulating part and a first electrode. The first epitaxial stack has a first semiconductor structure, a second semiconductor structure located on the first semiconductor structure, and a first active region located between the first semiconductor structure and the second semiconductor structure. The contact contacts the first semiconductor structure and has an opening of a first width. The insulating portion contacts the contact portion and has a first aperture of a second width. The first electrode is located on the second semiconductor structure and includes an electrode pad and an extended electrode. Wherein, the opening, the first pore and the electrode pad overlap in a vertical direction, the contact portion and the extended electrode overlap in a vertical direction, and the first width is different from the second width.
Description
本申请是中国实用新型申请(申请号:202123062555.3,申请日:2021年12月08日,实用新型名称:半导体元件)的分案申请。This application is a divisional application of the Chinese utility model application (Application Number: 202123062555.3, Application Date: December 08, 2021, Utility Model Name: Semiconductor Component).
技术领域Technical field
本实用新型涉及半导体元件,特别是涉及半导体发光元件,例如发光二极管。The utility model relates to semiconductor components, in particular to semiconductor light-emitting components, such as light-emitting diodes.
背景技术Background technique
半导体元件的用途十分广泛,相关材料的开发研究也持续进行。举例来说,包含三族及五族元素的III-V族半导体材料可应用于各种光电半导体元件如发光二极管(Lightemitting diode,LED)、激光二极管(Laser diode,LD)、光电侦测器或太阳能电池(Solarcell),或者可以是例如开关或整流器的功率元件,能用于照明、医疗、显示、通讯、感测、电源系统等领域。作为半导体发光元件之一的发光二极管具有耗电量低以及寿命长等优点,因此大量被应用。Semiconductor components are used in a wide range of applications, and research and development on related materials continues. For example, III-V semiconductor materials containing Group III and Group V elements can be used in various optoelectronic semiconductor devices such as light emitting diodes (LEDs), laser diodes (LD), photodetectors or Solar cells (Solarcells), or power components such as switches or rectifiers, can be used in lighting, medical, display, communication, sensing, power supply systems and other fields. As one of the semiconductor light-emitting elements, light-emitting diodes have the advantages of low power consumption and long life, so they are widely used.
实用新型内容Utility model content
本实用新型的目的在于提供一种半导体元件,以解决现有技术存在的问题。The purpose of this utility model is to provide a semiconductor element to solve the problems existing in the prior art.
本实用新型提供一种半导体元件,包括:外延结构,包含第一外延叠层,该第一外延叠层包括第一半导体结构、第二半导体结构及位于该第一半导体结构与该第二半导体结构之间的第一活性区,该第二半导体结构与该第一半导体结构具有相异的导电型态;多个接触部,位于该第一半导体结构下且接触该第一半导体结构;多个绝缘部,位于该接触部下且接触该接触部;第一电极,位于该第二半导体结构上且包含电极垫及延伸电极;其中,该接触部及该绝缘部与该电极垫于一垂直方向上互相错位,该接触部与该延伸电极于该垂直方向上重叠。The utility model provides a semiconductor element, including: an epitaxial structure, including a first epitaxial stack. The first epitaxial stack includes a first semiconductor structure, a second semiconductor structure, and an epitaxial structure located between the first semiconductor structure and the second semiconductor structure. The first active region between the second semiconductor structure and the first semiconductor structure has different conductivity types; a plurality of contact portions located under the first semiconductor structure and contacting the first semiconductor structure; a plurality of insulators The first electrode is located under the contact portion and in contact with the contact portion; the first electrode is located on the second semiconductor structure and includes an electrode pad and an extended electrode; wherein the contact portion, the insulating portion and the electrode pad are mutually connected in a vertical direction. Misaligned, the contact portion and the extended electrode overlap in the vertical direction.
于一剖面图中,该半导体元件还包括第一孔隙位于两相邻的该多个接触部之间,及第二孔隙位于两相邻之该多个绝缘部之间,该第一孔隙及该第二孔隙与该电极垫于该垂直方向上重叠。In a cross-sectional view, the semiconductor element further includes a first aperture located between two adjacent contact portions, and a second aperture located between two adjacent insulating portions, the first aperture and the plurality of adjacent insulating portions. The second pore overlaps the electrode pad in the vertical direction.
于一水平方向上,该第一孔隙的宽度及第二孔隙的宽度大于该电极垫的宽度。In a horizontal direction, the width of the first pore and the width of the second pore are greater than the width of the electrode pad.
该接触部的厚度小于该绝缘部的厚度。The thickness of the contact part is smaller than the thickness of the insulation part.
于一水平方向上该第一孔隙的宽度小于该第二孔隙的宽度。The width of the first pore is smaller than the width of the second pore in a horizontal direction.
该第一半导体结构具有朝向该第一活性区的第一表面及接触该接触部的第二表面,且该第一表面的宽度小于该第二表面的宽度。The first semiconductor structure has a first surface facing the first active region and a second surface contacting the contact portion, and the width of the first surface is smaller than the width of the second surface.
该半导体元件还包括导电层位于该绝缘部下,该导电层接触该绝缘部并填入该第一孔隙及该第二孔隙。The semiconductor element also includes a conductive layer located under the insulating part, the conductive layer contacts the insulating part and fills the first pore and the second pore.
该导电层填入接触该接触部。The conductive layer fills the contact portion.
该导电层连接该第一半导体结构。The conductive layer connects to the first semiconductor structure.
该第二孔隙与该多个接触部于该垂直方向上重叠。The second hole and the plurality of contact portions overlap in the vertical direction.
该半导体元件所发的光为红外光。The light emitted by the semiconductor element is infrared light.
该第一活性区的发光波长之波峰波长为730nm至1100nm。The peak wavelength of the luminescence wavelength of the first active region ranges from 730 nm to 1100 nm.
该外延结构另包含第二外延叠层位于该第一外延叠层上,该第二外延叠层具有第三半导体结构、第四半导体结构及第二活性区位于该第三半导体结构及该第四半导体结构之间,该第三半导体结构及该第四半导体结构具有相异的导电型态。The epitaxial structure further includes a second epitaxial stack located on the first epitaxial stack, the second epitaxial stack having a third semiconductor structure, a fourth semiconductor structure and a second active region located on the third semiconductor structure and the fourth Among the semiconductor structures, the third semiconductor structure and the fourth semiconductor structure have different conductive types.
该半导体元件还包括中间层位于该第一外延叠层及该第二外延叠层之间,该中间层包含pn结。The semiconductor device further includes an intermediate layer located between the first epitaxial stack and the second epitaxial stack, the intermediate layer including a pn junction.
该第一活性区及该第二活性区都发出波峰波长为730nm至1100nm的红外光。Both the first active area and the second active area emit infrared light with a peak wavelength of 730 nm to 1100 nm.
该第一半导体结构为p型,且该第二半导体结构为n型。The first semiconductor structure is p-type, and the second semiconductor structure is n-type.
该半导体元件还包括接合结构及基底,该接合结构位于该第一外延叠层及该基底之间。The semiconductor device also includes a bonding structure and a substrate, the bonding structure being between the first epitaxial stack and the substrate.
该半导体元件还包括反射层位于该第一外延叠层及该接合结构之间。The semiconductor device also includes a reflective layer located between the first epitaxial stack and the bonding structure.
该半导体元件还包括第二电极,该第二电极连接该基底远离该第一半导体结构的一侧。The semiconductor element further includes a second electrode connected to a side of the substrate away from the first semiconductor structure.
本实用新型另提供一种半导体组件,包括:封装基板;该半导体元件,位于该封装基板上;以及封装层,覆盖该半导体元件。The utility model also provides a semiconductor component, which includes: a packaging substrate; the semiconductor component is located on the packaging substrate; and a packaging layer covers the semiconductor component.
本实用新型的优点在于,其通过对半导体元件的设计,使其具有更佳的光电表现,例如:发光强度增加、顺向电压(Vf)降低等等优点,可应用于照明、医疗、显示、通讯、感测、电源系统等领域的产品,例如灯具、监视器、手机、平板计算机、车用仪表板、电视、计算机、穿戴装置(如手表、手环、项链等)、交通号志、户外显示器、医疗器材等。The advantage of this utility model is that through the design of semiconductor components, it has better optoelectronic performance, such as increased luminous intensity, reduced forward voltage (Vf), etc., and can be used in lighting, medical, display, Products in the fields of communications, sensing, power systems, etc., such as lamps, monitors, mobile phones, tablet computers, vehicle dashboards, TVs, computers, wearable devices (such as watches, bracelets, necklaces, etc.), traffic signals, outdoor Monitors, medical equipment, etc.
附图说明Description of drawings
图1为本实用新型一实施例的半导体元件的剖面示意图;Figure 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention;
图2为本实用新型另一实施例的半导体元件的外延结构示意图;Figure 2 is a schematic diagram of the epitaxial structure of a semiconductor element according to another embodiment of the present invention;
图3为本实用新型一实施例的半导体组件的剖面结构示意图;Figure 3 is a schematic cross-sectional structural diagram of a semiconductor component according to an embodiment of the present invention;
图4为本实用新型一实施例的感测模块的部分剖面结构示意图。Figure 4 is a partial cross-sectional structural diagram of a sensing module according to an embodiment of the present invention.
符号说明Symbol Description
100 半导体元件100 semiconductor components
1 第一外延叠层1 First epitaxial stack
11 第一半导体结构11 First Semiconductor Structure
111 接触部111 Contact Department
12 第二半导体结构12 Second semiconductor structure
13 第一活性区13 First active zone
131 第一阱层131 first well layer
132 第一阻障层132 First barrier layer
133 第二阱层133 Second well layer
134 第二阻障层134 Second barrier layer
135 第三阱层135 Third well layer
136 第三阻障层136 Third barrier layer
14 第一局限层14 First local level
15 第二局限层15 The second localization layer
2 第一电极2 first electrode
21 电极垫21 electrode pads
22 延伸电极22 extension electrode
3 第二电极3 second electrode
4 导电层4 conductive layer
5 反射层5 reflective layer
6 接合结构6 joint structure
7 基底7 base
8 绝缘部8 Insulation Department
8a 孔隙8a pores
81 中间层81 middle layer
811 第一重掺杂层811 First heavily doped layer
812 第二重掺杂层812 Second heavily doped layer
9 第二外延叠层9 Second epitaxial stack
91 第三半导体结构91 Third semiconductor structure
92 第四半导体结构92 Fourth semiconductor structure
93 第二活性区93 Second active zone
931 第四阱层931 Fourth well layer
932 第四阻障层932 Fourth barrier layer
933 第五阱层933 fifth well layer
934 第五阻障层934 fifth barrier layer
935 第六阱层935 Sixth well layer
936 第六阻障层936 Sixth barrier layer
94 第三局限层94 The third limited layer
95 第四局限层95 The fourth localized layer
T1 第一厚度T1 first thickness
T2 第二厚度T2 second thickness
T3 第三厚度T3 third thickness
T4 第四厚度T4 fourth thickness
300 半导体组件300 Semiconductor components
31 封装基板31 Package substrate
32 通孔32 through holes
33 载体33 carrier
33a 第一部分33a Part 1
33b 第二部分33b Part 2
35 接合线35 bonding wire
36 接触结构36 contact structure
36a 第一接触垫36a first contact pad
36b 第二接触垫36b second contact pad
38 封装层38 encapsulation layers
400 感测模块400 sensing module
420 乘载体420 carrier
411 第一半导体元件411 First semiconductor element
431 第二半导体元件431 Second semiconductor element
421 第一挡墙421 First retaining wall
422 第二挡墙422 Second retaining wall
423 第三挡墙423 The third retaining wall
424 载板424 carrier board
425 第一空间425 First Space
426 第二空间426 Second Space
具体实施方式Detailed ways
以下实施例将伴随着附图说明本实用新型的概念,在附图或说明中,相似或相同的构件将使用相似或相同的标号进行说明,并且若未特别说明,附图中各元件的形状或尺寸仅为例示,实际上并不限于此。需特别注意的是,图中未绘示或描述的元件,可以是本领域普通技术人员所知的形式。The following embodiments will illustrate the concept of the present invention along with the accompanying drawings. In the drawings or descriptions, similar or identical components will be described using similar or identical reference numerals, and if not otherwise specified, the shape of each element in the drawings or dimensions are only examples and are not actually limited thereto. It should be noted that components not shown or described in the figures may be in forms known to those of ordinary skill in the art.
在未特别说明的情况下,通式InGaP代表Inx0Ga1-x0P,其中0<x0<1;通式AlInP代表Alx1In1-x1P,其中0<x1<1;通式AlGaInP代表Alx2Gax3In1-x2-x3P,其中0<x2<1且0<x3<1;通式InGaAsP代表Inx4Ga1-x4Asx5P1-x5,其中0<x4<1,0<x5<1;通式AlGaInAs代表Alx6Gax7In1-x6-x7As,其中0<x6<1,0<x7<1;通式InGaNAs代表Inx8Ga1-x8Nx9As1-x9,其中0<x8<1,0<x9<1;通式InGaAs代表Inx10Ga1-x10As,其中0<x10<1;通式AlGaAs代表Alx11Ga1-x11As,其中0<x11<1。可依不同目的调整各元素的含量,例如但不限于调整能隙大小,或是当半导体元件为一发光元件时,可由此调整发光元件的主波长(domain wavelength)或峰值波长(peak wavelength)。Unless otherwise specified, the general formula InGaP represents In x0 Ga 1-x0 P, where 0<x0<1; the general formula AlInP represents Al x1 In 1-x1 P, where 0<x1<1; the general formula AlGaInP represents Al x2 Ga x3 In 1-x2-x3 P, where 0<x2<1 and 0<x3<1; the general formula InGaAsP represents In x4 Ga 1-x4 As x5 P 1-x5 , where 0<x4<1, 0 <x5<1; the general formula AlGaInAs represents Al x6 Ga x7 In 1-x6-x7 As, where 0<x6<1, 0<x7<1; the general formula InGaNAs represents In x8 Ga 1-x8 N x9 As 1-x9 , where 0<x8<1, 0<x9<1; the general formula InGaAs represents In x10 Ga 1-x10 As, where 0<x10<1; the general formula AlGaAs represents Al x11 Ga 1-x11 As, where 0<x11< 1. The content of each element can be adjusted according to different purposes, such as but not limited to adjusting the energy gap size, or when the semiconductor element is a light-emitting element, the domain wavelength or peak wavelength of the light-emitting element can be adjusted accordingly.
本实用新型的半导体元件例如是发光元件(例如:发光二极管(light-emittingdiode)、激光二极管(laser diode))、吸光元件(例如:光电二极管(photo-detector))或不发光元件。本实用新型的半导体元件包含的各层组成及掺质(dopant)可用任何适合的方式分析而得,例如二次离子质谱仪(secondary ion mass spectrometer,SIMS),而各层的厚度也可用任何适合的方式分析而得,例如穿透式电子显微镜(transmission electronmicroscopy,TEM)或是扫描式电子显微镜(scanning electron microscope,SEM)等。The semiconductor element of the present invention is, for example, a light-emitting element (such as a light-emitting diode, a laser diode), a light-absorbing element (such as a photo-detector), or a non-light-emitting element. The composition of each layer and dopant included in the semiconductor device of the present invention can be analyzed by any suitable method, such as secondary ion mass spectrometer (SIMS), and the thickness of each layer can also be determined by any suitable method. It is obtained by analysis using a transmission electron microscope (TEM) or a scanning electron microscope (SEM).
所属领域中具通常知识者应理解,可以在以下所说明各实施例的基础上添加其他构件。举例来说,在未特别说明的情况下,「第一层(或结构)位于第二层(或结构)上」的类似描述可包含第一层(或结构)与第二层(或结构)直接接触的实施例,也可包含第一层(或结构)与第二层(或结构)之间具有其他结构而彼此未直接接触的实施例。另外,应理解各层(或结构)的上下位置关系等可能因由不同方位观察而有所改变。Those of ordinary skill in the art should understand that other components can be added on the basis of each embodiment described below. For example, unless otherwise stated, similar descriptions such as "a first layer (or structure) is located on a second layer (or structure)" may include the first layer (or structure) and the second layer (or structure). Embodiments of direct contact may also include embodiments in which the first layer (or structure) and the second layer (or structure) have other structures but are not in direct contact with each other. In addition, it should be understood that the upper and lower position relationships of each layer (or structure) may change due to observation from different directions.
此外,在本实用新型中,一层或结构「实质上由M所组成」的叙述表示上述层或结构的主要组成为M,但并不排除上述层或结构包含掺质或不可避免的杂质(impurities)。In addition, in the present utility model, the statement that a layer or structure "substantially consists of M" means that the main component of the above-mentioned layer or structure is M, but it does not exclude that the above-mentioned layer or structure contains dopants or unavoidable impurities ( impurities).
图1为本实用新型一实施例的半导体元件100的剖面示意图。半导体元件100包含一外延结构,且外延结构包含一第一外延叠层1。半导体元件100还包含一第一电极2及一第二电极3分别位于第一外延叠层1的上下两侧、一导电层4、一反射层5、一接合结构6及一基底7。导电层4位于第一外延叠层1与反射层5之间,接合结构6位于基底7与反射层5之间。如图1所示,半导体元件100选择性地包含多个绝缘部8位于导电层4及第一外延叠层1之间,以及多个孔隙8a位于多个绝缘部8之间。导电层4接触多个绝缘部8并填入多个孔隙8a中,并接触第一外延叠层1。第一电极2可包含电极垫21以及延伸电极22与电极垫21相连接。在一实施例中,第一电极2仅包含电极垫未包含延伸电极。FIG. 1 is a schematic cross-sectional view of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 includes an epitaxial structure, and the epitaxial structure includes a first epitaxial stack 1 . The semiconductor device 100 further includes a first electrode 2 and a second electrode 3 respectively located on the upper and lower sides of the first epitaxial stack 1 , a conductive layer 4 , a reflective layer 5 , a bonding structure 6 and a substrate 7 . The conductive layer 4 is located between the first epitaxial stack 1 and the reflective layer 5 , and the bonding structure 6 is located between the substrate 7 and the reflective layer 5 . As shown in FIG. 1 , the semiconductor device 100 selectively includes a plurality of insulating portions 8 located between the conductive layer 4 and the first epitaxial stack 1 , and a plurality of pores 8 a located between the plurality of insulating portions 8 . The conductive layer 4 contacts the plurality of insulating portions 8 and fills the plurality of pores 8 a, and contacts the first epitaxial stack 1 . The first electrode 2 may include an electrode pad 21 and an extended electrode 22 connected to the electrode pad 21 . In one embodiment, the first electrode 2 only includes electrode pads and does not include extended electrodes.
第一外延叠层1包含一第一半导体结构11、一第二半导体结构12、一第一活性区13位于第一半导体结构11及第二半导体结构12之间、一第一局限层14位于第一活性区13及第一半导体结构11之间、及一第二局限层15位于第一活性区13及第二半导体结构12之间。第一半导体结构11与第二半导体结构12可具有相异的导电型态。例如,第一半导体结构11为n型,第二半导体结构12为p型;或者,第一半导体结构11为p型,第二半导体结构12为n型。由此,第一半导体结构11与第二半导体结构12可分别提供电子与空穴或空穴与电子。第一半导体结构11具有一第一掺质,第二半导体结构12具有一第二掺质,使第一半导体结构11及第二半导体结构12具有不同的导电性。第一掺质及第二掺质可以分别为碳(C)、锌(Zn)、硅(Si)、锗(Ge)、锡(Sn)、硒(Se)、镁(Mg)或碲(Te)。在本实施例中,第二半导体结构12为N型,且第一掺质为碲(Te)或硅(Si),第一半导体结构11为P型,且第一掺质为镁(Mg)或碳(C),且第一半导体结构11及第二半导体结构12的掺杂浓度约为5×1017/cm3至1×1020/cm3。第一半导体结构11及第二半导体结构12的能隙分别大于第一局限层14及第二局限层15,由此将载流子更进一步地限制在第一活性区13中。The first epitaxial stack 1 includes a first semiconductor structure 11, a second semiconductor structure 12, a first active region 13 located between the first semiconductor structure 11 and the second semiconductor structure 12, and a first confinement layer 14 located between the first semiconductor structure 11 and the second semiconductor structure 12. An active region 13 is located between the first semiconductor structure 11 and a second confinement layer 15 is located between the first active region 13 and the second semiconductor structure 12 . The first semiconductor structure 11 and the second semiconductor structure 12 may have different conductive types. For example, the first semiconductor structure 11 is n-type and the second semiconductor structure 12 is p-type; or the first semiconductor structure 11 is p-type and the second semiconductor structure 12 is n-type. Therefore, the first semiconductor structure 11 and the second semiconductor structure 12 can respectively provide electrons and holes or holes and electrons. The first semiconductor structure 11 has a first dopant, and the second semiconductor structure 12 has a second dopant, so that the first semiconductor structure 11 and the second semiconductor structure 12 have different conductivities. The first dopant and the second dopant may be carbon (C), zinc (Zn), silicon (Si), germanium (Ge), tin (Sn), selenium (Se), magnesium (Mg) or tellurium (Te) respectively. ). In this embodiment, the second semiconductor structure 12 is N-type, and the first dopant is tellurium (Te) or silicon (Si). The first semiconductor structure 11 is P-type, and the first dopant is magnesium (Mg). or carbon (C), and the doping concentration of the first semiconductor structure 11 and the second semiconductor structure 12 is about 5×10 17 /cm 3 to 1×10 20 /cm 3 . The energy gaps of the first semiconductor structure 11 and the second semiconductor structure 12 are respectively larger than the first confinement layer 14 and the second confinement layer 15 , thereby further confining the carriers in the first active region 13 .
由半导体元件100的剖面观之,第一外延叠层1可选择性包含多个接触部111远离第一活性区13且靠近导电层4。半导体元件100包含间隙111a位于两相邻的多个接触部111之间。多个接触部111具有第一掺质,且多个接触部111中的第一掺质浓度大于第一半导体结构11的第一掺质浓度。在本实施例中,在电极垫21下方未设有接触部111,即电极垫21与多个接触部111于垂直方向上互相错位。换言之,于垂直方向上,电极垫21与间隙111a重叠。于水平方向上,间隙111a的宽度大于电极垫21的宽度。在其他实施例中,多个接触部111与电极垫21及延伸电极22可互相错位。通过上述的第一电极2与接触部111的错位关系,可以防止电流直接由第一电极2下方导通,由此增加电流散布,进而提高半导体元件100的亮度。多个接触部111的材料可包含III-V族半导体材料,例如二元III-V族半导体材料如GaAs、GaP、GaN等。Viewed from the cross-section of the semiconductor device 100 , the first epitaxial stack 1 may selectively include a plurality of contact portions 111 away from the first active region 13 and close to the conductive layer 4 . The semiconductor device 100 includes a gap 111 a between two adjacent contact portions 111 . The plurality of contact portions 111 have a first dopant, and the first dopant concentration in the plurality of contact portions 111 is greater than the first dopant concentration of the first semiconductor structure 11 . In this embodiment, there is no contact portion 111 below the electrode pad 21 , that is, the electrode pad 21 and the plurality of contact portions 111 are offset from each other in the vertical direction. In other words, in the vertical direction, the electrode pad 21 overlaps the gap 111a. In the horizontal direction, the width of the gap 111 a is larger than the width of the electrode pad 21 . In other embodiments, the plurality of contact portions 111, the electrode pads 21 and the extended electrodes 22 may be offset from each other. Through the above-mentioned misaligned relationship between the first electrode 2 and the contact portion 111 , current can be prevented from being directly conducted under the first electrode 2 , thereby increasing current dispersion and thereby improving the brightness of the semiconductor element 100 . The material of the plurality of contacts 111 may include a III-V semiconductor material, such as a binary III-V semiconductor material such as GaAs, GaP, GaN, etc.
多个绝缘部8位于多个接触部111下且接触该多个接触部111。多个绝缘部8包括第一绝缘部81及第二绝缘部82。多个孔隙8a包括位于第一绝缘部81与第二绝缘部82之间的第一孔隙8a1。在一实施例中,在电极垫21下方未设有绝缘部8,即电极垫21与多个绝缘部8于垂直方向上互相错位。换言之,电极垫21与第一孔隙8a1于垂直方向上重叠。于水平方向上,第一孔隙8a1的宽度大于电极垫21的宽度。在一实施例中,第一孔隙8a1的宽度大于间隙111a的宽度。The plurality of insulating portions 8 are located under the plurality of contact portions 111 and contact the plurality of contact portions 111 . The plurality of insulating parts 8 includes a first insulating part 81 and a second insulating part 82 . The plurality of holes 8a include a first hole 8a1 located between the first insulating part 81 and the second insulating part 82. In one embodiment, there is no insulating portion 8 below the electrode pad 21 , that is, the electrode pad 21 and the plurality of insulating portions 8 are offset from each other in the vertical direction. In other words, the electrode pad 21 and the first hole 8a1 overlap in the vertical direction. In the horizontal direction, the width of the first hole 8a1 is greater than the width of the electrode pad 21. In one embodiment, the width of the first aperture 8a1 is greater than the width of the gap 111a.
在一实施例中,多个绝缘部8还包括第三绝缘部83。多个孔隙8a还包括位于第二绝缘部82及第三绝缘部83之间的第二孔隙8a2,于垂直方向上,第二孔隙8a2与接触部111重叠且与电极垫21不重叠。在一实施例中,导电层4可填入第一孔隙8a1及第二孔隙8a2并接触多个接触部111,且导电层4可填入间隙111a与第一半导体结构11连接。In one embodiment, the plurality of insulating parts 8 further include a third insulating part 83 . The plurality of pores 8a also include a second pore 8a2 located between the second insulating part 82 and the third insulating part 83. In the vertical direction, the second pore 8a2 overlaps the contact part 111 and does not overlap the electrode pad 21. In an embodiment, the conductive layer 4 can fill the first pore 8a1 and the second pore 8a2 and contact the plurality of contacts 111, and the conductive layer 4 can fill the gap 111a and connect with the first semiconductor structure 11.
第一半导体结构11、第二半导体结构12、第一活性区13、第一局限层14以及第二局限层15可分别包含三五族半导体材料。上述三五族半导体材料可包含Al、Ga、As、P或In。在一实施例中,第一半导体结构11、第二半导体结构12、第一活性区13、第一局限层14以及第二局限层15不包含N。具体来说,上述三五族半导体材料可为二元化合物半导体(如GaAs或GaP)、三元化合物半导体(如InGaAs、AlGaAs、InGaP或AlInP)或四元化合物半导体(如AlGaInAs、AlGaInP、InGaAsP、InGaAsN或AlGaAsP)。于一实施例,第一活性区13实质上由三元化合物半导体(如InGaAs、AlGaAs、InGaP或AlInP)或四元化合物半导体(如AlGaInAs、AlGaInP、InGaAsP或AlGaAsP)所组成。The first semiconductor structure 11 , the second semiconductor structure 12 , the first active region 13 , the first confinement layer 14 and the second confinement layer 15 may respectively include III-V semiconductor materials. The above-mentioned Group III and V semiconductor materials may include Al, Ga, As, P or In. In one embodiment, the first semiconductor structure 11 , the second semiconductor structure 12 , the first active region 13 , the first confinement layer 14 and the second confinement layer 15 do not contain N. Specifically, the above-mentioned III-V semiconductor materials can be binary compound semiconductors (such as GaAs or GaP), ternary compound semiconductors (such as InGaAs, AlGaAs, InGaP or AlInP) or quaternary compound semiconductors (such as AlGaInAs, AlGaInP, InGaAsP, InGaAsN or AlGaAsP). In one embodiment, the first active region 13 is essentially composed of a ternary compound semiconductor (such as InGaAs, AlGaAs, InGaP or AlInP) or a quaternary compound semiconductor (such as AlGaInAs, AlGaInP, InGaAsP or AlGaAsP).
半导体元件100可包含双异质结构(double heterostructure,DH)、双侧双异质结构(double-side double heterostructure,DDH)或多重量子井(multiple quantumwells,MQW)结构。根据一实施例,当半导体元件100为发光元件时,第一活性区13可由第一半导体结构11朝第二半导体结构12的方向发出一光线。所述光线包含可见光或不可见光。半导体元件100所发出的光线波长决定于第一活性区13的材料。第一活性区13的材料可包含InGaAs、AlGaAsP或GaAsP、InGaAsP、AlGaAs、AlGaInAs、InGaP或AlGaInP。举例来说:第一活性区13可以发射出峰值波长为700至1700nm的红外光、峰值波长为610nm至700nm的红光、或是峰值波长为530nm至600nm的黄光。在本实施例中,第一活性区13发出峰值波长为730nm至1100nm的红外光。The semiconductor device 100 may include a double heterostructure (DH), a double-side double heterostructure (DDH) or a multiple quantum wells (MQW) structure. According to an embodiment, when the semiconductor device 100 is a light-emitting device, the first active region 13 can emit light from the first semiconductor structure 11 toward the second semiconductor structure 12 . The light includes visible light or invisible light. The wavelength of the light emitted by the semiconductor device 100 is determined by the material of the first active region 13 . The material of the first active region 13 may include InGaAs, AlGaAsP or GaAsP, InGaAsP, AlGaAs, AlGaInAs, InGaP or AlGaInP. For example, the first active region 13 can emit infrared light with a peak wavelength of 700 to 1700 nm, red light with a peak wavelength of 610 nm to 700 nm, or yellow light with a peak wavelength of 530 nm to 600 nm. In this embodiment, the first active area 13 emits infrared light with a peak wavelength of 730 nm to 1100 nm.
在本实施例中,外延结构的各层材料的晶系为立方晶系(cubic),且属闪锌矿结构(zincblende structure)。在一实施例中,外延结构的各层中不存在有极性(polarization),即各层的极化向量约为零。In this embodiment, the crystal system of each layer of material of the epitaxial structure is cubic and has a zincblende structure. In one embodiment, there is no polarization in each layer of the epitaxial structure, that is, the polarization vector of each layer is approximately zero.
续参照图1,第一活性区13位于第一局限层14及第二局限层15之间,且于本实施例中,第一活性区13与第一局限层14直接相接,且第一活性区13与第二局限层15直接相接。第一活性区13包含一第一阱层131、第一阻障层132、第二阱层133及第二阻障层134依序堆叠于第一局限层14上,且第一阱层131较第二阱层133靠近第一局限层14。第一活性区13另可包含一第三阱层135及第三阻障层136依序推叠于第二阻障层134上,且第二阱层133较第三阱层135靠近第一局限层14。第一阱层131、第二阱层133及第三阱层135包含铟(In),且第一阱层131中的铟组成比例小于第二阱层133中的铟组成比例,第二阱层133中的铟组成比例小于第三阱层135中的铟组成比例。当第一活性区13具有多个互相交叠的阱层与阻障层时,第一活性区13中的阱层的铟组成比例由第一局限层14往第二局限层15的方向递增。在一实施例中,第一阱层131与第二阱层133的铟组成比例差异为0.1%至0.3%,第二阱层133与第三阱层135的铟组成比例差异为0.1%至0.3%,且第一阱层131与第三阱层133的铟组成比例差异为0.2%至0.6%。Continuing to refer to FIG. 1 , the first active area 13 is located between the first localization layer 14 and the second localization layer 15 , and in this embodiment, the first active area 13 and the first localization layer 14 are directly connected, and the first active area 13 is directly connected to the first localization layer 14 . The active area 13 is directly connected to the second localization layer 15 . The first active region 13 includes a first well layer 131, a first barrier layer 132, a second well layer 133 and a second barrier layer 134 sequentially stacked on the first confinement layer 14, and the first well layer 131 is relatively The second well layer 133 is close to the first confinement layer 14 . The first active region 13 may further include a third well layer 135 and a third barrier layer 136 sequentially stacked on the second barrier layer 134, and the second well layer 133 is closer to the first region than the third well layer 135. Layer 14. The first well layer 131 , the second well layer 133 and the third well layer 135 include indium (In), and the composition ratio of indium in the first well layer 131 is smaller than the composition ratio of indium in the second well layer 133 . The composition ratio of indium in the third well layer 133 is smaller than that in the third well layer 135 . When the first active region 13 has a plurality of overlapping well layers and barrier layers, the indium composition ratio of the well layers in the first active region 13 increases from the first confinement layer 14 toward the second confinement layer 15 . In one embodiment, the difference in the indium composition ratio between the first well layer 131 and the second well layer 133 is 0.1% to 0.3%, and the difference in the indium composition ratio between the second well layer 133 and the third well layer 135 is 0.1% to 0.3 %, and the difference in indium composition ratio between the first well layer 131 and the third well layer 133 is 0.2% to 0.6%.
在其他实施例中,第一活性结构13具有上述铟组成比例由第一局限层14往第二局限层15的方向递增的多个阱层(131、133、135),并在第三阱层135上另设有多个阱层具有固定的铟组成比例。即,这些多个阱层由第一局限层14往第二局限层15的方向上都具有固定的铟组成比例,且此固定的铟组成比例大于第三阱层135的铟组成比例。在另一实施例中,此固定的铟组成比例小于第三阱层135的铟组成比例。In other embodiments, the first active structure 13 has a plurality of well layers (131, 133, 135) with the above-mentioned indium composition ratio increasing from the first confinement layer 14 to the second confinement layer 15, and in the third well layer There are also multiple well layers on 135 with a fixed indium composition ratio. That is, these multiple well layers have a fixed indium composition ratio in the direction from the first confinement layer 14 to the second confinement layer 15 , and this fixed indium composition ratio is greater than the indium composition ratio of the third well layer 135 . In another embodiment, the fixed indium composition ratio is smaller than the indium composition ratio of the third well layer 135 .
在一实施例中,第一局限层14、第二局限层15及阻障层(132、134、136)可具有相同或不同的能隙。第一局限层14、第二局限层15及阻障层(132、134、136)可具有相同或不同的材料。第一局限层14及第二局限层15的能隙大于阱层(131、133、135)的能隙,也可帮助载流子限制在第一活性区13中。In an embodiment, the first confinement layer 14, the second confinement layer 15 and the barrier layers (132, 134, 136) may have the same or different energy gaps. The first confinement layer 14, the second confinement layer 15 and the barrier layers (132, 134, 136) may have the same or different materials. The energy gaps of the first confinement layer 14 and the second confinement layer 15 are larger than the energy gaps of the well layers (131, 133, 135), which can also help confine carriers in the first active region 13.
在本实施例中,第一阱层131及第二阱层133的材料为InGaAs,第二阻障层132及第二阻障层134的材料为AlGaAs。在其他实施例中,第一阱层131及第二阱层133的材料为InGaAs,第二阻障层132及第二阻障层134的材料为AlGaAsP;在另一实施例中,第一阱层131及第二阱层133的材料为InGaAs,第二阻障层132及第二阻障层134的材料为GaAsP。本实施例半导体元件100的第一活性区13中,阱层(131、133、135)的厚度小于阻障层(132、134、136)的厚度。阱层及/或阻障层可包含或未包含掺质。In this embodiment, the material of the first well layer 131 and the second well layer 133 is InGaAs, and the material of the second barrier layer 132 and the second barrier layer 134 is AlGaAs. In other embodiments, the material of the first well layer 131 and the second well layer 133 is InGaAs, and the material of the second barrier layer 132 and the second barrier layer 134 is AlGaAsP; in another embodiment, the first well layer 131 and the second well layer 133 are made of InGaAs. The material of the layer 131 and the second well layer 133 is InGaAs, and the material of the second barrier layer 132 and the second barrier layer 134 is GaAsP. In the first active region 13 of the semiconductor device 100 in this embodiment, the thickness of the well layer (131, 133, 135) is smaller than the thickness of the barrier layer (132, 134, 136). The well layer and/or barrier layer may or may not include dopants.
在另一实施例中,第一阱层131的厚度小于第二阱层133的厚度,第二阱层133的厚度小于第三阱层135的厚度。当第一活性区13具有多个互相交叠的阱层与阻障层时,第一活性区13中的阱层的厚度由第一局限层14往第二局限层15的方向递增。通过上述第一阱层131及第二阱层133的铟组成比例及/或厚度的设计方式,可以使半导体元件100具有更佳的光电表现,例如:发光强度增加、顺向电压(Vf)降低等。In another embodiment, the thickness of the first well layer 131 is less than the thickness of the second well layer 133 , and the thickness of the second well layer 133 is less than the thickness of the third well layer 135 . When the first active region 13 has a plurality of overlapping well layers and barrier layers, the thickness of the well layers in the first active region 13 increases from the first confinement layer 14 to the second confinement layer 15 . By designing the indium composition ratio and/or thickness of the first well layer 131 and the second well layer 133, the semiconductor device 100 can have better optoelectronic performance, such as increased luminous intensity and reduced forward voltage (Vf). wait.
当半导体元件为发光元件且被驱动时,会出现原波峰(第一信号)往长波长位移的现象,或者在原波峰右方出现较长波的第二信号。通过上述的第一阱层131及第二阱层133的铟组成比例及/或厚度的设计方式,也有助于防止半导体元件产生不预期的光谱变化,并达到维持半导体元件于不同电流驱动下的发光波长稳定度的功效。When the semiconductor element is a light-emitting element and is driven, the original wave peak (first signal) will shift to a longer wavelength, or a second signal with a longer wavelength will appear to the right of the original wave peak. The above-mentioned design of the indium composition ratio and/or thickness of the first well layer 131 and the second well layer 133 also helps to prevent unexpected spectral changes of the semiconductor element and maintain the stability of the semiconductor element under different current drives. Efficacy of luminescence wavelength stability.
第一局限层14及第二局限层15是用以防止第一活性区13中的载流子溢流。在本实用新型的实施例中,第一局限层14具有一第一厚度T1,第二局限层15具有一第二厚度T2大于第一厚度T1,用以避免第二半导体结构12中的第二掺质进入第一活性区13中而影响半导体元件100的发光特性。在本实施例中,第一厚度T1例如为150nm至400nm,第二厚度T2例如为300nm至650nm。在一实施例中,T2/T1大于2。较厚的第二局限层15可有效的阻挡第二半导体结构12中第二掺质进入第一活性区13,由此降低第一活性区13中第二掺质的掺质浓度。换言之,第一活性区13可能具有第二掺质且掺质浓度为小于1×1016/cm3。通过上述第二厚度T2大于第一厚度T1的设计方式,可以使半导体元件100具有更佳的光电表现,例如:发光强度增加、顺向电压(Vf)降低等。此外,较薄的第一局限层14也有助于使载流子易于进入第一活性区13中,进而达到提升半导体元件100的光电表现的功效。本实施例中,第一局限层14直接相接于第一半导体结构11,第二局限层15直接相接于该第二半导体结构12。The first confinement layer 14 and the second confinement layer 15 are used to prevent carriers in the first active region 13 from overflowing. In the embodiment of the present invention, the first confinement layer 14 has a first thickness T1, and the second confinement layer 15 has a second thickness T2 greater than the first thickness T1, in order to avoid the second thickness T1 in the second semiconductor structure 12. The dopant enters the first active region 13 and affects the light-emitting characteristics of the semiconductor device 100 . In this embodiment, the first thickness T1 is, for example, 150 nm to 400 nm, and the second thickness T2 is, for example, 300 nm to 650 nm. In one embodiment, T2/T1 is greater than 2. The thicker second confinement layer 15 can effectively block the second dopant in the second semiconductor structure 12 from entering the first active region 13 , thereby reducing the dopant concentration of the second dopant in the first active region 13 . In other words, the first active region 13 may have a second dopant and the dopant concentration is less than 1×10 16 /cm 3 . Through the design method in which the second thickness T2 is greater than the first thickness T1, the semiconductor element 100 can have better optoelectronic performance, such as increased luminous intensity, reduced forward voltage (Vf), etc. In addition, the thinner first confinement layer 14 also helps to make it easier for carriers to enter the first active region 13 , thereby achieving the effect of improving the optoelectronic performance of the semiconductor device 100 . In this embodiment, the first confinement layer 14 is directly connected to the first semiconductor structure 11 , and the second confinement layer 15 is directly connected to the second semiconductor structure 12 .
在一实施例中,第一局限层14及第二局限层15可包含或未包含掺质。掺质可为故意掺杂或非故意掺杂。当第一局限层14及第二局限层15中的掺质为非故意掺杂时,此掺质系在外延过程中进入第一局限层14及第二局限层15,整体而言,这些非故意掺杂的掺质浓度会大幅(例如1至2个数量级)小于在第一半导体结构11及第二半导体结构12中的掺质浓度,在一实施例中,第一局限层14及第二局限层15中存在故意掺质或非故意掺杂的掺质浓度小于1×1017/cm3。第一厚度T1及第二厚度T2分别小于第一半导体结构11的厚度及第二半导体结构13的厚度,且本实施例的第一厚度T1及第二厚度T2都大于第一活性区13中的阻障层(132、134、136)及阱层(131、133、135)的厚度。In one embodiment, the first confinement layer 14 and the second confinement layer 15 may or may not include dopants. Dopants may be intentional or unintentional. When the dopant in the first localization layer 14 and the second localization layer 15 is unintentionally doped, the dopant enters the first localization layer 14 and the second localization layer 15 during the epitaxial growth process. Overall, these dopants are not doped intentionally. The intentionally doped dopant concentration may be significantly (eg, 1 to 2 orders of magnitude) smaller than the dopant concentrations in the first semiconductor structure 11 and the second semiconductor structure 12. In one embodiment, the first confinement layer 14 and the second The concentration of intentional doping or unintentional doping in the localization layer 15 is less than 1×10 17 /cm 3 . The first thickness T1 and the second thickness T2 are respectively smaller than the thickness of the first semiconductor structure 11 and the thickness of the second semiconductor structure 13 , and both the first thickness T1 and the second thickness T2 of this embodiment are larger than those in the first active region 13 Thicknesses of barrier layers (132, 134, 136) and well layers (131, 133, 135).
基底7包含导电或绝缘材料。导电材料例如砷化镓(GaAs)、磷化铟(InP)、碳化硅(SiC)、磷化镓(GaP)、氧化锌(ZnO)、氮化镓(GaN)、氮化铝(AlN)、锗(Ge)或硅(Si)。绝缘材料例如蓝宝石(Sapphire)。在其他实施例中,基底7为一成长基板,即于基底7上可通过例如有机金属化学气相沉积法(MOCVD)外延形成第一外延叠层1。在一实施例中,基底7为一接合基板而非成长基板,其可通过接合结构6而与第一外延叠层1相接合,如图1所示。The substrate 7 contains electrically conductive or insulating material. Conductive materials such as gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), gallium phosphide (GaP), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN), Germanium (Ge) or silicon (Si). Insulating material such as sapphire. In other embodiments, the substrate 7 is a growth substrate, that is, the first epitaxial stack 1 can be epitaxially formed on the substrate 7 by, for example, metal-organic chemical vapor deposition (MOCVD). In one embodiment, the substrate 7 is a bonding substrate rather than a growth substrate, which can be bonded to the first epitaxial stack 1 through the bonding structure 6 , as shown in FIG. 1 .
第一电极2以及第二电极3用于与外部电源电连接。第一电极2以及第二电极3的材料可相同或不同,例如分别包含金属氧化材料、金属或合金。金属氧化材料包含氧化铟锡(ITO)、氧化铟(InO)、氧化锡(SnO)、氧化镉锡(CTO)、氧化锑锡(ATO)、氧化铝锌(AZO)、氧化锌锡(ZTO)、氧化镓锌(GZO)、氧化铟钨(IWO)、氧化锌(ZnO)或氧化铟锌(IZO)等。金属可列举如锗(Ge)、铍(Be)、锌(Zn)、金(Au)、铂(Pt)、钛(Ti)、铝(Al)、镍(Ni)或铜(Cu)等。合金可包含选自由上述金属所组成的群组中的至少两者,例如锗金镍(GeAuNi)、铍金(BeAu)、锗金(GeAu)或锌金(ZnAu)等。The first electrode 2 and the second electrode 3 are used for electrical connection with an external power supply. The materials of the first electrode 2 and the second electrode 3 may be the same or different, for example, they may respectively include metal oxide materials, metals or alloys. Metal oxide materials include indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO) , Gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO) or indium zinc oxide (IZO), etc. Examples of the metal include germanium (Ge), beryllium (Be), zinc (Zn), gold (Au), platinum (Pt), titanium (Ti), aluminum (Al), nickel (Ni) or copper (Cu). The alloy may include at least two selected from the group consisting of the above metals, such as germanium gold nickel (GeAuNi), beryllium gold (BeAu), germanium gold (GeAu) or zinc gold (ZnAu).
绝缘部8包括折射系数(refractive index)小于2的绝缘材料,例如氮化硅(SiNx)、氧化铝(AlOx)、氧化硅(SiOx)、氟化镁(MgFx)或其组合。导电层4可包含金属氧化材料,例如:氧化铟锡(ITO)、氧化铟(InO)、氧化锡(SnO)、氧化镉锡(CTO)、氧化锑锡(ATO)、氧化铝锌(AZO)、氧化锌锡(ZTO)、氧化镓锌(GZO)、氧化铟钨(IWO)、氧化锌(ZnO)、氧化铟锌(IZO)或上述材料的组合。The insulating part 8 includes an insulating material with a refractive index less than 2, such as silicon nitride (SiN x ), aluminum oxide (AlO x ), silicon oxide (SiO x ), magnesium fluoride (MgF x ) or combinations thereof. The conductive layer 4 may include metal oxide materials, such as indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO) , zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), indium zinc oxide (IZO) or a combination of the above materials.
反射层5可反射第一活性区13所发出的光线以朝第一电极2方向射出半导体元件100外。反射层5可包含半导体材料、金属或合金。半导体材料可包含三五族半导体材料,例如二元、三元或四元三五族半导体材料。金属包含但不限于铜(Cu)、铝(Al)、锡(Sn)、金(Au)或银(Ag)等。合金可包含选自由上述金属所组成的群组中的至少两者。在一实施例中,反射层5可包含布拉格反射结构(Distributed Bragg Reflector structure,DBR)。布拉格反射结构可由不同折射率的两种以上的半导体材料交替堆叠而形成,例如由AlAs/GaAs、AlGaAs/GaAs或InGaP/GaAs所形成。The reflective layer 5 can reflect the light emitted from the first active area 13 so as to be emitted out of the semiconductor element 100 toward the first electrode 2 . Reflective layer 5 may comprise semiconductor material, metal or alloy. The semiconductor material may include a III-V semiconductor material, such as a binary, ternary or quaternary III-V semiconductor material. Metals include but are not limited to copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), etc. The alloy may include at least two selected from the group consisting of the above metals. In one embodiment, the reflective layer 5 may include a Distributed Bragg Reflector structure (DBR). The Bragg reflection structure can be formed by alternately stacking two or more semiconductor materials with different refractive indexes, such as AlAs/GaAs, AlGaAs/GaAs or InGaP/GaAs.
接合结构6连接基底7与反射层5。在一实施例中,接合结构6可为单层或多层(未绘示)。接合结构6的材料可包含透明导电材料、金属或合金。透明导电材料包含但不限于氧化铟锡(ITO)、氧化铟(InO)、氧化锡(SnO)、氧化镉锡(CTO)、氧化锑锡(ATO)、氧化铝锌(AZO)、氧化锌锡(ZTO)、氧化镓锌(GZO)、氧化锌(ZnO)、磷化镓(GaP)、氧化铟铈(ICO)、氧化铟钨(IWO)、氧化铟钛(ITiO)、氧化铟锌(IZO)、氧化铟镓(IGO)、氧化镓铝锌(GAZO)、石墨烯(graphene)或上述材料的组合。金属包含但不限于铜(Cu)、铝(Al)、锡(Sn)、金(Au)、银(Ag)、钛(Ti)、镍(Ni)、铂(Pt)或钨(W)等。合金可包含选自由上述金属所组成的群组中的至少两者。The bonding structure 6 connects the substrate 7 and the reflective layer 5 . In one embodiment, the bonding structure 6 can be a single layer or multiple layers (not shown). The material of the joint structure 6 may include transparent conductive materials, metals or alloys. Transparent conductive materials include but are not limited to indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), zinc oxide (ZnO), gallium phosphide (GaP), indium cerium oxide (ICO), indium tungsten oxide (IWO), indium titanium oxide (ITiO), indium zinc oxide (IZO) ), indium gallium oxide (IGO), gallium aluminum zinc oxide (GAZO), graphene or a combination of the above materials. Metals include but are not limited to copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), platinum (Pt) or tungsten (W), etc. . The alloy may include at least two selected from the group consisting of the above metals.
图2为本实用新型另一实施例的半导体元件的外延结构示意图。在本实施例中,外延结构除了上述的第一外延叠层1外,另包含一第二外延叠层9位于第一外延叠层1上,且第一外延叠层1与第二外延叠层9之间具有一中间层81。第二外延叠层9包含第三半导体结构91、一第四半导体结构92、一第二活性区93位于第三半导体结构91及第四半导体结构92之间、一第三局限层94位于第二活性区93及第三半导体结构91之间、及一第四局限层95位于第二活性区93及第四半导体结构92之间,且第三局限层94较第四局限层95靠近第一局限层14。第三半导体结构91与第四半导体结构92可具有相异的导电型态。例如,第三半导体结构91为n型,第四半导体结构92为p型;或者,第三半导体结构91为p型,第四半导体结构92为n型。由此,第三半导体结构91与第四半导体结构92可分别提供电子与空穴,第三半导体结构91具有一第三掺质,第四半导体结构92具有一第四掺质,使其具有不同的导电性。第三掺质可与第一掺质相同或不同,且第四掺质可与第二掺质相同或不同。第三掺质和第四掺质的材料可参考上述第一掺质及第二掺质的材料选择。FIG. 2 is a schematic diagram of the epitaxial structure of a semiconductor device according to another embodiment of the present invention. In this embodiment, in addition to the above-mentioned first epitaxial stack 1, the epitaxial structure also includes a second epitaxial stack 9 located on the first epitaxial stack 1, and the first epitaxial stack 1 and the second epitaxial stack 9 There is an intermediate layer 81 between 9. The second epitaxial stack 9 includes a third semiconductor structure 91, a fourth semiconductor structure 92, a second active region 93 located between the third semiconductor structure 91 and the fourth semiconductor structure 92, and a third confinement layer 94 located between the second semiconductor structure 91 and the fourth semiconductor structure 92. Between the active area 93 and the third semiconductor structure 91 , and a fourth localization layer 95 is located between the second active area 93 and the fourth semiconductor structure 92 , and the third localization layer 94 is closer to the first localization than the fourth localization layer 95 Layer 14. The third semiconductor structure 91 and the fourth semiconductor structure 92 may have different conductive types. For example, the third semiconductor structure 91 is n-type and the fourth semiconductor structure 92 is p-type; or the third semiconductor structure 91 is p-type and the fourth semiconductor structure 92 is n-type. Therefore, the third semiconductor structure 91 and the fourth semiconductor structure 92 can provide electrons and holes respectively. The third semiconductor structure 91 has a third dopant, and the fourth semiconductor structure 92 has a fourth dopant, so that they have different conductivity. The third dopant may be the same as or different from the first dopant, and the fourth dopant may be the same as or different from the second dopant. The materials of the third dopant and the fourth dopant can be selected with reference to the above-mentioned materials of the first dopant and the second dopant.
在本实施例中,第三半导体结构91具有与第二半导体结构12相反的导电型态,且与第一半导体结构11具有相同的导电型态。设置于第三半导体结构91及第二半导体结构12之间的中间层81是用以使载流子在第一半导体叠层1及第二半导体叠层9之间隧穿。详言之,中间层81包含一pn结,此pn结通过具有一第一导电性的一第一重掺杂层811(例如n型导电性半导体层)及一具有一第二导电性的第二重掺杂层812(例如p型导电性半导体层)所构成。第一重掺杂层811及第二重掺杂层812具有一掺杂浓度至少高于第二半导体结构12及第三半导体结构91的掺杂浓度一个数量级(order)以上,例如具有高于1×1018/cm3的掺杂浓度,以于操作时提供低阻值的电性结。In this embodiment, the third semiconductor structure 91 has an opposite conductivity type to the second semiconductor structure 12 and has the same conductivity type as the first semiconductor structure 11 . The intermediate layer 81 disposed between the third semiconductor structure 91 and the second semiconductor structure 12 is used to allow carriers to tunnel between the first semiconductor stack 1 and the second semiconductor stack 9 . Specifically, the intermediate layer 81 includes a pn junction, which is formed by a first heavily doped layer 811 having a first conductivity (for example, an n-type conductive semiconductor layer) and a third layer having a second conductivity. It is composed of a double doped layer 812 (for example, a p-type conductive semiconductor layer). The first heavily doped layer 811 and the second heavily doped layer 812 have a doping concentration that is at least one order of magnitude higher than the doping concentrations of the second semiconductor structure 12 and the third semiconductor structure 91 , for example, have a doping concentration higher than 1 The doping concentration is ×10 18 /cm 3 to provide a low resistance electrical junction during operation.
第二活性区93与第一活性区13具有相类似的结构、材料组成及发光波长,例如:第二活性区93与第一活性区13都发出波峰波长为730nm至1100nm的红外光。详言之,第二活性区93包含一第四阱层931、第四阻障层932、第五阱层933及第五阻障层934依序堆叠于第三局限层94上,且第四阱层931较第五阱层933靠近第三局限层94。第二活性区93另可包含一第六阱层935及第六阻障层936依序推叠于第五阻障层934上,第五阱层933较第六阱层935靠近第三局限层94。第四阱层931、第五阱层933及第六阱层935包含铟(In),且第四阱层931中的铟组成比例小于第五阱层933中的铟组成比例,第五阱层933中的铟组成比例小于第六阱层935中的铟组成比例。当第二活性区93具有多个互相交叠的阱层与阻障层时,第二活性区93中的阱层的铟组成比例由第三局限层94往第四局限层95的方向递增。在另一实施例中,第四阱层931的厚度小于第五阱层933的厚度,第五阱层933的厚度小于第六阱层935的厚度。当第二活性区93具有多个互相交叠的阱层与阻障层时,第二活性区93中的阱层的厚度由第三局限层94往第四局限层95的方向递增。如前述,通过阱层的铟组成比例及/或厚度的设计方式,可以使半导体元件具有更佳的光电表现。The second active region 93 and the first active region 13 have similar structures, material compositions, and emission wavelengths. For example, the second active region 93 and the first active region 13 both emit infrared light with a peak wavelength of 730 nm to 1100 nm. In detail, the second active region 93 includes a fourth well layer 931, a fourth barrier layer 932, a fifth well layer 933 and a fifth barrier layer 934 sequentially stacked on the third confinement layer 94, and the fourth The well layer 931 is closer to the third confinement layer 94 than the fifth well layer 933 . The second active region 93 may also include a sixth well layer 935 and a sixth barrier layer 936 sequentially stacked on the fifth barrier layer 934. The fifth well layer 933 is closer to the third localization layer than the sixth well layer 935. 94. The fourth well layer 931, the fifth well layer 933, and the sixth well layer 935 include indium (In), and the indium composition ratio in the fourth well layer 931 is smaller than the indium composition ratio in the fifth well layer 933. The fifth well layer The composition ratio of indium in 933 is smaller than that in the sixth well layer 935 . When the second active region 93 has a plurality of overlapping well layers and barrier layers, the indium composition ratio of the well layers in the second active region 93 increases from the third confinement layer 94 toward the fourth confinement layer 95 . In another embodiment, the thickness of the fourth well layer 931 is less than the thickness of the fifth well layer 933 , and the thickness of the fifth well layer 933 is less than the thickness of the sixth well layer 935 . When the second active region 93 has a plurality of overlapping well layers and barrier layers, the thickness of the well layers in the second active region 93 increases from the third confinement layer 94 toward the fourth confinement layer 95 . As mentioned above, by designing the indium composition ratio and/or thickness of the well layer, the semiconductor element can have better optoelectronic performance.
第三局限层94及第四局限层95是用以防止第二活性区93中的载流子溢流。第三局限层94具有一第三厚度T3,第四局限层95具有一第四厚度T4大于第三厚度T3,用以避免第四半导体结构92中的第四掺质进入第二活性区93中而影响半导体元件的发光特性。在本实施例中,第三厚度T3例如为150nm至400nm,第四厚度T4例如为300nm至650nm。在一实施例中T4/T3大于2,第三厚度T3大致等于第一厚度T1,且第四厚度T4大致等于第二厚度T2。在另一实施例中,T3>T1,T4>T2,且T2>T1,T4>T3;在又一实施例中,T3<T1,T4<T2,且T2>T1,T4>T3。The third confinement layer 94 and the fourth confinement layer 95 are used to prevent carriers in the second active region 93 from overflowing. The third localization layer 94 has a third thickness T3, and the fourth localization layer 95 has a fourth thickness T4 that is greater than the third thickness T3 to prevent the fourth dopant in the fourth semiconductor structure 92 from entering the second active region 93. And affect the luminescence characteristics of semiconductor components. In this embodiment, the third thickness T3 is, for example, 150 nm to 400 nm, and the fourth thickness T4 is, for example, 300 nm to 650 nm. In one embodiment, T4/T3 is greater than 2, the third thickness T3 is approximately equal to the first thickness T1, and the fourth thickness T4 is approximately equal to the second thickness T2. In another embodiment, T3>T1, T4>T2, and T2>T1, T4>T3; in yet another embodiment, T3<T1, T4<T2, and T2>T1, T4>T3.
上述局限层14、15、94、95的厚度设计(即:第二厚度T2大于第一厚度T1及/或第四厚度T4大于第三厚度T3)、第一活性区13及/或第二活性区93中的阱层的铟组成比例设计(即:阱层的铟组成比例由第一局限层14往第二局限层15及/或由第三局限层94往第四局限层95的方向递增)、第一活性区13及/或第二活性区93中的阱层的厚度设计(即:阱层的厚度由第一局限层14往第二局限层15的方向及/或由第三局限层94往第四局限层95的方向递增),若再搭配增加第一半导体结构11及/或第二半导体结构12的掺质浓度为8×1017~5×1018/cm3、及/或第一半导体结构11及/或第二半导体结构12的铝含量为25%~50%等外延结构特征,将有助于增加载流子浓度及/或加强电流分散效果,进而达到提升半导体元件100的发光强度的功效。上述外延结构特征特别适合用于高电流密度操作的半导体元件,例如电流密度为0.5A/mm2至2A/mm2的半导体元件。电流密度为操作时施加于半导体元件100的电流值与基底7表面积的商。例如:操作时施加于半导体元件的电流值为100mA,半导体元件的基底面积为0.125mm2,则电流密度为0.8A/mm2。上述铝含量指铝的原子百分比,例如当第一半导体结构11及/或第二半导体结构12的材料为AlGaAs且铝含量为25%时,其材料组成为Al0.25Ga0.75As。The thickness design of the above-mentioned localization layers 14, 15, 94, 95 (that is, the second thickness T2 is greater than the first thickness T1 and/or the fourth thickness T4 is greater than the third thickness T3), the first active region 13 and/or the second active area The indium composition ratio of the well layer in the region 93 is designed (that is, the indium composition ratio of the well layer increases from the first confinement layer 14 to the second confinement layer 15 and/or from the third confinement layer 94 to the fourth confinement layer 95 ), the thickness design of the well layer in the first active region 13 and/or the second active region 93 (that is, the thickness of the well layer is from the direction of the first confinement layer 14 to the second confinement layer 15 and/or from the third confinement layer layer 94 toward the fourth localization layer 95), if the dopant concentration of the first semiconductor structure 11 and/or the second semiconductor structure 12 is further increased to 8×10 17 to 5×10 18 /cm 3 , and/ Or epitaxial structural features such as the aluminum content of the first semiconductor structure 11 and/or the second semiconductor structure 12 being 25% to 50% will help increase the carrier concentration and/or enhance the current dispersion effect, thereby improving the semiconductor device. Efficacy of 100 luminous intensity. The above epitaxial structural features are particularly suitable for semiconductor devices operating at high current densities, such as semiconductor devices with current densities of 0.5 A/mm 2 to 2 A/mm 2 . The current density is the quotient of the current value applied to the semiconductor element 100 during operation and the surface area of the substrate 7 . For example: the current value applied to the semiconductor element during operation is 100mA, and the base area of the semiconductor element is 0.125mm 2 , then the current density is 0.8A/mm 2 . The aluminum content refers to the atomic percentage of aluminum. For example, when the material of the first semiconductor structure 11 and/or the second semiconductor structure 12 is AlGaAs and the aluminum content is 25%, the material composition is Al 0.25 Ga 0.75 As.
举例来说,在一实施例中,半导体元件为发光元件且具有第一厚度T1小于第二厚度T2的设计,若再分别搭配具有第一半导体结构11的掺质浓度为8×1017~5×1018/cm3的外延结构特征,相较于不具有上述外延结构特征的发光元件,当操作于电流密度为1.7A/mm2时,本实施例发光元件的发光强度可增加2.8%。在另一实施例中,半导体元件为发光元件且具有第一厚度T1小于第二厚度T2的设计,若再分别搭配具有第一半导体结构11的铝含量为25%~50%的外延结构特征,相较于不具有上述外延结构特征的发光元件,当操作于电流密度为1.7A/mm2时,本实施例发光元件的发光强度可增加6.1%。For example, in one embodiment, the semiconductor element is a light-emitting element and has a design in which the first thickness T1 is smaller than the second thickness T2. If the dopant concentration of the first semiconductor structure 11 is 8×10 17 to 5 The epitaxial structural features of In another embodiment, the semiconductor element is a light-emitting element and has a design in which the first thickness T1 is smaller than the second thickness T2. If the first semiconductor structure 11 is combined with an epitaxial structural feature having an aluminum content of 25% to 50%, Compared with a light-emitting element without the above-mentioned epitaxial structural features, when operating at a current density of 1.7 A/mm 2 , the luminous intensity of the light-emitting element of this embodiment can be increased by 6.1%.
图3为本实用新型一实施例的半导体组件300的剖面结构示意图。请参照图3,半导体组件300包含半导体元件100、封装基板31、载体33、接合线35、接触结构36以及封装层38。封装基板31可包含陶瓷或玻璃材料。封装基板31中具有多个通孔32。通孔32中可填充有导电性材料如金属等而有助于导电或/且散热。载体33位于封装基板31一侧的表面上,且也包含导电性材料,如金属。接触结构36位于封装基板31另一侧的表面上。在本实施例中,接触结构36包含第一接触垫36a以及第二接触垫36b,且第一接触垫36a以及第二接触垫36b可通过通孔32而与载体33电连接。在一实施例中,接触结构36可进一步包含散热垫(thermalpad)(未绘示),例如位于第一接触垫36a与第二接触垫36b之间。FIG. 3 is a schematic cross-sectional structural diagram of a semiconductor component 300 according to an embodiment of the present invention. Referring to FIG. 3 , the semiconductor component 300 includes a semiconductor element 100 , a packaging substrate 31 , a carrier 33 , bonding wires 35 , contact structures 36 and packaging layers 38 . The packaging substrate 31 may include ceramic or glass materials. The package substrate 31 has a plurality of through holes 32 therein. The through hole 32 may be filled with conductive material such as metal to facilitate conduction and/or heat dissipation. The carrier 33 is located on the surface of one side of the packaging substrate 31 and also includes conductive material, such as metal. Contact structure 36 is located on the surface of the other side of package substrate 31 . In this embodiment, the contact structure 36 includes a first contact pad 36 a and a second contact pad 36 b, and the first contact pad 36 a and the second contact pad 36 b can be electrically connected to the carrier 33 through the through hole 32 . In one embodiment, the contact structure 36 may further include a thermal pad (not shown), for example, located between the first contact pad 36a and the second contact pad 36b.
半导体元件100位于载体33上。在本实施例中,载体33包含第一部分33a及第二部分33b,半导体元件100通过接合线35而与载体33的第二部分33b电连接。接合线35的材质可包含金属,例如金、银、铜、铝或至少包含上述任一元素的合金。封装层38覆盖于半导体元件100上,具有保护半导体元件100的效果。具体来说,封装层38可包含树脂材料如环氧树脂(epoxy)、硅氧烷树脂(silicone)等。封装层38选择性地可包含多个波长转换粒子(图未示)以转换半导体元件100所发出的第一光为一第二光。第二光的波长大于第一光的波长。Semiconductor component 100 is located on carrier 33 . In this embodiment, the carrier 33 includes a first part 33 a and a second part 33 b, and the semiconductor element 100 is electrically connected to the second part 33 b of the carrier 33 through the bonding wire 35 . The material of the bonding wire 35 may include metal, such as gold, silver, copper, aluminum or an alloy containing at least any of the above elements. The encapsulation layer 38 covers the semiconductor element 100 and has the effect of protecting the semiconductor element 100 . Specifically, the encapsulation layer 38 may include resin materials such as epoxy, silicone, etc. The encapsulation layer 38 may optionally include a plurality of wavelength conversion particles (not shown) to convert the first light emitted by the semiconductor device 100 into a second light. The wavelength of the second light is greater than the wavelength of the first light.
图4为本实用新型一实施例的感测模块400的部分剖面结构示意图,感测模块400包含一承载体420、第一半导体元件411及第二半导体元件431。第一半导体元件411及/或第二半导体元件431可以为上述的半导体元件。承载体420包含第一挡墙421、第二挡墙422、第三挡墙423、载板424、一第一空间425及第二空间426,第一半导体元件411位于第一挡墙421与第二挡墙422之间的空间425中,第二半导体元件431位于第二挡墙422与第三挡墙423之间的空间426中。第一半导体元件411及/或第二半导体元件431可以为如图1的垂直式芯片,或是为具有图1或图2的外延结构的倒装芯片或正装芯片。第一半导体元件411及第二半导体元件431位于载板424上,并与载板424上的电路连接结构(图未示)形成电连接。在本实施中,第一半导体元件411为一发光元件,第二半导体元件431为一光接收元件,且感测模块400可置于穿戴装置(例如;手表、耳机)中,第一半导体元件411发出的光线穿过皮肤并照射身体细胞以及血液,再通过第二半导体元件431吸收从身体细胞以及血液散射/反射回来的光,根据此反射、散射光的变化,用以侦测人体的生理信号,例如:心率、血糖、血压、血氧浓度等。4 is a partial cross-sectional structural diagram of a sensing module 400 according to an embodiment of the present invention. The sensing module 400 includes a carrier 420, a first semiconductor element 411 and a second semiconductor element 431. The first semiconductor element 411 and/or the second semiconductor element 431 may be the above-mentioned semiconductor elements. The carrier 420 includes a first retaining wall 421, a second retaining wall 422, a third retaining wall 423, a carrier plate 424, a first space 425 and a second space 426. The first semiconductor element 411 is located between the first retaining wall 421 and the second retaining wall 423. In the space 425 between the two blocking walls 422 , the second semiconductor element 431 is located in the space 426 between the second blocking wall 422 and the third blocking wall 423 . The first semiconductor element 411 and/or the second semiconductor element 431 may be a vertical chip as shown in FIG. 1 , or a flip chip or a full chip chip having the epitaxial structure of FIG. 1 or FIG. 2 . The first semiconductor element 411 and the second semiconductor element 431 are located on the carrier board 424 and are electrically connected to the circuit connection structure (not shown) on the carrier board 424 . In this implementation, the first semiconductor element 411 is a light-emitting element, the second semiconductor element 431 is a light-receiving element, and the sensing module 400 can be placed in a wearable device (such as a watch, earphones). The first semiconductor element 411 The emitted light passes through the skin and irradiates the body cells and blood, and then absorbs the light scattered/reflected back from the body cells and blood through the second semiconductor element 431. Based on the changes in the reflected and scattered light, it is used to detect physiological signals of the human body. , such as: heart rate, blood sugar, blood pressure, blood oxygen concentration, etc.
具体来说,本实用新型的外延结构、半导体元件及半导体组件可应用于照明、医疗、显示、通讯、感测、电源系统等领域的产品,例如灯具、监视器、手机、平板计算机、车用仪表板、电视、计算机、穿戴装置(如手表、手环、项链等)、交通号志、户外显示器、医疗器材等。Specifically, the epitaxial structures, semiconductor elements and semiconductor components of the present invention can be applied to products in the fields of lighting, medical care, display, communication, sensing, power supply systems, etc., such as lamps, monitors, mobile phones, tablet computers, and automotive products. Dashboards, TVs, computers, wearable devices (such as watches, bracelets, necklaces, etc.), traffic signals, outdoor displays, medical equipment, etc.
虽然结合以上实施例已公开了本实用新型,然而其并非用以限定本实用新型,所属技术领域中具有通常知识者应理解,在不脱离本实用新型的精神和范围内可作些许的修饰或变更,故本实用新型的保护范围应当以附上的权利要求所界定的为准。此外,上述实施例内容在适当的情况下可互相组合或替换,而非仅限于所描述的特定实施例。举例而言,在一实施例中所揭露特定构件的相关参数或特定构件与其他构件的连接关系也可应用于其他实施例中,且均落于本实用新型的权利保护范围。Although the present utility model has been disclosed in conjunction with the above embodiments, they are not intended to limit the present utility model. Those of ordinary skill in the art will understand that slight modifications or modifications may be made without departing from the spirit and scope of the present utility model. Therefore, the protection scope of the present utility model shall be defined by the appended claims. In addition, the above-described embodiments may be combined or replaced with each other under appropriate circumstances and are not limited to the specific embodiments described. For example, the relevant parameters of a specific component or the connection relationship between a specific component and other components disclosed in one embodiment can also be applied to other embodiments, and all fall within the scope of rights protection of the present invention.
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