TWI828963B - Apparatus and computer program product for controlling different types of storage units - Google Patents

Abstract

The invention introduces an apparatus and a computer program product for controlling different types of storage units. The apparatus includes an interface and a processing unit. The interface includes channels and each channel is connected to a first type and a second type of storage units. The processing unit coupled to the interface is arranged operably to configure the interface in a first operation mode corresponding to the first type of storage units; drive the interface to issue a first signal to enable the first types of storage units connected to different channels; drive the interface to read data from the first type of storage units; and before accessing to data of the second type of storage units, reconfigure the interface in a second operation mode corresponding to the second type of storage units. The installation of different types of storage units provides a wide range of application potentials to a host.

Description

Devices and computer program products used to control different types of storage units

The present invention relates to storage devices, and in particular, to a device and computer program product for controlling different types of storage units.

Flash memory devices are generally divided into NOR flash memory devices and NAND flash memory devices. The NOR flash memory device is a random access device. The host device (Host) can provide any address for accessing the NOR flash memory device on the address pin and obtain the data pin of the NOR flash memory device in real time. Get the data stored at this address. In contrast, NAND flash memory devices do not have random access, but sequential access. NAND flash memory devices cannot access any random address like NOR flash memory devices. Instead, the master device needs to write a sequence of Bytes values to the NAND flash memory device to define the request. The type of command (such as read, write, erase, etc.), and the address used for this command. An address can point to a page (the smallest unit of a write operation in a flash memory device) or a block (the smallest unit of an erase operation in a flash memory device).

The storage space of a mass storage device (Mass Storage Device) can be implemented using NAND flash memory devices, which contain a large number of Triple Level Cells (TLCs) to store large amounts of data. However, writing to a triple-layer unit takes longer. In addition, three-tier units also require time-consuming wear leveling operations to extend the service life of large-scale storage devices. When the storage space of a mass storage device is only implemented in three-tier units, the application flexibility for the main device is insufficient. For example, it is less suitable for cold data that requires quick access. Therefore, the present invention proposes a method and device for controlling different types of storage units to overcome the above limitations.

In view of this, how to alleviate or eliminate the deficiencies in the above-mentioned related fields is a problem that needs to be solved.

The invention proposes a device for controlling different types of storage units. The device includes: an interface; and a processing unit. The interface includes a plurality of channels, and each channel is connected to a storage unit of the first type and a second type. The processing unit coupling interface is used to configure the interface in a first working mode; the driver interface sends a first signal to enable the first type of storage unit between different channels; the driver interface accesses data of the first type of storage unit; and Before accessing data in the storage unit of the second type, the interface is reconfigured into the second working mode.

The present invention also provides a computer program product, which includes program code and is used to control different types of storage units when the program code is executed by a processing unit. The program code is used to: configure the interface in the first working mode, the interface includes multiple channels, each channel is connected to the storage unit of the first type and the second type; the driver interface sends a first signal to enable the first connection of the multiple channels. a storage unit of the first type; driving the interface to access data of the storage unit of the first type; and reconfiguring the interface to the second working mode before accessing data of the storage unit of the second type.

The first operating mode corresponds to a first type of storage unit, and the second operating mode corresponds to a second type of storage unit.

The invention also provides a device for controlling different types of storage units. The device includes: an interface; and a processing unit. The interface connects multiple storage units, wherein the storage units include non-volatile hybrid memory and flash memory. The processing unit coupling interface is used to initialize the hybrid memory during the system startup phase; read parameters for configuring the flash memory and the system code from the hybrid memory; initialize the flash memory according to the parameters; and Execute the program code in the system to enter the normal working mode and wait for commands from the main device.

The present invention also provides a computer program product, which includes program code and is used to control different types of storage units when the program code is executed by a processing unit. The program code is used to: initialize the non-volatile hybrid memory during the system boot phase; read the parameters of the configured flash memory from the hybrid memory, as well as the program code in the system; initialize the flash memory according to the parameters; and Execute the program code in the system to enter the normal working mode and wait for commands from the main device.

One of the advantages of the above embodiments is that the arrangement of multiple types of storage units can provide the host device with more diverse application potentials.

Other advantages of the present invention will be explained in more detail in conjunction with the following description and drawings.

The following description is a preferred implementation manner for completing the invention, and its purpose is to describe the basic spirit of the invention, but is not intended to limit the invention. For the actual invention, reference must be made to the following claims.

It must be understood that the words "including" and "include" used in this specification are used to indicate the existence of specific technical features, numerical values, method steps, work processes, components and/or components, but do not exclude the possibility of adding further technical features, values, method steps, processes, components, components, or any combination of the above.

Words such as "first", "second", and "third" used in the claims are used to modify the elements in the claims, and are not used to indicate a priority, precedence relationship, or a single element. Prior to another element, or the chronological order in which method steps are performed, it is only used to distinguish elements with the same name.

It must be understood that when an element is described as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, and intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements could be interpreted in a similar fashion, such as "between" versus "directly between," or "adjacent" versus "directly adjacent," etc.

Refer to Figure 1. The general system architecture 100 includes a main device 110, a memory controller 130, a dynamic random access memory 151 (Dynamic Random Access Memory DRAM), a dynamic random access memory 153 (DRAM-like), a flash memory ( Flash) 171 and flash-like memory (Flash-like) 173. This system architecture 100 can be implemented in electronic products such as personal computers, laptop computers (Laptop PC), tablet computers, mobile phones, digital cameras, and digital video cameras. The memory controller 130 is a special application integrated circuit (Application-Specific Integrated Circuit ASIC) used to control dynamic random access memory 151, quasi-dynamic random access memory 153, flash memory 171 or The data access of the flash memory 173 may include the processing unit 131, the read-only memory 132, the static random access memory (Static Random Access Memory SRAM), the main device interface 135, the dual-mode memory interface 137 and the dual-mode memory interface 137. Mode flash interface 139. The memory controller 130, dynamic random access memory 151, dynamic random access memory-like 153, flash memory 171 or flash memory-like 173 can be provided on the data storage device, and the data storage device can be connected to the main device 110 communicates and executes the host command (Host Command) from the main device 110.

In some cost-saving embodiments, the data storage device can be simplified to only any two of the dynamic random access memory 151, the dynamic random access memory 153, the flash memory 171 and the flash memory 173. Or any two or more. In other cost-saving embodiments, the system architecture 100 can be simplified to not include the dynamic random access memory 151 and the quasi-dynamic random access memory 153, so that the memory controller 130 can be simplified to not include the dual-mode memory. interface 137, or disable the operation of the dual-mode memory interface 137.

The flash memory 171 provides a large amount of storage space, usually hundreds of Gigabytes or even Terabytes, which can be used to store a large amount of user data, such as high-resolution pictures, videos, etc. The memory cells in the flash memory 171 may be triple level cells (Triple Level Cells, TLCs) or quad-level cells (Quad-Level Cells QLCs). The dynamic random access memory 151 can be used to cache user data from the main device 110 or from the flash memory 171, and can also be used to cache part or all of the Logical-Physical Address Mapping Table (L2P Table). . The dynamic random access memory 151 can also store firmware and variables required for the operation of the data storage device.

The memory controller 130 includes a processing unit 131 that communicates with the host device 110 through a host device interface 135 . The main device interface 135 can be universal flash storage (Universal Flash Storage UFS), fast non-volatile memory (Non-Volatile Memory Express NVMe), universal serial bus (Universal Serial Bus, USB), advanced technology attachment (advanced technology attachment (ATA), serial advanced technology attachment (SATA), peripheral component interconnect express (PCI-E) or other interfaces. Either the main device 110 or the processing unit 131 may be implemented in a variety of ways, such as using general-purpose hardware (eg, a single processor, a multi-processor with parallel processing capabilities, or other processors with computing capabilities), and When executing firmware or software instructions (Instructions), the functions described later are provided. A multiprocessor is a single computing element that can be equipped with two or more independent processors (also called multi-cores) to read and execute program instructions.

The processing unit 131 can communicate with the flash memory 171 through a dual-mode flash memory interface 139, for example, Open NAND Flash (Open NAND Flash Interface ONFI), double data rate switch (DDR Toggle) or other interfaces can be used. The processing unit 131 can communicate with the dynamic random access memory 151 through the dual-mode memory interface 137. For example, the third generation double data rate (Double Data Rate Third Generation, DDR3) or the fourth generation double data rate (DDR3) can be used. Double Data Rate Fourth Generation (DDR4) or other interface.

The quasi-dynamic random access memory 153 is also called a hybrid memory and can be implemented by a phase-change memory (Phase-Change Memory) or a magnetoresistive memory. The quasi-Dynamic Random Access Memory 153 has faster data access capabilities, so it can be used as a data buffer (Buffer) to temporarily store data; what's more, the quasi-Dynamic Random Access Memory 153 can provide long-term storage Data storage capability, the DRAM-like 153 can also be used as a data storage medium. The similar dynamic random access memory 153 adopts an operation interface similar to the dynamic random access memory 151. The access speed of the similar dynamic random access memory 153 is only 1/10 of the dynamic random access memory 151, but , the data storage capacity may be, for example, 10 times that of the dynamic random access memory 151 .

Flash-like memory 173 can also be called a hybrid memory. It is essentially a flash memory. The memory unit is a single-level cell (SLC). However, the data length of a page (Page) is only 512B, for example. It provides long-term data storage capability, so it can be used as a data storage medium. The flash memory 173 uses an operating interface similar to the flash memory 171 . The access speed of the flash memory 173 is, for example, 10 times that of the flash memory 171 . However, the data storage capacity is only that of the flash memory 171 . 1/10 of memory 171.

The processing unit 131 can communicate with the DRAM-like 153 and the Flash-like memory 173 through a Memory-like Interface I/F and a Flash-like I/F respectively. . Dynamic random access memory 153 and flash memory 173 can also be called hybrid memory because they have non-volatile data storage characteristics and their access speed is between flash memory 171 and dynamic random access memory 151.

In addition, compared to flash memory 171, hybrid memory has better endurance (Endurance) and better data retention capabilities. Therefore, data unlike flash memory 171 usually requires higher error correction capabilities. Error-Correcting Code (ECC), such as Low-Density Parity Check Code (LDPC), protection. Data stored in hybrid memory can be protected using ECC with lower error correction capabilities, such as BCH code (Bose–Chaudhuri–Hocquenghem Code). Taking each 1K byte of user data as an example, the BCH code can provide the ability to correct up to 72 error bits, while the LDPC can provide the ability to correct up to 128 error bits.

In addition, in terms of data access latency (Latency), dynamic random access memory 151 is better than hybrid memory, and hybrid memory is better than flash memory 171. Therefore, based on the differences in the above characteristics, the hybrid memory can provide more diverse applications, such as storing information required during booting, serving as a Level-4 Cache for the main device 110, etc.

Since the flash-like memory 173 uses flash memory as the data storage medium, the flash-like interface is similar to the flash interface. Some of the pin definitions of the flash-like interface and the flash interface are the same or similar. capacity, but some pins are defined differently. Therefore, the dual-mode flash interface 139 is based on the flash interface and expanded. Similarly, the memory-like interface is similar to the memory interface. Some pins of the memory-like interface and the memory interface are defined to be the same or compatible, but some pins are defined to be different. Therefore, the dual-mode memory interface 137 It is based on the memory interface and expanded. In other words, the dual-mode flash memory interface 139 and the dual-mode memory interface 137 are integrated interfaces that can access different types of flash memory and random access memory respectively. In addition, the dual-mode flash memory interface 139 preferably uses page as the minimum unit for data writing and block as the minimum unit for data erasure. The dual-mode memory interface 137 uses bit as the minimum unit for data writing.

FIG. 2 shows an embodiment of the connection between the dual-mode flash memory interface 139 and the flash memory 171 and the flash-like memory 173 . The dual-mode flash memory interface 139 may include four input/output channels (I/O channels, hereinafter referred to as channels CH) CH#0 to CH#3. Each channel can be connected to the same or different types of storage modules, such as one flash memory module and two flash memory modules, and is identified by a logical unit number (Logical Unit Number LUN). For example, channel CH#0 connects the flash memory module 173#0 and the flash memory modules 171#0 and 171#4. In other words, different types of flash memory modules can share a channel. In this connection mode, the storage modules between multi-channel CHs can be accessed in multi-channel mode, which can increase the performance of data access. The processing unit 131 can access the flash memory modules 173#0~3 of channels CH#0~3 in multi-channel mode by enabling the chip enable (CE) signal CE#0 and process Unit 131 can also access the flash memory modules 171#0~3 of channels CH#0~3 in multi-channel mode by enabling the chip enable signal CE#1.

FIG. 3 shows another embodiment of the connection between the dual-mode flash memory interface 139 and the flash memory 171 and the flash-like memory 173 . Each channel only connects to storage modules of the same type. Each of channels CH#0 and CH#1 only connects to flash memory modules, while each of channels CH#2 and CH#3 only connects to Flash memory module. In this connection mode, the storage modules between multi-channel CHs can be accessed in multi-channel mode, which can increase the performance of data access. The processing unit 131 can access the flash memory modules 173 #0 and #3 of channels CH#0~1 in multi-channel mode by enabling CE#0. The processing unit 131 can also enable CE #0 and accesses the flash memory modules 171 #0 and #3 of channels CH#2~3 in multi-channel mode.

The dual-mode flash memory interface 139 is configured with 30 pins. Table 1 shows the pin functions (Pin Function) of the dual-mode flash interface 139: Table 1 Pin number ONFI (Async) Toggle ONFI(Sync) Flash-like I/F 0~7 Data[0:7] Data[0:7] Data[0:7] Data[0:7] 8 CE# CE# CE# CS 9 ALE ALE ALE Select_In 10 CLE CLE CLE CA 11 RE# RE# R/W x 12 RE_c RE_c RE_c x 13 WE# WE# Clock Clock 14 R/B# R/B# R/B# x 15 WP# WP# WP# x 16 DQS_c DQS_c DQS_c x 17 DQS# DQS# DQS# DQS# 18 ZQ ZQ ZQ ZQ 19~26 x x Data[8:15] x 27 x x x Clock_c 28 x x x CKE 29 x x x ODT

As shown in Table 1, the dual-mode flash memory interface 139 can be configured as a flash memory interface, including: open NAND flash synchronous mode (ONFI Sync), open NAND flash asynchronous mode (ONFI Async) or double data rate switch ( DDR Toggle) interface is used to allow the processing unit 131 and the flash memory module to communicate with each other. In addition, the dual-mode flash memory interface 139 can be configured as a flash-like I/F to allow the processing unit 131 and the flash-like memory module to communicate with each other. The letter "x" represents a floating, reserved or manufacturer-proprietary pin, the letter "#" represents a negative edge driver, and the letter "c" represents complement.

The dual-mode flash memory interface 139 may include a plurality of registers corresponding to the pins of the storage module, so that the processing unit 131 can set parameters output to specific pins of the storage module, such as preset voltage levels, driving methods (positive edge drive Assertion or negative edge driving De-assertion, or No-function), whether it is oscillating (swinging), clock frequency, etc. For example, when the dual-mode flash memory interface 139 is configured as an ONFI Sync, ONFI Async or DDR Toggle interface, the processing unit 131 can configure the corresponding register to set the default voltage level output to pin #8 to a high voltage, driving mode Set it to negative edge drive, and set the parameter of whether to oscillate to No. When the dual-mode flash memory interface 139 is configured as a flash-like interface, the processing unit 131 can configure the corresponding register to set the preset voltage level output to pin #8 to low voltage, set the driving mode to positive edge driving, and Set the parameter of whether to oscillate to No. For another example, when the dual-mode flash memory interface 139 is configured as an ONFI Sync interface, the processing unit 131 can configure the corresponding register to set the oscillation parameter output to pin #13 to yes, and set the clock frequency to the flash memory Frequencies acceptable to the module. When the dual-mode flash memory interface 139 is configured as a flash-like interface, the processing unit 131 can configure the corresponding register to set the oscillation parameter output to pin #13 to yes, and set the clock frequency to a flash-like memory mode. acceptable frequency for the group.

Each storage module has an independent CE or Chip Select (CS) signal. The processing unit 131 can access data in the storage modules on different channels CH#0 to CH#3 in parallel through the dual-mode flash memory interface 139. Specifically, the processing unit 131 can first send one of the chip enable signals CE#0 to CE#3 to enable the designated storage module in each channel, and then through the input and output channels CH#0 to CH In #3, the shared data line Data[0:7] or the shared data lines Data[0:7] and Data[8:15] are used to access data in the enabled storage module in parallel. For example, the processing unit 131 transmits commands, logical block addresses to be read, user data to be written, etc. to the enabled storage module through the shared data line, or receives user data from the enabled storage module. , reply to messages, etc. In addition, each channel can also pass Address Latch Enable ALE, Command Latch Enable CLE, Read Enable RE, Complementary Read enable (Complement RE, RE_c), write enable (Write Enable WE), read/write (R/W), ready/busy (Ready/Busy, R/B), write protection (Write Protect, WP), command address (Command Address, CA), clock (Clock), complementary clock (Complement Clock, Clock_c), clock enable (Clock Enable, CKE), DQS, ZQ, ODT and other control signals.

In addition, the number of pins of the dual-mode flash memory interface 139 can be reduced by redefining the pin function. For example, move the ODT function of the flash-like interface to pin #15, so that pin #15 acts as WP in the flash interface and acts as ODT in the flash-like interface. In this way, pin #139 of the dual-mode flash interface 29 is not needed.

After the connection configuration is set, the manufacturer of the memory controller 130 can directly write the connection configuration into the ROM. In this way, the processing unit 131 can control the operation of the dual-mode flash memory interface 139 according to the ROM settings. Alternatively, during the initialization stage of the memory controller 130, the processing unit 131 takes turns outputting operation instructions to the storage module according to the flash interface or flash-like interface, for example, outputting a data read instruction of the flash interface. If the storage module If the data can be returned correctly, the processing unit 131 determines that the storage module is a flash memory module; otherwise, the storage module is a flash memory module. Alternatively, the processing unit 131 uses a default interface to read the default storage module. For example, the storage module in channel CH#0 controlled by CE#0 must be a flash memory module, and the connection configuration can be stored in this flash memory module. When the memory controller 130 performs initialization, the processing unit 131 directly reads the flash memory modules of CE#0 and CH#0 through the flash interface to obtain the connection configuration.

Based on the connections shown in FIG. 2 , the processing unit 131 can drive different types of flash memory modules using different communication protocols (Protocol), or drive different types of flash memory modules in different working modes. Before enabling another flash memory module, the processing unit 131 may reconfigure (Reconfigure) the dual-mode flash memory interface 139 . For example, the dual-mode flash memory interface 139 can first be configured by the processing unit 131 to access the working mode of the flash memory module 173 when it is powered on. After the configuration is successful, the processing unit 131 drives the dual-mode flash memory interface 139 to send the enable signal CE#0 to enable the flash memory modules 173#0 to 173#3, and then accesses the programs required for booting. Instructions, comparison tables, information, etc. After successful booting, the processing unit 131 can reconfigure the dual-mode flash memory interface 139 to the working mode of accessing the flash memory module 171 . After the configuration is successful, the processing unit 131 drives the dual-mode flash memory interface 139 to send the enable signal CE#1 or CE#2 to enable the flash memory modules 171#0 to 171#3 or the flash memory module 171#. 4 to 171#7, and then access user data and perform various background operations to enhance the storage capacity of the flash memory 171, such as garbage collection (Garbage Collection, GC), wear leveling (Wear Leveling, WL) operations, etc. During accessing user data, if it is necessary to access program instructions, lookup tables or data in the flash memory module 173, the processing unit 131 issues an enable signal CE#0 to enable the flash memory module. Before assembly 173 , the dual-mode flash memory interface 139 can be reconfigured to the working mode of the access-type flash memory module 173 .

In some embodiments, when the processing unit 131 is a multi-processor with parallel processing capabilities, each processor core can control a specific channel to access data in part of the storage module. For example, one processor core is responsible for controlling channels CH#0 and CH#1, while another processor core is responsible for controlling channels CH#2 and CH#3. In other embodiments, when the connection configuration between the processing unit 131 and the storage module is as shown in Figure 3, one or several processor cores may be dedicated to accessing data in the flash memory module. , while other processor cores can be dedicated to accessing data in flash-like memory modules. Therefore, the connection configuration shown in FIG. 3 can eliminate the need for the processing unit 131 to spend time reconfiguring the dual-mode flash memory interface 139 . However, compared to the connection shown in Figure 2, the parallel processing bandwidth of the dual-mode flash memory interface 139 will be reduced.

FIG. 4 shows an embodiment of the connection between the dual-mode memory interface 137 and the dynamic random access memory 151 and the quasi-dynamic random access memory 153 . The dual-mode memory interface 137 may include channels CH#0 to CH#3. Each channel CH can be connected to the same or different types of memory modules, for example: one type of dynamic random access memory module and two dynamic random access memory modules. For example, channel CH#0 connects the dynamic random access memory module 153#0 and two dynamic random access memory modules 151#0 and 151#4. In other words, different types of memory modules can share a channel. In this connection mode, the memory modules between multi-channel CHs can be accessed in multi-channel mode, which can increase the performance of data access. The processing unit 131 can access the dynamic random access memory modules 153#0~3 of channels CH#0~3 through CS#0 in multi-channel mode. The processing unit 131 can also enable CS# 1 and access the dynamic random access memory 151#0~3 of channels CH#0~3 in multi-channel mode.

FIG. 5 shows another embodiment of the connection between the dual-mode memory interface 137 and the dynamic random access memory 151 and the quasi-dynamic random access memory 153 . Each channel is only connected to the same type of memory module, each of channels CH#0 and CH#1 is only connected to DRAM-like modules, and each of channels CH#2 and CH#3 is only connected to DRAM modules. group. In this connection mode, the storage modules between multi-channel CHs can be accessed in multi-channel mode, which can increase the performance of data access. The processing unit 131 can access the DRAM-like modules 153 #0 and #3 of channels CH#0~1 in multi-channel mode by enabling CS#0. The processing unit 131 can also enable CS#0 and access the DRAM-like modules 153#0 and #3 of channels CH#0~1. The DRAM modules 153#0 and #3 of channels CH#2~3 are accessed in multi-channel mode.

The dual-mode memory interface 137 is configured with 51 pins. Table 2 shows the pin functions (Pin Function) of the dual-mode memory interface 137: Table 2 Pin number DDR4 DRAM-like I/F 0~7 Data[0:7] Data[0:7] 8 CS CS 9 RAS# Select_In 10 CAS# CA 11 Clock Clock 12 Clock_c Clock_c 13 Reset# Reset# 14 CKE CKE 15 ODT ODT 16 Alert Alert 17 x Select_Out 18 DQS# DQS# 19 ZQ ZQ 20 WP# x twenty one DTQS x 22~24 Chip ID [0:2] x 25 ACT x 26 DM x 27 DBI x 28~29 BG[0~1] x 30~31 BA[0~1] x 32~47 A[0-17] x 48 DTQS x 49 PAR x 50 TEN x

As shown in Table 2, the dual-mode memory interface 137 can be configured as a DDR4 interface to allow the processing unit 131 and the DDR4 DRAM module 151 to communicate with each other. In addition, the dual-mode memory interface 137 can also be configured as a DRAM-like interface to allow the processing unit 131 and the DRAM-like module 153 to communicate with each other. The dual-mode memory interface 137 may include a plurality of registers corresponding to the memory module pins, so that the processing unit 131 can set parameters output to specific pins of the memory module, such as preset voltage levels, driving methods ( Driven by positive or negative edges, or not working), whether it oscillates, etc. For example, when the dual-mode memory interface 137 is configured as a DDR4 interface, the processing unit 131 can configure the corresponding register to set the preset voltage level output to pin #15 to high or low voltage, and set the driving mode to inactive. , and set the parameter of whether to oscillate to No. When the dual-mode memory interface 137 is configured as a DRAM-like interface, the processing unit 131 can configure the corresponding register to set the preset voltage level output to pin #15 to low voltage and the driving mode to positive edge driving. And set the parameter of whether to oscillate to No. For another example, when the dual-mode memory interface 137 is configured as a DDR4 interface, the processing unit 131 can configure the corresponding register to set the oscillation parameter output to pin #11 to yes, and set the clock frequency to a value that the DRAM module can Accepted frequency. When the dual-mode memory interface 137 is configured as a DRAM-like I/F, the processing unit 131 can configure the corresponding register to set the oscillation parameter output to pin #11 to yes, and set the clock frequency to the DRAM-like I/F. acceptable frequency for the group.

Each memory module can input an independent CS signal. The processing unit 131 can access data in the memory modules on different channels CH#0 to CH#3 in parallel through the dual-mode memory interface 137. Specifically, the processing unit 131 can first send one of the chip selection signals CS#0~#3 to enable the designated memory module in each channel, and then pass the chip selection signal CS#0 to CH#3. Data line Data[0:7], parallel access to data in the enabled memory module. In addition, each channel can also transmit command address (CA), reset (Reset), wake-up (Wake), warning (Alert), input selection (Select_In), and output selection between enabled memory modules. (Select_Out), Chip ID, Activation Command Input ACT, Input Data Mask DM, Data Bus Inversion DBI, Bank Group BG), Bank Address (Bank Address), Address Input (Address Input), Command and Address Parity Input (PAR), Test Mode Enable and other control signals.

Based on the connections shown in FIG. 4 , the processing unit 131 can use different communication protocols to drive different types of memory modules, or drive different types of memory modules in different working modes. The processing unit 131 may reconfigure the dual-mode memory interface 137 before enabling another memory module. For example, the dual-mode memory interface 137 can be configured by the processing unit 131 to access the working mode of the DRAM-like module 153 when it is powered on. After the configuration is successful, the processing unit 131 drives the dual-mode memory interface 137 to send the enable signal CS0 to enable the DRAM-like modules 153#0 to 153#3, and then accesses the program instructions and comparison tables required for booting. , information, etc. After successful booting, the processing unit 131 can reconfigure the dual-mode memory interface 137 to the working mode of accessing the DRAM module 151 . After the configuration is successful, the processing unit 131 drives the dual-mode memory interface 137 to send the enable signal CS1 or CS2 to enable the DRAM modules 151#0 to 151#3 or the DRAM modules 151#4 to 151#7. Then, temporarily Stores the user data that the host device 110 is about to write into the flash memory 171, the user data that is read from the flash memory 171 and is about to be typed out to the host device 110, or the partial logical-entity mapping table required for search. wait. During accessing user data, if it is necessary to access program instructions, lookup tables or data in the DRAM-like module 153, the processing unit 131 can reconfigure the dual-mode DRAM-like module 153 before sending the enable signal CS0 to enable the DRAM-like module 153. The module memory interface 137 is a working mode for accessing the DRAM-like module 153 .

In some embodiments, when the processing unit 131 is a multi-processor with parallel processing capabilities, each processor core can control a specific channel to access data in some memory modules. For example, one processor core controls channels CH#0 and CH#1, while another processor core controls channels CH#2 and CH#3. In addition, in some embodiments, when the connection configuration between the processing unit 131 and the memory module is as shown in Figure 5, one or several processor cores can be dedicated to accessing data in the DRAM module. Other processor cores can be dedicated to accessing data in DRAM-like modules. Therefore, the connection configuration shown in FIG. 5 can eliminate the need for the processing unit 131 to spend time reconfiguring the dual-mode memory interface 137 . However, compared to the connection shown in FIG. 4 , the parallel processing bandwidth of the dual-mode memory interface 137 will be reduced.

Information and program instructions required for system startup, such as information blocks, complete logical-entity mapping tables, and in-system programming (ISP), are usually stored in non-volatile storage units. In some implementations, these necessary information and programs are stored in flash memory 171 . However, in order to shorten the system boot time, these necessary information and program instructions can be stored in the hybrid memory in the system architecture 100 of the embodiment of the present invention. The information block can record parameters used to configure the flash memory 171, such as bad block and bad column (Bad Column) locations in the flash memory 171, superblock architecture (Superblock Architecture), etc., and configure dynamic randomization. Access parameters of memory 151.

Referring to FIG. 1 , in some embodiments, the data storage device may be configured with dynamic random access memory 151 , hybrid memory 153 or 173 , and flash memory 171 . The complete L2P mapping table is preferably stored in the hybrid memory 153 or 173 to speed up the access of the L2P mapping table. The hybrid memory 153 or 173 can also be used as a fast flush storage space (Flush Storage Space). When a power outage occurs, the data in the dynamic random access memory 151 can be quickly flushed to the hybrid memory 153 or 173. . The dynamic random access memory 151 can be used to temporarily store hot data (Hot Data) and user data (User Data) from the main device 110; the flash memory 171 can be used as the main storage space (Main Storage Space) for backup. System code, cold data and/or Seldom Used Data.

In some embodiments, the data storage device may be configured with hybrid memory 153 and flash memory 171 . The complete L2P mapping table is preferably stored in the hybrid memory 153 to speed up access to the L2P mapping table. Since the hybrid memory 153 has a long-term data storage capability, the data storage device does not need to consider the processing of power outage events. The hybrid memory 153 can be used to store a small amount of hot data or user data of the autonomous device 110; the flash memory 171 is used as the main storage space to back up system code, cold data and /or use less data.

Referring to Figure 6, after receiving the system boot signal (step S610), the processing unit 131 can read and execute the boot code (Boot Code) from the read only memory (Read Only Memory, ROM) for entering the ROM mode (step S610). S631). In the ROM mode, the hybrid memory 153 or 173 is initialized (step S633). In step S633, the processing unit 131 may first detect the types of all storage units connected through the integrated interface, such as storage modules 171#0 to 171#7 and 173#0 to 173#5 and memory module 151#0. to 151#7 and 153#0 to 153#5 types, used to find hybrid memory 153 or 173. In some embodiments, the processing unit 131 can determine the memory by detecting the voltage level on a specific pin of the specific enabled memory or storage module through the hardware of the dual-mode memory interface 137 or the dual-mode flash memory interface 139 Whether the memory or storage module is a hybrid memory. For example, the processing unit 131 may detect the voltage level on pin #14 of the enabled storage module through the hardware of the dual-mode flash memory interface 139 . If the voltage level is low, it is determined that the enabled storage module is a flash memory module; otherwise, it is determined that the enabled storage module is a flash memory module. In other embodiments, the processing unit 131 may execute firmware instructions for sending hybrid memory-recognizable commands to the enabled specific memory or storage module through the dual-mode memory interface 137 or the dual-mode flash memory interface 139. And based on whether the correct reply is received, it is determined whether the memory or storage module is a hybrid memory. Next, the processing unit 131 reads the ISP code, configuration parameters and L2P mapping table from the hybrid memory 153 or 173 (steps S651, S653 and S655), and initializes the flash memory 171 and dynamic random access according to the configuration parameters. Memory 151 (steps S671 and S673). The processing unit 131 then executes the ISP code, enters the normal working mode (Normal Mode), and waits for a command issued by the main device 110 (step S690). In some embodiments of the normal working mode, in order to speed up the search and update of the L2P mapping table, part of the L2P mapping table that is being used or is about to be used can be temporarily stored in the dynamic random access memory 151, and updated back at an appropriate point in time. Hybrid memory 153 or 173. In addition, part of the Physical-Logical Mapping Table (P2L Table) required for searching or updating can be temporarily stored in the dynamic random access memory 151 or the static random access memory 133 . The dynamic random access memory 151 can first temporarily store the user data to be written by the host device 110. After that, the processing unit 131 can write the temporarily stored data into the hybrid memory 153 or 173 or fast according to the characteristics of the user data. Flash memory171.

Referring to FIG. 1 , in other embodiments, the data storage device may be configured with hybrid memory 153 or 173 and flash memory 171 , but without dynamic random access memory 151 . The complete L2P mapping table is permanently stored in the hybrid memory 153 or 173. The hybrid memory 153 or 173 can provide fast flash storage space, while the flash memory 171 can provide the main storage space. Referring to FIG. 7 , since the data storage device is not configured with the dynamic random access memory 151 , the processing unit 131 cannot execute step S673 in FIG. 6 to initialize the dynamic random access memory 151 according to the configuration parameters. Instead, the processing unit 131 may request the host device 110 to configure a portion of the dynamic random access memory space from the host side as a host memory buffer (Host Memory Buffer, HMB) (step S773). In some embodiments of the normal working mode, in order to speed up the search and update of the L2P mapping table, part of the L2P mapping table being used or about to be used can be temporarily stored in the host memory buffer, and updated back to the hybrid memory at an appropriate point in time. 153 or 173. In addition, part of the physical-logical table required during search or update can be temporarily stored in the host memory buffer or static random access memory 133 . The host memory buffer can first temporarily store the user data to be written by the host device 110, and then the processing unit 131 can write the temporarily stored data into the hybrid memory 153 or 173 or the flash memory 171 according to the characteristics of the user data. .

Steps S610 to S673 in FIG. 6 and steps S610 to S671 and S773 in FIG. 7 can be called steps performed in the system booting stage (System Booting Stage).

In some embodiments of the normal operating mode, the static random access memory 133 can be used to temporarily store data to be written to the flash memory 171 or the hybrid memory 153 or 173, or from the flash memory 171 or the hybrid memory 153 or 173. Data is read from memory 153 or 173, and direct access memory (DMA) technology is used to move data between the two components.

In some embodiments of the normal operating mode, the processing unit 131 may execute the same wear leveling algorithm to manage the flash memory 171 and the flash-like memory 173 . The static random access memory 133 can store the write/erase count (Program/Erase Count, P/E Count) of each physical block (Physical Block) in the flash memory module 171 and the flash-like memory 173 ). However, the startup threshold (Threshold) for the wear leveling operation of the physical blocks in the flash memory 171 and the flash-like memory 173 may be the same or different.

In some embodiments of the normal working mode, the processing unit 131 may perform a garbage collection (Garbage Collection GC) operation for the flash memory 171 and the flash-like memory 173 . The processing unit 131 may configure a part of the space in the hybrid memory 153 or 173 as an over provision space to serve as a buffer for data movement or other operations.

In some embodiments of the normal working mode, for sudden power off recovery (SPOR), the processing unit 131 can periodically or when specific conditions are met, buffer the dynamic random access memory 151 or the host memory. Data is written to the non-volatile hybrid memory 153 or 173 or the flash memory 171 . The temporarily stored L2P mapping table and user data can be better written into the hybrid memory 153 or 173, so that the recovery operation after a sudden power outage can be more efficient.

In some embodiments, when the space of the hybrid memory 153 or 173 is sufficient, the processing unit 131 may not use the flash memory 171 . When the space of the hybrid memory 153 or 173 is insufficient, the flash memory 171 is initialized and the space in the flash memory 171 is used.

All or part of the steps in the method of the present invention can be implemented by a computer program, such as a computer operating system, a driver for specific hardware in the computer, or a software application. In addition, it can also be implemented in other types of programs as shown above. Those with ordinary skill in the art can write the methods of the embodiments of the present invention into computer programs, which will not be described again for the sake of simplicity. The computer program implemented according to the method of the embodiment of the present invention can be stored in an appropriate computer-readable data carrier, such as DVD, CD-ROM, USB disk, hard disk, or can be placed in a computer program that can be accessed through a network (such as the Internet). , or other appropriate vehicle).

Although the above-described elements are included in FIGS. 1 to 5 , it does not rule out that more other additional elements may be used to achieve better technical effects without violating the spirit of the invention. In addition, although the flow charts of Figures 6 and 7 are executed in a specified order, those skilled in the art can modify the order of these steps to achieve the same effect without violating the spirit of the invention. Therefore, The present invention is not limited to the use of only the sequence described above. In addition, those skilled in the art can also integrate several steps into one step, or in addition to these steps, perform more steps sequentially or in parallel, and the invention is not limited thereby.

Although the present invention is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, this invention covers modifications and similar arrangements which will be obvious to one skilled in the art. Therefore, the scope of the claims of the application must be interpreted in the broadest manner to include all obvious modifications and similar arrangements.

100:System architecture

110: Main device

130:Controller

131: Processing unit

132: Read-only memory

133: Static random access memory

135: Main device interface

137:Dual-mode memory interface

139:Dual-mode flash memory interface

151:Dynamic Random Access Memory

171#0~171#7:DRAM module

153: Class dynamic random access memory

153#0~153#5: DRAM-like module

171:Flash memory

171#0~171#7: Flash memory module

173: Flash-like memory

173#0~173#5: Flash memory module

CH#0~CH#3: Channel

CE#0~CE#2: Chip enable signal

CS0~CS2: chip selection signal

S610～S690, S773: Method steps

FIG. 1 is a schematic system architecture diagram of a flash storage device according to an embodiment of the present invention.

2 and 3 are schematic diagrams of connections between flash memory interfaces and different types of flash memories according to embodiments of the present invention.

4 and 5 are schematic diagrams of connections between memory interfaces and different types of dynamic random access memories according to embodiments of the present invention.

FIG. 6 is a system boot flow chart of a data storage device equipped with a dynamic random access memory according to an embodiment of the present invention.

FIG. 7 is a system boot flow chart of a data storage device without dynamic random access memory according to an embodiment of the present invention.

100:System architecture

110: Main device

130:Controller

131: Processing unit

132: Read-only memory

133: Static random access memory

135: Main device interface

137:Memory interface

139:Flash memory interface

151:Dynamic Random Access Memory

153: Class dynamic random access memory

171:Flash memory

173: Flash-like memory

Claims (14)

A device for controlling different types of storage units, including: An interface includes a plurality of channels, wherein each channel is connected to a first type and a second type of storage unit; and A processing unit coupled to the interface for configuring the interface into a first working mode, wherein the first working mode corresponds to the first type of storage unit; driving the interface to send a first signal to enable connection to the multiple channels of the first type of storage unit; driving the interface to access data of the first type of storage unit; and before accessing data of the second type of storage unit, reconfiguring the interface as a first type Two operating modes, wherein the second operating mode corresponds to the second type of storage unit. The device of claim 1, wherein the first type of storage unit is a non-volatile flash memory module, the second type of storage unit is a flash memory module, and the processing unit is powered on When configuring the interface as the first working mode, and driving the interface to access the parameters of the flash memory module used to configure the flash memory module, the processing unit is configured after the boot is successful. This interface is the second working mode. The device of claim 1, wherein the first type of storage unit is a non-volatile type of dynamic random access memory module, the second type of storage unit is a dynamic random access memory module, and the The processing unit configures the interface in the first working mode when booting, and drives the interface to access parameters used to configure the dynamic random access memory module in the dynamic random access memory module. After successful startup, the processing unit configures the interface as the second working mode. A computer program product that includes a program code that, when executed by a processing unit, is used to control different types of storage units. The program code is used to: Configuring an interface as a first working mode, wherein the interface includes a plurality of channels, each channel is connected to a first type and a second type of storage unit, the first working mode corresponds to the first type of storage unit; driving the interface to send a first signal to enable the first type of storage unit connected to the plurality of channels; driving the interface to access data of the first type of storage unit; and Before accessing data of the second type of storage unit, the interface is reconfigured into a second working mode, and the second working mode corresponds to the second type of storage unit. The computer program product of claim 4, wherein the first type of storage unit is a non-volatile flash memory module, the second type of storage unit is a flash memory module, and the program code Used for: Configuring the interface as the first working mode when booting, and driving the interface to access parameters used to configure the flash memory module in the flash memory module; and After successful startup, the interface is configured as the second working mode. The computer program product of claim 4, wherein the first type of storage unit is a non-volatile type of dynamic random access memory module, and the second type of storage unit is a dynamic random access memory module. , this code is used to: Configure the interface as the first working mode when booting, and drive the interface to access parameters used to configure the dynamic random access memory module in the dynamic random access memory module; and After successful startup, the interface is configured as the second working mode. A device for controlling different types of storage units, including: An interface connects a plurality of storage units, wherein the plurality of storage units include a non-volatile hybrid memory and a flash memory; and A processing unit coupled to the interface for initializing the hybrid memory during a system boot phase; reading a first parameter that configures the flash memory from the hybrid memory, and an in-system program code; initialize the flash memory according to the first parameter; and execute the system program code for entering a normal operating mode and waiting for a command issued by a host device. The device of claim 7, wherein the processing unit detects the types of all the storage units connected through the interface to find the hybrid memory before initializing the hybrid memory. The device of claim 8, wherein the processing unit detects the voltage level on a specific pin of the enabled specific storage unit through the hardware of the interface to determine whether the specific storage unit belongs to the hybrid memory. . The device of claim 8, wherein the processing unit sends a command identifiable by the hybrid memory to an enabled specific storage unit through the interface, and determines whether the specific storage unit belongs to Hybrid memory. A computer program product that includes a program code that, when executed by a processing unit, is used to control different types of storage units. The program code is used to: During a system startup phase, initialize a non-volatile hybrid memory; Reading a first parameter that configures a flash memory and an in-system program code from the hybrid memory; Initialize the flash memory according to the first parameter; and Execute the program code in the system to enter a normal working mode and wait for a command issued by a master device. A computer program product as described in request 11, the code being used to: Before initializing the hybrid memory, detect the types of all storage units connected through an interface to find the hybrid memory. A computer program product as described in request 12, the program code being used to: Reading a second parameter that configures a dynamic random access memory from the hybrid memory; and The dynamic random access memory is configured according to the second parameter. A computer program product as described in request 12, the program code being used to: Requests the host device to configure a portion of the dynamic random access memory space from the host side as a host memory buffer.

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