CN111399750A - Flash data writing method and computer readable storage medium - Google Patents

Abstract

The invention provides a data writing method of a flash memory, which is executed by a processing unit and comprises the following steps: before executing a part of logic-physical comparison table updating or garbage recycling program, judging whether a host writing instruction needing immediate processing exists in a submission queue; and when the host write command needing immediate processing exists, executing the host write command in a batch, and then executing the part of the logic-physical comparison table updating or garbage collection program.

Description

Flash data writing method and computer readable storage medium

technical field

The present invention relates to a storage device, in particular to a data writing method of a flash memory and a computer-readable storage medium.

Background technique

Flash memory is usually divided into NOR flash memory and NAND flash memory. The NOR flash memory is a random access device, and the host device (Host) can provide any address for accessing the NOR flash memory on the address pin, and obtain the data stored at the address from the data pin of the NOR flash memory in time. In contrast, NAND flash memory is not random access, but sequential access. NAND flash memory cannot access any random address like NOR flash memory. Instead, the host device needs to write the value of a sequence of bytes (Bytes) into the NAND flash memory to define the type of command requested (eg, read , write, erase, etc.), and the address used on this command. The address can point to a page (the smallest block of data in flash for write operations) or a block (the smallest block of data in flash for erase operations).

The latency of data writing (Latency) is one of the important measurement items of Quality of Service QoS. In this test, 4K data can be randomly written to the memory cells for several hours, the memory cells are placed in Dirty Mode, and then the 4K data can be randomly written for 180 seconds with the command depth of QD1/QD128, and the delay time is measured. Since the storage unit is in the dirty mode, the NAND flash memory also needs to arrange time to write the updated logical-physical comparison table (Host-Flash H2F Table) in the static random access memory or the dynamic random access memory to the storage unit, so as to Reduced the time to perform SPO Recovery SPOR after Sudden Power Off SPO. In addition, when the NAND flash memory is in the dirty mode, it is necessary to arrange time to perform a garbage collection (Garbage Collection GC) operation to prevent the storage unit from being unable to write user data due to insufficient space. The present invention provides a data writing method of flash memory and a calculator program product, which are used to meet the measurement requirements of delay time when the storage unit is in the dirty mode.

SUMMARY OF THE INVENTION

In view of this, how to alleviate or eliminate the above-mentioned deficiencies in related fields is a problem to be solved.

The present invention provides a method for writing data in flash memory. The method is implemented by a processing unit when loading and executing program codes of software or firmware modules. Whether there is a host write command that needs to be processed immediately in the submission queue; and when there is a host write command that needs to be processed immediately, first execute the host write command in one batch, and then execute the part of the logical-physical comparison table update or Garbage collector.

The present invention further provides a computer-readable storage medium written with flash memory data, which is used for storing a computer program executable by a processing unit, and when the computer program is executed by the processing unit, the following steps are implemented: Before the comparison table is updated or the garbage collection program, it is judged whether there is a host write command that needs to be processed immediately in the submission queue; and when there is a host write command that needs to be processed immediately, first execute the host write command in one batch, and then execute it again This part of the logical-physical table update or garbage collector.

One of the advantages of the above-mentioned embodiment is that, through the above judgment, it can avoid too long waiting time for some host write instructions in the delivery queue due to the update of the logical-physical comparison table or the execution of the garbage collection program.

Other advantages of the present invention will be explained in more detail in conjunction with the following description and drawings.

Description of drawings

The drawings described herein are used to provide further understanding of the present application and constitute a part of the present application. The schematic embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation of the present application.

FIG. 1 is a schematic diagram of a system architecture of a flash memory according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of the connection between the flash memory interface and the LUN.

FIG. 3 is a schematic diagram of an instruction queue.

FIG. 4 is a schematic diagram of a Flash Translation Layer (FTL) architecture.

FIG. 5 is a flowchart of a data writing method of some embodiments.

FIG. 6 is a flowchart of a method for processing a host write command according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of the arrival and processing of a host write command according to an embodiment of the present invention.

8 is a flowchart of a method for updating a logical-physical comparison table (Host-Flash H2F Table) according to an embodiment of the present invention.

FIG. 9 is a schematic diagram of physical storage comparison.

FIG. 10 is a flowchart of a method for executing a garbage collection (Garbage Collection GC) program according to an embodiment of the present invention.

【List of reference numerals】

100 Electronics

110 Main unit

120, 131 Random Access Memory

130 Storage

132 host interface

133 processing unit

135 Flash Controller

137 Flash interface

139 LUNs

139#0 to 139#11 LUNs

CH#0～CH#3 Output input channel

CE#0～CE#2 enable signal

310 Delivery queue

330 Completion queue

CQH, CQT, SQH, SQT pointers

410, 430, 450, 470 software or firmware modules

S510～S590, S611～S635, S810～S870, S1010～S1070 Method steps

70 Execution of a batch of host write commands

70a Start of operation time point

70b, T0, T1, T2, T3 end running time point

W0～W12 Host write command

910 H2F Form

930 Physical address information

930-0 (physical) block number

930-1 (physical) page number and offset

930-2 (Physical) Plane Number

930-3 Logical Unit Number

Detailed ways

The embodiments of the present invention will be described below with reference to the related drawings. In the figures, the same reference numbers refer to the same or similar components or method flows.

It must be understood that words such as "comprising" and "including" used in this specification are used to indicate the existence of specific technical features, values, method steps, job processes, components and/or components, but do not exclude the possibility of Plus more technical features, values, method steps, job processes, components, components, or any combination of the above.

The use of words such as "first", "second" and "third" in the present invention is used to modify the components in the claims, and is not used to indicate that there is a priority order, a precedence relationship between them, or that a component comes first Another component, or the chronological order in which method steps are executed, is only used to distinguish components with the same name.

It must be understood that when an element is described as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, and intervening elements may be present. In contrast, when a component is described as being "directly connected" or "directly coupled" to another component, there are no intervening components present. Other words used to describe the relationship between components may also be read in a similar fashion, such as "between" versus "directly intervening," or "adjacent" versus "directly adjoining," and the like.

Refer to Figure 1. The electronic device 100 includes a host device 110 , a random access memory (Random Access Memory RAM) 120 and a storage device 130 . The master device 110 may create a queue according to its needs during operation. The electronic device 100 is, for example, an electronic product such as a personal computer, a notebook computer (Laptop PC), a tablet computer, a mobile phone, a digital camera, and a digital video camera. Certain portions of random access memory 120 may be configured as data buffers, queues, and the like. The storage device 130 may include a processing unit 133 , and may also include a random access memory 131 to improve the performance of the storage device 130 . The processing unit 133 may receive commands from the host device 110 through the host interface (Host Interface) 132, and instruct the flash memory controller 135 to perform operations such as data reading, writing, and erasing accordingly. Universal Flash Storage UFS, Non-Volatile Memory Express NVMe, Universal Serial Bus USB, and Advanced Technology Attachment ATA can be used between the host device 110 and the processing unit 133. ), serial advanced technology attachment (serial advanced technology attachment SATA), peripheral component interconnect express PCI-E and other communication protocols for communication. Either of the main device 110 and the processing unit 133 may be implemented using a variety of ways, such as using general purpose hardware (eg, a single processor, multiprocessor capable of parallel processing, graphics processor, or other processor capable of computing) , and, when executing software and/or firmware instructions, provide the functionality described later. The random access memories 120 and 131 can store data required during execution, such as variables, data tables, and the like.

The logical unit number (Logical Unit Number LUN) 139 provides a large amount of storage space, usually hundreds of Gigabytes, or even Terabytes, which can be used to store a large amount of user data, such as high-resolution pictures, movies, and the like. The LUN 139 includes a control circuit and a memory array, and the memory cells in the memory array may be triple level cells (TLCs) or quad-level cells (Quad-Level Cells QLCs). The random access memory 131 can be used to cache the user data that the main device 110 will write to the LUN 139, the user data that is read from the LUN 139 and will be typed out to the main device 110, and the logical-physical comparison table (Logical-Physical) required for searching. Mapping Table, L2P Table). Random access memory 131 may also store data required in the execution of software and firmware instructions, eg, variables, data tables, and the like. The random access memory 131 may include a state random access memory (SRAM), a dynamic random access memory (DRAM), or both.

The storage device 130 further includes a flash memory controller 135, a flash memory interface 137 and a LUN 139, and the flash memory controller 135 communicates with the LUN 139 through the flash memory interface 137. In detail, a double data rate (Double Data Rate DDR) communication protocol can be used, for example, Open NAND Flash (Open NAND Flash Interface ONFI), Double Data Rate Switch (DDRToggle) or other interfaces. The flash controller 135 of the storage device 130 writes user data to a designated address (destination address) in the LUN 139 through the flash interface 137 , and reads user data from a designated address (source address) in the LUN 139 . The flash memory interface 137 uses a plurality of electronic signals to coordinate data and command transfer between the flash memory controller 135 and the LUN 139 , including data lines, clock signals, and control signals. Data lines can be used to transmit commands, addresses, read and written data; control signal lines can be used to transmit Chip Enable CE, Address Latch Enable ALE, Command Latch Enable CLE ), write enable (Write Enable WE) and other control signals. The processing unit 133 and the flash memory controller 135 may exist separately or be integrated in the same chip.

Referring to FIG. 2 , the flash memory interface 137 may include four I/O channels (I/O channels, hereinafter referred to as channels) CH#0 to CH#3, each channel is connected to three LUNs, for example, channel CH#0 is connected to LUN139#0 , 139#4 and 139#8. It should be noted that, in order to meet different system requirements, those skilled in the art can set multiple channels in the flash memory interface 137, and connect each channel to at least one LUN, and the present invention is not limited thereby. Flash controller 135 may drive flash interface 137 to issue one of enable signals CE#0 to CE#2 to enable LUNs 139#0 to 139#3, 139#4 to 139#7, or 139#8 to 139#11 , and then read user data from the enabled LUN, or write user data to the enabled LUN in parallel.

Referring to FIG. 3 , the command queue may include a Submission Queue (SQ) 310 and a Completion Queue (CQ) 330, which are used to temporarily store the host device command and the CompletionElement CE, respectively. The submit queue 310 and the completion queue 330 are preferably created in the same device, for example, the submit queue 310 and the completion queue 330 are preferably created in the random access memory 120 on the host side, or can also be created in the storage device 130 in random access memory 131. The submit queue 310 and the completion queue 330 may also be established in different devices. Each of submit queue 310 and completion queue 330 includes a collection of multiple entries. Each item in the submission queue 310 can store an I/O command, such as an erase, read, write command, and so on. The items in the collection are stored sequentially. The basic principle of the operation of the set is to add an entry (may be called enqueue) from the end position (such as the position pointed to by the pointer SQT or CQT), and remove the entry (such as the position pointed to by the pointer SQH or CQH) ( may be called dequeue). That is, the first instruction added to the submit queue 310 will also be the first to be removed. The host device 110 may write a plurality of write commands to the submit queue 310 , and the processing unit 133 reads (or called fetch fetch) the earliest arriving write command from the submit queue 310 and executes it. After the execution of the write instruction is completed, the processing unit 133 writes the completion element to the completion queue 330, and the host device 110 can read or extract the completion element to determine the execution result of the write instruction.

Referring to FIG. 4 , the Flash Translation Layer (FTL) architecture includes a write command read module 410 , a write command execution module 430 , an H2F table write module 450 and a garbage collection (Garbage Collection GC) operation module 470 . The function HW_PushIOCmdInfoPrdInfo() can include the program code of the write command reading module 410, and when the processing unit 133 loads and executes it, reads a specified number of host write commands (Host Write Commands) from the delivery queue, and writes the host write commands to be written. The user data of the specific logical address (Logical Address) is temporarily stored in the random access memory 131 . The function FTL_HandlePrdInfo() may include the program code of the write instruction execution module 430, and when the processing unit 133 loads and executes the write instruction from the host, the user data temporarily stored in the random access memory 131 is written through the flash controller 135 and the flash interface 137 according to the host write instruction The LUN 139 obtains the physical address (Physical Address) from the information recovered by the flash controller 135 , and then updates the corresponding relationship between the logical address and the physical address to an appropriate position in the H2F table in the random access memory 131 . The function SaveMap( ) may contain the program code of the H2F table writing module 450 and write the updated H2F table to the LUN 139 through the flash controller 135 and the flash interface 137 when the processing unit 133 loads and executes it. When the processing unit 133 loads and executes the GC operation module 470, it collects broken user data in multiple physical pages, and writes the collected user data into a new physical page in the LUN 139 through the flash controller 135 and the flash interface 137, using So that these freed physical pages can be used by other user data after erasing.

In some embodiments, the processing unit 133 may implement the method flow shown in FIG. 5 when loading and executing the program code of the control module. When the processing unit 133 detects that the host device 110 starts to write the host write command into the delivery queue 310, the loop (steps S510 to S590) may be repeatedly executed until there is no host write command in the delivery queue 310 (in step S590 "" No" path). In each iteration (Iteration), the processing unit 133 may execute the write command reading module 410 , the write command executing module 430 , the H2F table writing module 450 and the GC operation module 470 in sequence. However, when the running time of the H2F table writing module 450 or the GC operation module 470 is too long, the waiting time for submitting the host write command in the queue 310 may be too long, thereby causing a delay that cannot meet the quality of service (QoS) requirements. Time metric requirements. In addition, since the host device 110 can write any number of host write commands to the submission queue 310 at any time point, the host interface 132 (referred to as hardware HW for short) can only read the upper limit number of host write commands at most. If the host device 110 issues more than the upper limit number of host write commands at one time, the host interface 132 can only read the upper limit number of host write commands for the write command reading module 410 to process. The remaining host write commands can only be processed by the command read module 410 in the next round. Due to the lack of information on the time when each host write command arrives at the delivery queue 310, the control module (which may be referred to as Firmware FW for short) cannot know how long the host write command obtained from the hardware has been delayed.

To complement the time information of host write commands arriving at submit queue 310 , in some embodiments, write command reading module 410 may be modified to append a timestamp to newly arriving host write commands in submit queue 310 during processing of the host write commands. Referring to the embodiment of the method for processing a host write instruction shown in FIG. 6 , the method is implemented when the processing unit 133 loads and executes the program code of the write instruction reading module 410 . First, a cycle (steps S611 to S613 ) is repeatedly executed for reading all host write commands that need to be processed immediately in the delivery queue 310 in one batch (Batch). Due to hardware limitations, the processing unit 133 reads no more than the upper limit number of host write instructions per round. In step S611 of entering the loop for the first time, the processing unit 133 may read the time information of the host write command arriving in the submission queue 310 from the random access memory 131, and determine the host write command to be processed immediately according to the time information. Time information to arrive at the submission queue 310 can be implemented using Table 1 below:

Table 1

instruction set number Host write command number arrival timestamp S0 W0-W4 T0 S1 W5-W9 T1

Each entry in Table 1 can be associated with an instruction set, containing the instruction set number, the number of the host write instructions contained in this data set, and the arrival timestamps associated with all host write instructions. For example, the instruction set "S0" contains host write instructions "W0" to "W4", and their arrival time in the commit queue 310 is "T0". "W0" to "W4" may also represent the host write commands that submit the 0th to 4th items in the queue 310. The processing unit 133 can use the formula (1) to determine whether the host write instruction in an instruction set needs to be processed immediately:

Tnow-Ti>Ttr

Wherein, Tnow represents the current time, i represents a positive integer, Ti represents the arrival time point of the i-th host write command in the delivery queue 310 , and Tr represents a threshold. The setting of the threshold can refer to the requirements of the delay time measurement item. For example, if the delay time measurement item requires that the delay time of 99% of the host write commands needs to be less than 5 milliseconds (ms), the threshold value can be set between 4 and 5 The value in milliseconds. When the condition of formula (1) is satisfied, it means that the i-th host write command in the delivery queue 310 needs to be processed immediately.

In the cache mode (Cache Mode), the processing unit 133 can obtain each host write command from the submission queue 310 through the host interface 132, and read the pending write command from the random access memory 120 through the host interface 132 according to the address information in the host write command. user data into the LUN 139 , and store the user data in the random access memory 131 . Since the completion host write command is executed when the user data is stored in the random access memory 131 , the processing unit 133 can write the Completion Element CE corresponding to the host write command to the completion queue 330 through the host interface 132 . Afterwards, the processing unit 133 can schedule time to execute the program code of the write instruction execution module 430 for writing the user data temporarily stored in the random access memory 131 into the LUN 139 through the flash memory controller 135 and the flash memory interface 137 .

In the non-cache mode or the storage device 130 is not configured with a storage space for temporarily storing user data, after the processing unit 133 obtains one or more host write commands and the user data to be written through the host interface 132, the processing unit 133 can directly Jump to executing the program code of the write instruction execution module 430 for writing user data to the LUN 139 through the flash memory interface 137 . After successfully writing to the LUN 139 , the processing unit 133 may switch back to executing the program code of the write command execution module 430 for writing the completion components corresponding to the host write command(s) to the completion queue 330 . In some embodiments, the write instruction execution module 430 and the write instruction execution module 430 can be integrated into a single module and are not limited to the FTL architecture.

After the loop is executed, the processing unit 133 obtains from the random access memory 131 the time stamp Tpre representing the read end of the last batch of host write commands (step S631 ), updates the arrival time information in the random access memory 131, and uses After deleting the record of the processed host write command, and adding Tpre to the record of the new host write command in the submission queue 310 (step S633), and updating Tpre to a timestamp representing the current time for the next batch of hosts The execution reference of the write command (step S635).

The following example is used to assist in explaining the method flow shown in FIG. 6 . Referring to FIG. 7 , the execution of the write instruction reading module 410 of the previous batch ends at time point T2 and the execution 70 of the write instruction reading module 410 of this batch starts at time point 70a and ends at time point T3 (70b ). At time point 70a, the random access memory 131 stores the execution end timestamp Tpre of the last batch of host write commands as time point T2, and the host write commands "W0" to "W9" as described in Table 1 arrive at the submission queue 310 time information. Assuming that the instruction set "S0" (that is, the host write instructions "W0" to "W4") satisfies the condition of the formula (1), it needs to be processed immediately. Then, the processing unit 133 reads the host write commands "W0" to "W4" in the submit queue 310 (step S631). Near the time point T3, the read operation of the host write commands "W0" to "W4" ends. After the operation ends, the processing unit 133 reads the execution end timestamp Tpre (= T2 ) of the last batch of host write commands from the random access memory 131 (step S633 ). Suppose that between time points T2 and T3, the host device 110 writes the host write commands "W10" to "W12" to the submit queue 310, and changes the pointer SQT to point to the thirteenth item in the submit queue 310. By comparing the arrival time information in the random access memory 131 with the address currently pointed by the pointer SQT, the processing unit 131 can know that the host device 110 newly writes the host write commands "W10" to "W12" to the submit queue 310. Next, the processing unit 131 updates the arrival time information as shown in Table 2 (step S633):

Table 2

instruction set number Host write command number arrival timestamp S1 W5-W9 T1 S2 W10-W12 T2

Although the actual arrival time of the host write commands "W10" to "W12" is later than the time point T2, since the write command reading module 410 does not know the actual arrival time of any host write command, the earliest possible arrival time T2 is used as the timestamp , which can reduce the possibility that the actual delay time of the host write command exceeds the time measurement requirement.

Although only two queues 310 and 330 are shown in FIG. 3 , the host can create a larger number of Submission Sub-queues and Completion Sub-queues according to different application requirements. Table 1 can be modified to include the arrival time information of the host write commands in different delivery sub-queues, and make an aggregate judgment on whether the host write commands in all the delivery sub-queues need to be processed immediately, and the present invention is not limited by this.

In order to solve the technical problem generated when the LUN 139 is in the dirty mode, the method flow shown in FIG. 8 and FIG. 10 is a data writing method of a flash memory, and this method is loaded by the processing unit 133 and executes the program code of the relevant software or firmware module. It is implemented at the time of implementation, including the following steps: before executing a part of the H2F table update or GC operation, determine whether there is at least one host write command that needs to be processed immediately in the submission queue 310; and when there is a host write command that needs to be processed immediately, first One batch executes the host write command(s), and then executes the H2F table update or GC operation in this part; and when there is no host write command that needs to be processed immediately, directly executes the H2F table update or GC operation in this part . Those skilled in the art understand that H2F table update and GC operations are operations initiated by the storage device 130 to optimize the performance of the storage device 130 , rather than initiated by the host device 110 like a host write command. Details are as follows:

To avoid frequently updating the H2F table in the LUN 139, the processing unit 133 may temporarily store all or part of the H2F table in the random access memory 131 (usually DRAM), and update the contents of the temporarily stored H2F table after the write operation is completed. In order to shorten the time for performing SPO Recovery SPOR after a sudden power failure (Sudden Power Off SPO), the processing unit 133 will write the updated content of the temporary H2F table into the LUN 139 after updating a certain number of records. . Such H2F table write operations may be more frequent when storage device 130 is in dirty mode. However, the processing unit 133 and the flash memory interface 137 need a period of time to complete the entire write operation of the part that needs to be updated, which may cause the waiting time of some host write commands in the delivery queue 310 to be too long to meet the delay time measurement requirement of QoS. In order to avoid the above problems, in some embodiments, the H2F table writing module 450 can be modified to divide all the updated content in the H2F table into several segments, and determine whether there is a need for immediate Handles the host write command. When there are host write commands that need to be processed immediately, these host write commands are processed first.

Referring to FIG. 9, the H2F table 910 preferably stores physical address information corresponding to each logical address (or Logical Block Address LBA) in order. The space required for H2F table 910 is preferably proportional to the total number of logical addresses. The logical address can be represented by a logical block address, and each LBA corresponds to a logical block of a fixed size, such as 512 bytes (Bytes), and is stored in a physical address. For example, the H2F table 910 sequentially stores physical address information from LBA#0 to LBA#65535. Data of several consecutive logical addresses (eg LBA#0 to LBA#7) can form a host page. The physical address information 330 includes, for example, four bytes, wherein 930-0 records the (physical) block number ((Physical) Block Number), and 930-1 records the (physical) page number and offset (offset); 930 -2 records the (physical) plane number, 930-3 records the logical unit number and the output input channel number and so on. For example, physical address information 930 corresponding to LBA #2 may point to a local 951 in block 950 .

Referring to the embodiment of the H2F table updating method shown in FIG. 8 , the method is implemented when the processing unit 133 loads and executes the program code of the H2F table writing module 450 . The processing unit 133 may repeatedly execute a loop (steps S810 to S870 ) for segmenting and writing all the updated contents in the H2F table to the LUN 139 . For example, when the physical address information about LBA#0 to LBA#2047 in the temporary H2F table is updated, the processing unit 133 may first write the information about LBA#0 to LBA#1023 (ie, the first segment) in one batch. physical address information, and write the physical address information about LBA#1028 to LBA#2047 (that is, the second segment) in the next batch. In each round, the processing unit 133 first determines whether there is a host write command that needs to be processed immediately (step S810). For the determination of the host write command, reference may be made to the descriptions in Table 1, step S613 and formula (1) above, which will not be repeated for brevity. When there is a host write command that needs to be processed immediately (the "Yes" path in step S810 ), the processing unit 133 first reads the host write command that needs to be processed immediately (step S830 ), and then stores the updated content in the H2F table to LUN 139 (step S850). When there is no host write command that needs to be processed immediately ("No" path in step S810), a segment of updated content in the H2F table is directly stored to the LUN 139 (step S850).

When storage device 130 is in dirty mode, many physical pages in LUN 139 may contain valid and invalid sections (also called expired sections), where valid sections store valid user data and invalid sections store invalid ( old) user data. When the processing unit 133 detects that the free space of the LUN 139 is insufficient, it can instruct the flash controller 135 to read and collect the user data in the valid sectors in the source block, and then instruct the flash controller 135 to rewrite the collected valid sectors. The user data is transferred to the empty physical pages of the active block (or destination block), so that these data blocks (source blocks) containing invalid user data can be changed into idle blocks. After that, after erasing, the idle block can be used as an active block to provide data storage space. A procedure like the above is called garbage collection.

However, the processing unit 133 and the flash memory interface 137 need a period of time to complete the entire GC procedure, which may cause the waiting time of some host write commands in the submission queue 310 to be too long to meet the delay time requirement of QoS. In order to avoid the above problems, in some embodiments, the GC operation module 470 can be modified to divide the entire garbage collection process into several stages, and determine whether there is a host write command that needs to be processed immediately before executing the work of one stage. When there are host write commands that need to be processed immediately, these host write commands are processed first.

In some embodiments, the entire GC procedure can be divided into five stages of operations: the processing unit 133 can determine the source address of the valid user data in the source block and the destination address of the destination block in the first stage. In the second stage, the processing unit 133 may instruct the flash controller 135 to read user data from the source address of the LUN 139 and instruct the flash controller 135 to write the read user data to the destination address of the LUN 139 . In the third and fourth stages, the processing unit 133 can update the H2F table and the Physical-Logical Mapping Table (P2L table) respectively. The processing unit 133 may change the target block to an idle block in the fifth stage. The above five stages are only examples, and those skilled in the art can combine several stages into a single stage in the GC operation module 470 according to the working speed of the processing unit 133, the flash memory controller 135 and the flash memory interface 137, or split one stage into a single stage. into several sub-stages. In addition, the GC operation module 470 can optimize the execution sequence of the five stages according to the processing state. For example, the first to second stages are arranged in a cycle until the destination block can no longer write user data from the source block. Then perform the third to fifth stages.

Referring to the embodiment of the execution method of the GC program shown in FIG. 10 , the method is implemented when the processing unit 133 loads and executes the program code of the GC operation module 470 . The processing unit 133 may repeatedly execute a cycle (steps S1010 to S1070 ) for executing the GC procedure in stages. In each batch, the processing unit 133 first determines whether there is a host write command that needs to be processed immediately (step S1010 ). For the determination of the host write command, reference may be made to the descriptions in Table 1, step S613 and formula (1) above, which will not be repeated for brevity. When there is a host write command that needs to be processed immediately (the "Yes" path in step S1010 ), the processing unit 133 first reads the host write command that needs to be processed immediately (step S1030 ), and then executes the first or next stage of the write command. GC operation (step S1050). When there is no host write command that needs to be processed immediately (the "No" path in step S1010 ), the GC operation of the first or next stage is directly executed (step S1050 ).

In some embodiments of step S830 or S1030, the processing unit 133 may call and execute the function HW_PushIOCmdInfoPrdInfo( ) to complete the method steps described in FIG. 6 . In other embodiments of step S830 or S1030, the H2F table writing module 450 or the GC operation module 470 may embed the program codes of the method steps described in FIG. 6 for the processing unit 133 to execute.

All or part of the steps in the method of the present invention can be implemented by a computer program, such as an operating system of a computer, a driver program of specific hardware in the computer, or a software program. In addition, other types of programs as shown above can also be implemented. Those skilled in the art can write the method of the embodiment of the present invention into a calculator program, which will not be described for the sake of brevity. The calculator program implemented by the method according to the embodiment of the present invention can be stored in a suitable computer-readable data carrier, such as DVD, CD-ROM, USB, hard disk, or can be placed on a computer that can be accessed through a network (for example, the Internet, or other suitable carrier). ) to access the web server.

Although the components described above are included in FIG. 1 , it is not excluded that more other additional components can be used to achieve better technical effects without violating the spirit of the invention. In addition, although the flowcharts in FIGS. 6 , 8 and 10 are executed in the specified order, those skilled in the art can modify the steps between these steps under the premise of achieving the same effect without violating the spirit of the invention. order, therefore, the present invention is not limited to use only the above-mentioned order. In addition, those skilled in the art can also integrate several steps into one step, or in addition to these steps, perform more steps sequentially or in parallel, and the present invention is not limited thereby.

Although the present invention is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, this invention covers modifications and similar arrangements obvious to those skilled in the art. Therefore, the scope of the claims is to be construed in the broadest manner so as to encompass all obvious modifications and similar arrangements.

Claims (16)

1. A flash memory data writing method implemented by a processing unit when loading and executing program codes of a software or firmware module, comprising:

before executing a part of logic-physical comparison table updating or garbage recycling program, judging whether a host writing instruction needing immediate processing exists in a submission queue; and

when the host write command needing immediate processing exists, the host write command is executed in a batch, and then the logic-physical comparison table updating or garbage collection program of the part is executed.

2. The method of claim 1, comprising:

when there is no host write instruction that needs immediate processing, the logical-to-physical lookup table update or garbage collection procedure for that portion is performed.

3. The method as claimed in any one of claims 1 to 2, wherein the following formula is used to determine whether the host write command requiring immediate processing exists in the delivery queue:

Tnow-Ti>Ttr

wherein Tnow represents the current time, i represents a positive integer, Ti represents the arrival time point of the ith host write instruction in the submission queue, and Tr represents a threshold value; when the condition of the formula is satisfied, it represents that the ith host write instruction in the submission queue needs to be processed immediately.

4. The method as claimed in claim 3, wherein the arrival time of each host write command in the issue queue is the time point of the last batch of host write commands when the processing unit detects that the host write command entered the issue queue.

5. The method of any of claims 1-2, wherein the partial logical-to-physical mapping table update comprises writing physical address information associated with a contiguous segment of logical addresses to the memory unit via the flash interface.

6. The method as claimed in any one of claims 1 to 2, wherein the garbage collection process is divided into a plurality of stages, and the part of the garbage collection process comprises a one-stage operation.

7. The method of claim 6, wherein the multi-stage operations comprise: determining a source address of a segment containing valid user data and a destination address of an empty physical page of an idle block or an active block; instructing a flash memory controller to read user data from the source address of a memory cell and to write the read user data to the destination address of the memory cell; updating a logic-physical comparison table; or instruct the flash memory controller to erase the data block containing the source address in the memory unit.

8. The method of any of claims 1-2, wherein performing each of the host write commands comprises retrieving the host write command from the delivery queue through a host interface; reading user data to be written into the storage unit from the random access memory through the host interface according to the address information in the host write command; storing the user data in a random access memory; and writing a completion component corresponding to the host write instruction into a completion queue through the host interface.

9. The method of any of claims 1-2, wherein performing each of the host write commands comprises retrieving the host write command from the delivery queue through a host interface; reading user data to be written into the storage unit from the random access memory through the host interface according to the address information in the host write command; writing the user data to the storage unit through a flash memory interface; and writing a completion component corresponding to the host write instruction into a completion queue through the host interface.

10. A computer-readable storage medium into which flash data is written, for storing a computer program executable by a processing unit, the computer program, when executed by the processing unit, implementing the steps of:

before executing a part of logic-physical comparison table updating or garbage recycling program, judging whether a host writing instruction needing immediate processing exists in a submission queue; and

when the host write command needing immediate processing exists, the host write command is executed in a batch, and then the logic-physical comparison table updating or garbage collection program of the part is executed.

11. The computer-readable storage medium for writing data into a flash memory of claim 10, wherein the following formula is used to determine whether the host write command requiring immediate processing exists in the delivery queue:

Tnow-Ti>Ttr

wherein Tnow represents the current time, i represents a positive integer, Ti represents the arrival time point of the ith host write instruction in the submission queue, and Tr represents a threshold value; when the condition of the formula is satisfied, it represents that the ith host write instruction in the submission queue needs to be processed immediately.

12. The computer-readable storage medium of claim 11, wherein the time of arrival of each host write command in the issue queue is a time of completion of execution of a previous batch of host write commands when the processing unit detects that the host write command entered the issue queue.

13. The computer-readable storage medium of claim 10, wherein the partial logical-to-physical mapping table update comprises writing physical address information associated with a contiguous segment of logical addresses to the memory unit via the flash interface.

14. The computer-readable storage medium of claim 10, wherein the garbage collection process is divided into a plurality of stages, and the portion of the garbage collection process comprises a stage of operation.

15. The computer-readable storage medium of any of claims 10 to 14, wherein performing each of the host write commands comprises retrieving the host write command from the delivery queue via a host interface; reading user data to be written into the storage unit from the random access memory through the host interface according to the address information in the host write command; storing the user data in a random access memory; and writing a completion component corresponding to the host write instruction into a completion queue through the host interface.

16. The computer-readable storage medium of any of claims 10 to 14, wherein performing each of the host write commands comprises retrieving the host write command from the delivery queue via a host interface; reading user data to be written into the storage unit from the random access memory through the host interface according to the address information in the host write command; writing the user data to the storage unit through a flash memory interface; and writing a completion component corresponding to the host write instruction into a completion queue through the host interface.

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