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TWI825465B - Light-emitting device - Google Patents

Light-emitting device Download PDF

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Publication number
TWI825465B
TWI825465B TW110130262A TW110130262A TWI825465B TW I825465 B TWI825465 B TW I825465B TW 110130262 A TW110130262 A TW 110130262A TW 110130262 A TW110130262 A TW 110130262A TW I825465 B TWI825465 B TW I825465B
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light
emitting unit
electrode
semiconductor
distance
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TW110130262A
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Chinese (zh)
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TW202310448A (en
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陳昭興
許啟祥
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晶元光電股份有限公司
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Priority to KR1020220069919A priority patent/KR20230026248A/en
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Publication of TWI825465B publication Critical patent/TWI825465B/en

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/81Bodies
    • H10H20/819Bodies characterised by their shape, e.g. curved or truncated substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/83Electrodes
    • H10H20/831Electrodes characterised by their shape
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/84Coatings, e.g. passivation layers or antireflective coatings
    • H10H20/841Reflective coatings, e.g. dielectric Bragg reflectors

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Abstract

A light-emitting device includes a substrate with a first surface and a second surface opposite to the first surface; and a first light-emitting unit located on the first surface of the substrate, including a first semiconductor layer and a semiconductor mesa located on the first semiconductor layer, wherein in a top view of the light-emitting device, the first semiconductor layer includes a first side and a first protrusion protruding from the first side, and the semiconductor mesa includes a second side and a second recess recessed from the second side and opposite to the first protrusion.

Description

發光元件 Light emitting element

本發明係關於一種發光元件,且特別係關於一種包含多個發光單元的發光元件。The present invention relates to a light-emitting element, and in particular to a light-emitting element including a plurality of light-emitting units.

發光二極體(Light-Emitting Diode, LED)為固態半導體發光元件,其優點為功耗低,產生的熱能低,工作壽命長,防震,體積小,反應速度快和具有良好的光電特性,例如穩定的發光波長。因此發光二極體被廣泛應用於家用電器,設備指示燈,及光電產品等。Light-Emitting Diode (LED) is a solid-state semiconductor light-emitting element. Its advantages are low power consumption, low heat energy generation, long working life, shockproof, small size, fast response speed and good optoelectronic properties, such as Stable luminescence wavelength. Therefore, light-emitting diodes are widely used in household appliances, equipment indicators, and optoelectronic products.

根據本發明之一實施例揭露一發光元件,包含一基板具有一第一表面以及一與第一表面相對之第二表面;以及一第一發光單元位於基板之第一表面上並包含一第一半導體層及一半導體台面位於第一半導體層上,其中自發光元件之一上視圖觀之,第一半導體層包含一第一側邊以及一第一凸部突出於第一側邊,半導體台面包含一第二側邊及一第二凹部凹陷於第二側邊並與第一凸部相對。According to an embodiment of the present invention, a light-emitting element is disclosed, which includes a substrate having a first surface and a second surface opposite to the first surface; and a first light-emitting unit is located on the first surface of the substrate and includes a first The semiconductor layer and a semiconductor mesa are located on the first semiconductor layer. Viewed from a top view of one of the self-luminous elements, the first semiconductor layer includes a first side and a first protrusion protruding from the first side. The semiconductor mesa includes A second side and a second concave portion are recessed in the second side and opposite to the first convex portion.

為了使本發明之敘述更加詳盡與完備,請參照下列實施例之描述並配合相關圖示。惟,以下所示之實施例係用於例示本發明之發光元件,並非將本發明限定於以下之實施例。又,本說明書記載於實施例中的構成零件之尺寸、材質、形狀、相對配置等在沒有限定之記載下,本發明之範圍並非限定於此,而僅是單純之說明而已。且各圖示所示構件之大小或位置關係等,會由於為了明確說明有加以誇大之情形。更且,於以下之描述中,為了適切省略詳細說明,對於同一或同性質之構件用同一名稱、符號顯示。In order to make the description of the present invention more detailed and complete, please refer to the description of the following embodiments and the relevant illustrations. However, the embodiments shown below are used to illustrate the light-emitting element of the present invention, and the present invention is not limited to the following embodiments. In addition, the size, material, shape, relative arrangement, etc. of the constituent parts described in the embodiments described in this specification are not described as limiting, and the scope of the present invention is not limited thereto, but is merely explained. In addition, the size and positional relationship of components shown in each diagram may be exaggerated for clear explanation. Moreover, in the following description, in order to omit detailed explanation appropriately, components of the same or similar nature are shown with the same names and symbols.

第1圖係本發明一實施例所揭示之一發光元件1的上視圖。第2圖係沿著第1圖之切線Y-Y’的發光元件1的剖面圖。第3圖係第1圖之位置Ⅰ的部分放大圖。第4圖係本發明一實施例所揭示之一發光元件2的上視圖。第5圖係沿著第4圖之切線Y-Y’的發光元件2的剖面圖。第6圖係第4圖之位置Ⅱ的部分放大圖。Figure 1 is a top view of a light-emitting element 1 disclosed in an embodiment of the present invention. Figure 2 is a cross-sectional view of the light-emitting element 1 taken along the tangent line Y-Y' in Figure 1. Figure 3 is a partially enlarged view of position I of Figure 1. Figure 4 is a top view of a light-emitting element 2 disclosed in an embodiment of the present invention. Figure 5 is a cross-sectional view of the light-emitting element 2 taken along the tangent line Y-Y' in Figure 4. Figure 6 is a partially enlarged view of position II of Figure 4.

發光元件1或2可為具有較小的水平面積的小型發光二極體晶片,至少任一邊具有一長度小於或等於200μm,但大於80μm。例如具有230μm×180μm或150μm×90μm的尺寸。然而,實施例的發光元件1或2的橫長及縱長並不限定於上述內容。並且,發光元件1或2可為具有較薄的厚度的小型發光二極體晶片。發光元件1或2可具有約100μm以下的厚度,較佳具有約40μm以上且90μm以下的厚度。發光元件1或2能夠以7mA/mm 2以上且250mA/mm 2以下的電流密度驅動。本實施例的發光元件1或2可應用到小型或薄型的各種發光裝置。 The light-emitting element 1 or 2 may be a small light-emitting diode chip with a small horizontal area, and at least any side has a length less than or equal to 200 μm but greater than 80 μm. For example, it has dimensions of 230 μm×180 μm or 150 μm×90 μm. However, the horizontal length and vertical length of the light-emitting element 1 or 2 of the embodiment are not limited to the above contents. Furthermore, the light-emitting element 1 or 2 may be a small-sized light-emitting diode chip with a thin thickness. The light-emitting element 1 or 2 may have a thickness of about 100 μm or less, and preferably has a thickness of about 40 μm or more and 90 μm or less. The light-emitting element 1 or 2 can be driven at a current density of 7 mA/mm 2 or more and 250 mA/mm 2 or less. The light-emitting element 1 or 2 of this embodiment can be applied to various small or thin light-emitting devices.

如第1圖~第2圖及第4圖~第5圖所示,發光元件1或2包含一基板10。基板10具有一第一表面100及一與第一表面100相對之第二表面110。複數個發光單元1a,1b藉由一溝渠1000相互隔開的形成在基板10之第一表面100上。本發明之實施例雖以兩個發光單元1a,1b進行例示性的說明,但本發明之發光元件1或2所包含的發光單元的數量並不限定於兩個。As shown in Figures 1 to 2 and Figures 4 to 5, the light-emitting element 1 or 2 includes a substrate 10. The substrate 10 has a first surface 100 and a second surface 110 opposite to the first surface 100 . A plurality of light-emitting units 1a, 1b are formed on the first surface 100 of the substrate 10 and are separated from each other by a trench 1000. Although the embodiment of the present invention is illustrated with two light-emitting units 1a and 1b, the number of light-emitting units included in the light-emitting element 1 or 2 of the present invention is not limited to two.

如第1圖及第4圖所示,溝渠1000使發光單元1a,1b彼此分離。據此,基板10的第一表面100暴露於溝渠1000。溝渠1000可通過微影及蝕刻製程而形成。發光單元1a,1b隔著溝渠1000而彼此相向。如第2圖或第5圖所示,第一發光單元1b以及第二發光單元1a分別包含一半導體疊層20b,20a。半導體疊層20b,20a各包含一第一半導體層21b,21a,一第二半導體層22a,22b,及一活性層23a,23b,其中活性層23a,23b係分別位於第一半導體層21a,21b及第二半導體層22a,22b之間。彼此相向的發光單元1a,1b的側面被定義為內側面,除此之外的側面被定義為外側面。第一發光單元1b的第一半導體層21b及第二發光單元1a的第一半導體層21a也分別包括內側面及外側面。例如,第一半導體層21a,21b分別包含一個內側面20a1,20b1及三個外側面20a2,20b2。如第2圖或第5圖所示,第一半導體層21a,21b的外側面20a2,20b2及內側面20a1,20b1可以是傾斜的。但是本發明並不限定於此,也可以是僅有鄰近溝渠1000的內側面20a1,20b1相對地傾斜,外側面20a2,20b2可以與基板10的側面10s對齊。例如,第一半導體層21a,21b的外側面20a2,20b2可以通過與基板10一同劃線而形成。相較內側面20a1,20b1,外側面20a2,20b2較陡峭,例如呈垂直基板10之第一表面100之一垂直面。As shown in Figures 1 and 4, the trench 1000 separates the light-emitting units 1a and 1b from each other. Accordingly, the first surface 100 of the substrate 10 is exposed to the trench 1000 . The trench 1000 can be formed through photolithography and etching processes. The light-emitting units 1a and 1b face each other across the trench 1000. As shown in Figure 2 or Figure 5, the first light-emitting unit 1b and the second light-emitting unit 1a respectively include a semiconductor stack 20b, 20a. The semiconductor stacks 20b, 20a each include a first semiconductor layer 21b, 21a, a second semiconductor layer 22a, 22b, and an active layer 23a, 23b, wherein the active layers 23a, 23b are respectively located on the first semiconductor layer 21a, 21b. and between the second semiconductor layers 22a and 22b. The side surfaces of the light-emitting units 1a and 1b facing each other are defined as inner side surfaces, and the other side surfaces are defined as outer side surfaces. The first semiconductor layer 21b of the first light-emitting unit 1b and the first semiconductor layer 21a of the second light-emitting unit 1a also include an inner side and an outer side respectively. For example, the first semiconductor layers 21a and 21b respectively include one inner side surface 20a1 and 20b1 and three outer side surfaces 20a2 and 20b2. As shown in FIG. 2 or FIG. 5 , the outer side surfaces 20a2 and 20b2 and the inner side surfaces 20a1 and 20b1 of the first semiconductor layers 21a and 21b may be inclined. However, the present invention is not limited to this. Only the inner side surfaces 20a1 and 20b1 adjacent to the trench 1000 may be relatively inclined, and the outer side surfaces 20a2 and 20b2 may be aligned with the side surface 10s of the substrate 10 . For example, the outer side surfaces 20a2 and 20b2 of the first semiconductor layers 21a and 21b may be formed by scribing together with the substrate 10. Compared with the inner side surfaces 20a1 and 20b1, the outer side surfaces 20a2 and 20b2 are steeper, for example, they are vertical surfaces perpendicular to the first surface 100 of the substrate 10.

如第1圖或第4圖所示,在第一發光單元1b以及第二發光單元1a的周邊露出基板10的第一表面100。第一發光單元1b以及第二發光單元1a的周邊所露出的區域稱為分離區域ISO。發光元件1或2具有一第一邊11以及一與第一邊11相接之第二邊12。第7圖係第1圖之位置Ⅲ或第4圖之位置Ⅲ的部分上視圖。如第7圖所示,分離區域ISO於第一邊11上具有一第一距離d1,分離區域ISO於第二邊12上具有一第二距離d2,且第一距離d1與第二距離d2具有不同的寬度。第一距離d1、第二距離d2包含一寬度介於1μm~50μm之間,較佳小於30μm,更佳小於15μm。於一實施例中,第一距離d1包含一寬度介於1μm~30μm之間,較佳介於3μm~20μm之間,更佳介於5μm~15μm之間。第二距離d2包含一寬度介於0.5μm~20μm之間,較佳介於2μm~12μm之間,更佳介於3μm~9μm之間。As shown in FIG. 1 or 4 , the first surface 100 of the substrate 10 is exposed around the first light-emitting unit 1 b and the second light-emitting unit 1 a. The exposed area around the first light-emitting unit 1b and the second light-emitting unit 1a is called an isolation area ISO. The light-emitting element 1 or 2 has a first side 11 and a second side 12 connected to the first side 11 . Figure 7 is a partial top view of position III in Figure 1 or position III in Figure 4. As shown in Figure 7, the separation area ISO has a first distance d1 on the first side 11, the separation area ISO has a second distance d2 on the second side 12, and the first distance d1 and the second distance d2 have Different widths. The first distance d1 and the second distance d2 include a width between 1 μm and 50 μm, preferably less than 30 μm, and more preferably less than 15 μm. In one embodiment, the first distance d1 includes a width between 1 μm and 30 μm, preferably between 3 μm and 20 μm, and more preferably between 5 μm and 15 μm. The second distance d2 includes a width between 0.5 μm and 20 μm, preferably between 2 μm and 12 μm, and more preferably between 3 μm and 9 μm.

如第2圖或第5圖所示,藉由乾蝕刻或濕蝕刻以將半導體疊層20a,20b的邊緣部分蝕刻而露出第一半導體層21a,21b。蝕刻後剩餘下來的部分構成半導體台面20ma,20mb設置於第一半導體層21a,21b上。半導體台面20ma,20mb可以限定位於被第一半導體層21a,21b包圍的內側。半導體台面20ma,20mb包含第二半導體層22a,22b,及活性層23a,23b,其中活性層23a,23b係分別位於第一半導體層21a,21b及第二半導體層22a,22b之間。As shown in FIG. 2 or FIG. 5 , the edge portions of the semiconductor stacks 20 a and 20 b are etched by dry etching or wet etching to expose the first semiconductor layers 21 a and 21 b. The remaining portions after etching constitute semiconductor mesas 20ma and 20mb, which are disposed on the first semiconductor layers 21a and 21b. The semiconductor mesas 20ma, 20mb may be defined on the inside surrounded by the first semiconductor layers 21a, 21b. The semiconductor mesas 20ma, 20mb include second semiconductor layers 22a, 22b, and active layers 23a, 23b, where the active layers 23a, 23b are respectively located between the first semiconductor layers 21a, 21b and the second semiconductor layers 22a, 22b.

半導體台面20ma可以包含貫通第二半導體層22a及活性層23a的通孔200。如第1圖所示,在半導體台面20ma可以形成有多個通孔200,然而也可以如第4圖所示地形成有單一的通孔200。於俯視圖下,通孔200可以為長條形狀,橢圓形,或圓形。The semiconductor mesa 20ma may include a through hole 200 penetrating the second semiconductor layer 22a and the active layer 23a. As shown in FIG. 1 , a plurality of through holes 200 may be formed on the semiconductor mesa 20ma, but a single through hole 200 may also be formed as shown in FIG. 4 . In a top view, the through hole 200 may be elongated, oval, or circular.

如第1圖或第4圖所示,位於第一發光單元1b及第二發光單元1a上的第一半導體層21b,21a於俯視圖下具有互補的形狀。具體而言,第一發光單元1b上的第一半導體層21b可以形成有向第一發光單元1b以外延伸的第一凸部210b,且第二發光單元1a上的第一半導體層21a對應地形成有向第二發光單元1a以內延伸的第一凹部210a。As shown in Figure 1 or Figure 4, the first semiconductor layers 21b and 21a located on the first light-emitting unit 1b and the second light-emitting unit 1a have complementary shapes in a top view. Specifically, the first semiconductor layer 21b on the first light-emitting unit 1b may be formed with a first protrusion 210b extending outside the first light-emitting unit 1b, and the first semiconductor layer 21a on the second light-emitting unit 1a may be formed correspondingly. There is a first recess 210a extending into the second light emitting unit 1a.

第一發光單元1b上的半導體台面20mb及第二發光單元1a上的半導體台面20ma可以各自形成有向半導體台面20mb,20ma內部延伸的第二凹部220b及第三凹部220a。第一半導體層21b,21a通過第二凹部220b及第三凹部220a而暴露出來。第二凹部220b及第三凹部220a分別向第一發光單元1b及第二發光單元1a之半導體台面20mb,20ma的內部延伸地形成,具體而言,如第1圖或第4圖所示,第二凹部220b及第三凹部220a可以從半導體台面20mb,20ma的一側邊m1,m1’朝向與其相對的另一側邊m2,m2’延伸。第二凹部220b及第三凹部220a的數量可以是一個,也可以是兩個(含)以上。設置於第一發光單元1b之第一凸部210b的數量與設置於第一發光單元1b之第二凹部220b的數量相同。設置於第一發光單元1b之第二凹部220b的數量與設置於第二發光單元1a之第三凹部220a的數量相同。The semiconductor mesa 20mb on the first light-emitting unit 1b and the semiconductor mesa 20ma on the second light-emitting unit 1a may each be formed with a second recess 220b and a third recess 220a extending toward the inside of the semiconductor mesa 20mb, 20ma. The first semiconductor layers 21b and 21a are exposed through the second recessed portion 220b and the third recessed portion 220a. The second recessed portion 220b and the third recessed portion 220a are respectively formed to extend into the inside of the semiconductor mesa 20mb, 20ma of the first light-emitting unit 1b and the second light-emitting unit 1a. Specifically, as shown in FIG. 1 or 4, The second recessed portion 220b and the third recessed portion 220a may extend from one side m1, m1' of the semiconductor mesa 20mb, 20ma toward the other opposite side m2, m2'. The number of the second recessed portion 220b and the third recessed portion 220a may be one, or two or more (inclusive). The number of the first convex portions 210b provided on the first light-emitting unit 1b is the same as the number of the second recessed portions 220b provided on the first light-emitting unit 1b. The number of the second recessed portions 220b provided in the first light-emitting unit 1b is the same as the number of the third recessed portions 220a provided in the second light-emitting unit 1a.

於本實施例中,自發光元件1或2之上視圖觀之,如第1圖或第4圖所示,於平行於發光元件1或2之第一邊11之方向上,設置於第二發光單元1a之第一凹部210a,及/或第三凹部220a分別具有一最大寬度大於設置於第一發光單元1b之第二凹部220b的最大寬度。於平行於發光元件1或2之第二邊12之方向上,設置於第一發光單元1b之第二凹部220b或設置於第二發光單元1a之第三凹部220a具有一凹陷深度不大於其各自的最大寬度。於一實施例中,第二凹部220b的凹陷深度大於第三凹部220a的凹陷深度。In this embodiment, from the top view of the light-emitting element 1 or 2, as shown in Figure 1 or Figure 4, in the direction parallel to the first side 11 of the light-emitting element 1 or 2, it is disposed on the second The first recessed portion 210a and/or the third recessed portion 220a of the light-emitting unit 1a respectively have a maximum width greater than the maximum width of the second recessed portion 220b provided in the first light-emitting unit 1b. In a direction parallel to the second side 12 of the light-emitting element 1 or 2, the second recessed portion 220b provided in the first light-emitting unit 1b or the third recessed portion 220a provided in the second light-emitting unit 1a has a recessed depth no greater than its respective depth. the maximum width. In one embodiment, the recessed depth of the second recessed portion 220b is greater than the recessed depth of the third recessed portion 220a.

第3圖係第1圖之位置Ⅰ的部分放大圖。第6圖係第4圖之位置Ⅱ的部分放大圖。如第3圖或第6圖所示,第一發光單元1b的第一半導體層21b包含一第一側邊211b,以及第一凸部210b於朝向第一發光單元1b之一外部的方向上突出於第一側邊211b。所述第一凸部210b係指第一凸部210b的兩個端點之間的假想線係位於第一半導體層21b的內部。第一發光單元1b上的半導體台面20mb包含一第二側邊222b,以及一第二凹部220b於朝向第一發光單元1b之一內部的方向上凹陷於第二側邊222b。所述第二凹部220b係指第二凹部220b上的兩個端點之間的假想線係位於半導體台面20mb的外部。於俯視圖下,第一凸部210b具有向第一發光單元1b之第一側邊211b以外突出的形狀,且第一半導體層21b之第一凸部210b的位置相應於半導體台面20mb的第二凹部220b。換言之,第一發光單元1b之第一半導體層21b的第一凸部210b與半導體台面20mb的第二凹部220b的延伸方向係相反。為了使後續製程中形成的第一電極51b達到更佳的電流分散效果,第一凸部210b包含一第一曲率半徑大於第二凹部220b之一第二曲率半徑。Figure 3 is a partially enlarged view of position I of Figure 1. Figure 6 is a partially enlarged view of position II of Figure 4. As shown in Figure 3 or Figure 6, the first semiconductor layer 21b of the first light-emitting unit 1b includes a first side 211b, and the first convex portion 210b protrudes in a direction toward the outside of the first light-emitting unit 1b. on the first side 211b. The first convex portion 210b means that the imaginary line between the two endpoints of the first convex portion 210b is located inside the first semiconductor layer 21b. The semiconductor mesa 20mb on the first light-emitting unit 1b includes a second side 222b, and a second recess 220b is recessed in the second side 222b in a direction toward the inside of the first light-emitting unit 1b. The second recessed portion 220b means that the imaginary line between the two endpoints of the second recessed portion 220b is located outside the semiconductor mesa 20mb. In a top view, the first convex portion 210b has a shape protruding out of the first side 211b of the first light-emitting unit 1b, and the position of the first convex portion 210b of the first semiconductor layer 21b corresponds to the second concave portion of the semiconductor mesa 20mb. 220b. In other words, the extending directions of the first convex portion 210b of the first semiconductor layer 21b of the first light-emitting unit 1b and the second recessed portion 220b of the semiconductor mesa 20mb are opposite. In order to achieve a better current dispersion effect for the first electrode 51b formed in the subsequent process, the first convex portion 210b includes a first curvature radius larger than a second curvature radius of the second concave portion 220b.

如第3圖或第6圖所示,第二發光單元1a的第一半導體層21a具有向內部延伸的第一凹部210a。第二發光單元1a之第一凹部210a的形狀係互補於第一發光單元1b上的第一凸部210b的形狀,且半導體台面20ma之第三凹部220a的位置及形狀對應於第一半導體層21a之第一凹部210a的位置及形狀。As shown in FIG. 3 or FIG. 6 , the first semiconductor layer 21a of the second light emitting unit 1a has a first recess 210a extending inward. The shape of the first concave portion 210a of the second light-emitting unit 1a is complementary to the shape of the first convex portion 210b on the first light-emitting unit 1b, and the position and shape of the third concave portion 220a of the semiconductor mesa 20ma correspond to the first semiconductor layer 21a The position and shape of the first recess 210a.

具體而言,第二發光單元1a上的第一半導體層21a包含一第一側邊211a以及一第一凹部210a。於朝向第二發光單元1a之一內部的方向上,第一凹部210a凹陷於第一側邊211a並與第一發光單元1b上的第一凸部210b相對。第二發光單元1a上的半導體台面20ma包含一第二側邊222a,以及一第三凹部220a凹陷於第二側邊222a並與第一發光單元1b上的第一凸部210b相對。Specifically, the first semiconductor layer 21a on the second light-emitting unit 1a includes a first side 211a and a first recess 210a. In the direction toward the inside of the second light-emitting unit 1a, the first recessed portion 210a is recessed in the first side 211a and is opposite to the first convex portion 210b on the first light-emitting unit 1b. The semiconductor mesa 20ma on the second light-emitting unit 1a includes a second side 222a, and a third recessed portion 220a is recessed in the second side 222a and faces the first convex portion 210b on the first light-emitting unit 1b.

兩相鄰發光單元1a,1b之半導體台面20ma,20mb的第三凹部220a及第二凹部220b的位置係相互對應。隨著第一凸部210b及第二凹部220b的數量增加,於後續製程中形成於第一凸部210b之第一電極51b的數量也增加,從而改善電流分散性能。第1圖例示了第一發光單元1b包含兩個第一凸部210b且第二發光單元1a包含兩個第一凹部210a。第4圖例示了第一發光單元1b包含一個第一凸部210b且第二發光單元1a包含一個第一凹部210a。The positions of the third recessed portion 220a and the second recessed portion 220b of the semiconductor mesas 20ma and 20mb of the two adjacent light-emitting units 1a and 1b correspond to each other. As the number of the first convex portions 210b and the second recessed portions 220b increases, the number of the first electrodes 51b formed on the first convex portions 210b in subsequent processes also increases, thereby improving the current dispersion performance. Figure 1 illustrates that the first light-emitting unit 1b includes two first convex portions 210b and the second light-emitting unit 1a includes two first concave portions 210a. Figure 4 illustrates that the first light-emitting unit 1b includes a first convex portion 210b and the second light-emitting unit 1a includes a first concave portion 210a.

第3圖例示的發光元件1之部分與第6圖例示的發光元件2之部分大體相似,主要的差異在於發光元件1之第一發光單元1b的第一半導體層21b的第一側邊211b與第二發光單元1a的第一半導體層21b的第一側邊211a之間的間距大致相同於第一凸部210b與第一凹部210a之間的間距,以至於發光元件1的溝渠1000於俯視圖下具有等間距的寬度S。如第6圖所示,發光元件2之第一發光單元1b的第一半導體層21b的第一側邊211b與第二發光單元1a的第一半導體層21a的第一側邊211a之間的間距不同於第一凸部210b與第一凹部210a之間的間距,以至於發光元件2的溝渠1000於俯視圖下具有不同間距的寬度S1及S2。具體而言,發光元件2之第一發光單元1b的第一凸部210b與第二發光單元1a的第一凹部210a之間具有第一間距S1。發光元件2之第一發光單元1b的第一半導體層21b的第一側邊211b與第二發光單元1a的第一半導體層21a的第一側邊211a之間具有第二間距S2。於本實施例中,第一間距S1可大於或小於第二間距S2。The part of the light-emitting element 1 illustrated in Figure 3 is generally similar to the part of the light-emitting element 2 illustrated in Figure 6. The main difference lies in the first side 211b of the first semiconductor layer 21b of the first light-emitting unit 1b of the light-emitting element 1. The distance between the first side edges 211a of the first semiconductor layer 21b of the second light-emitting unit 1a is substantially the same as the distance between the first convex part 210b and the first recessed part 210a, so that the trench 1000 of the light-emitting element 1 is in a top view. Have equally spaced width S. As shown in Figure 6, the distance between the first side 211b of the first semiconductor layer 21b of the first light-emitting unit 1b of the light-emitting element 2 and the first side 211a of the first semiconductor layer 21a of the second light-emitting unit 1a The distance between the first convex part 210b and the first recessed part 210a is different, so that the trench 1000 of the light-emitting element 2 has widths S1 and S2 with different distances in a top view. Specifically, there is a first distance S1 between the first convex portion 210b of the first light-emitting unit 1b and the first concave portion 210a of the second light-emitting unit 1a of the light-emitting element 2. There is a second spacing S2 between the first side 211b of the first semiconductor layer 21b of the first light-emitting unit 1b of the light-emitting element 2 and the first side 211a of the first semiconductor layer 21a of the second light-emitting unit 1a. In this embodiment, the first distance S1 may be larger or smaller than the second distance S2.

基板10可以為一成長基板以磊晶成長半導體疊層20a,20b。基板10包括用以磊晶成長磷化鋁鎵銦(AlGaInP)之砷化鎵(GaAs)晶圓,或用以成長氮化鎵(GaN)、氮化銦鎵(InGaN)、或氮化鋁鎵(AlGaN)之藍寶石(Al 2O 3)晶圓、氮化鎵(GaN)晶圓、碳化矽(SiC)晶圓、或氮化鋁(AlN)晶圓。 The substrate 10 may be a growth substrate for epitaxially growing the semiconductor stacks 20a, 20b. The substrate 10 includes a gallium arsenide (GaAs) wafer for epitaxial growth of aluminum gallium indium phosphide (AlGaInP), or for the growth of gallium nitride (GaN), indium gallium nitride (InGaN), or aluminum gallium nitride. (AlGaN) sapphire (Al 2 O 3 ) wafer, gallium nitride (GaN) wafer, silicon carbide (SiC) wafer, or aluminum nitride (AlN) wafer.

基板10與半導體疊層20a,20b相接的第一表面100可以為粗糙化的表面。粗糙化的表面可以為具有不規則形態的表面或具有規則形態的表面。相對於基板10的第一表面100,基板10包含複數個凸部(圖未示)突出於第一表面100或是複數個凹部(圖未示)凹陷於(圖未示)。於一剖面圖下,凸部或凹部可以為半球形狀或者多邊錐形狀。The first surface 100 of the substrate 10 connecting the semiconductor stacks 20a, 20b may be a roughened surface. The roughened surface may be a surface with irregular morphology or a surface with regular morphology. Relative to the first surface 100 of the substrate 10 , the substrate 10 includes a plurality of convex portions (not shown) protruding from the first surface 100 or a plurality of recessed portions (not shown) recessed in the first surface 100 (not shown). In a cross-sectional view, the convex part or the concave part may be in the shape of a hemisphere or a polygonal cone.

於本發明之一實施例中,藉由金屬有機化學氣相沉積法(MOCVD)、分子束磊晶(MBE)、氫化物氣相沉積法(HVPE)、物理氣相沉積法(PVD)或離子電鍍方法以於基板10上形成具有光電特性之半導體疊層20a,20b,例如發光(light-emitting)疊層,其中物理氣象沉積法包含濺鍍 (Sputtering)或蒸鍍(Evaporation)法。In one embodiment of the present invention, metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), physical vapor deposition (PVD) or ion The electroplating method is used to form semiconductor stacks 20a, 20b with optoelectronic properties, such as light-emitting stacks, on the substrate 10. The physical vapor deposition method includes sputtering or evaporation.

藉由改變半導體疊層20a,20b中一層或多層的物理及化學組成以調整發光元件1或2發出光線的波長。半導體疊層20a,20b之材料包含Ⅲ-Ⅴ族半導體材料,例如Al xIn yGa (1-x-y)N或Al xIn yGa (1-x-y)P,其中0≦x,y≦1;(x+y)≦1。當半導體疊層20a,20b之材料為AlInGaP系列材料時,可發出波長介於610 nm及650 nm之間的紅光。當半導體疊層20a,20b之材料為InGaN系列材料時,可發出波長介於400 nm及490 nm之間的藍光,波長介於490 nm及500 nm之間的青色光,或波長介於500 nm及570 nm之間的綠光。當半導體疊層20a,20b之材料為AlGaN系列或AlInGaN系列材料時,可發出波長介於250 nm及400 nm之間的紫外光。 The wavelength of light emitted by the light-emitting element 1 or 2 is adjusted by changing the physical and chemical composition of one or more layers in the semiconductor stack 20a, 20b. The materials of the semiconductor stacks 20a and 20b include III-V group semiconductor materials, such as Al x In y Ga (1-xy) N or Al x In y Ga (1-xy) P, where 0≦x, y≦1; (x+y)≦1. When the material of the semiconductor stack 20a and 20b is an AlInGaP series material, it can emit red light with a wavelength between 610 nm and 650 nm. When the semiconductor stack 20a, 20b is made of InGaN series materials, it can emit blue light with a wavelength between 400 nm and 490 nm, cyan light with a wavelength between 490 nm and 500 nm, or a wavelength between 500 nm. and green light between 570 nm. When the materials of the semiconductor stacks 20a and 20b are AlGaN series or AlInGaN series materials, ultraviolet light with a wavelength between 250 nm and 400 nm can be emitted.

第一半導體層21a,21b和第二半導體層22a,22b可為包覆層(cladding layer)或侷限層(confinement layer),兩者具有不同的導電型態、電性、極性,或依摻雜的元素以提供電子或電洞,例如第一半導體層21a,21b為n型電性的半導體,第二半導體層22a,22b為p型電性的半導體。活性層23a,23b分別形成在第一半導體層21a,21b和第二半導體層22a,22b之間,電子與電洞於一電流驅動下在活性層23a,23b複合,將電能轉換成光能,以發出一光線。活性層23a,23b可為單異質結構(single heterostructure, SH),雙異質結構(double heterostructure, DH),雙側雙異質結構(double-side double heterostructure, DDH),或是多層量子井結構(multi-quantum well, MQW)。活性層23a,23b之材料可為中性、p型或n型電性的半導體。第一半導體層21a,21b、第二半導體層22a,22b、或活性層23a,23b可為一單層或包含複數子層的結構。The first semiconductor layers 21a, 21b and the second semiconductor layers 22a, 22b can be cladding layers or confinement layers, and they have different conductive types, electrical properties, polarities, or doping. elements to provide electrons or holes. For example, the first semiconductor layers 21a and 21b are n-type semiconductors, and the second semiconductor layers 22a and 22b are p-type semiconductors. Active layers 23a and 23b are respectively formed between the first semiconductor layers 21a and 21b and the second semiconductor layers 22a and 22b. Electrons and holes recombine in the active layers 23a and 23b driven by a current to convert electrical energy into light energy. to emit a light. The active layers 23a and 23b can be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-layer quantum well structure (multi -quantum well, MQW). The material of the active layers 23a and 23b can be a neutral, p-type or n-type electrical semiconductor. The first semiconductor layer 21a, 21b, the second semiconductor layer 22a, 22b, or the active layer 23a, 23b may be a single layer or a structure including a plurality of sub-layers.

於本發明之一實施例中,半導體疊層20a,20b還可包含一緩衝層(圖未示)位於第一半導體層21a,21b和基板10之間,用以釋放基板10和半導體疊層20a,20b之間因材料晶格不匹配而產生的應力,以減少差排及晶格缺陷,進而提升磊晶品質。緩衝層可為一單層或包含複數子層的結構。於一實施例中,可選用PVD氮化鋁(AlN)做為緩衝層,形成於半導體疊層20a,20b及基板10之間,用以改善半導體疊層20a,20b的磊晶品質。在一實施例中,用以形成PVD氮化鋁(AlN)的靶材係由氮化鋁所組成。在另一實施例中,可使用由鋁組成的靶材,於氮源的環境下與鋁靶材反應性地形成氮化鋁。In one embodiment of the present invention, the semiconductor stack 20a, 20b may further include a buffer layer (not shown) between the first semiconductor layer 21a, 21b and the substrate 10 to release the substrate 10 and the semiconductor stack 20a. , the stress caused by the material lattice mismatch between 20b to reduce misalignment and lattice defects, thereby improving the epitaxial quality. The buffer layer may be a single layer or a structure including multiple sub-layers. In one embodiment, PVD aluminum nitride (AlN) can be used as a buffer layer formed between the semiconductor stacks 20a, 20b and the substrate 10 to improve the epitaxial quality of the semiconductor stacks 20a, 20b. In one embodiment, the target used to form PVD aluminum nitride (AlN) is composed of aluminum nitride. In another embodiment, a target composed of aluminum can be used, and aluminum nitride can be formed by reacting with the aluminum target in a nitrogen source environment.

如第1圖~第2圖及第4圖~第5圖所示,接觸電極40b,40a分別設置於第一發光單元1b及第二發光單元1a的第二半導體層22b,22a上,並且電連接於第一發光單元1b及第二發光單元1a的第二半導體層22a,22b。接觸電極40a,40b可以幾乎覆蓋第二半導體層22a,22b的全部區域,也可以與半導體台面20m的邊緣相隔一距離。例如,接觸電極40a,40b可以覆蓋第二半導體層22a,22b的80%以上,更佳可以覆蓋90%以上。為了防止水氣從發光單元1a,1b的側壁或基板10的邊緣流入而造成損傷,相對於半導體台面20m的邊緣,接觸電極40a,40b的邊緣部位可設置於發光單元1a,1b的內側。接觸電極40a,40b可以各包含具有反射性的金屬層,以將在活性層23a,23b生成而向接觸電極40a,40b行進的光向基板10之第二表面110反射。於一實施例中,接觸電極40a,40b可以形成為單一反射金屬層,例如Ag或Al。然而並不局限於此,接觸電極40a,40b也可以包含透明氧化物層以作為歐姆接觸層。為了減少接觸電阻並提高電流擴散的效率,透明氧化物層之材料包含對於活性層23a,23b所發出的光線為透明的材料。接觸電極40a,40b包含氧化銦錫(Indium Tin Oxide,ITO)、氧化鋅(Zinc Oxide,ZnO)、氧化鋅銦錫(Zinc Indium TinOxide,ZITO)、氧化銦鋅(Zinc Indium Oxide,ZIO)、氧化鋅錫(Zinc Tin Oxide,ZTO)、氧化鎵銦錫(Gallium Indium Tin Oxide,GITO)、氧化銦鎵(Gallium Indium Oxide,GIO)、氧化鋅鎵(Gallium Zinc Oxide,GZO)、鋁摻雜氧化鋅(Aluminum doped Zinc Oxide,AZO)、氟摻雜氧化錫(Fluorine Tin Oxide,FTO)等的透光性導電氧化物、及如鋁(Al)、鎳(Ni)、金(Au)等具有厚度小於500埃之的透光性金屬層中的至少一種。所述透光性導電性氧化物還可包括各種摻雜劑。As shown in Figures 1 to 2 and Figures 4 to 5, contact electrodes 40b and 40a are respectively provided on the second semiconductor layers 22b and 22a of the first light-emitting unit 1b and the second light-emitting unit 1a, and are electrically The second semiconductor layers 22a and 22b are connected to the first light-emitting unit 1b and the second light-emitting unit 1a. The contact electrodes 40a, 40b may cover almost the entire area of the second semiconductor layer 22a, 22b, or may be spaced apart from the edge of the semiconductor mesa 20m. For example, the contact electrodes 40a and 40b can cover more than 80% of the second semiconductor layer 22a and 22b, and more preferably can cover more than 90%. In order to prevent water vapor from flowing into the side walls of the light-emitting units 1a and 1b or the edge of the substrate 10 and causing damage, the edge portions of the contact electrodes 40a and 40b can be disposed inside the light-emitting units 1a and 1b relative to the edge of the semiconductor mesa 20m. The contact electrodes 40a and 40b may each include a reflective metal layer to reflect the light generated in the active layers 23a and 23b and traveling toward the contact electrodes 40a and 40b toward the second surface 110 of the substrate 10 . In one embodiment, the contact electrodes 40a, 40b may be formed as a single reflective metal layer, such as Ag or Al. However, it is not limited thereto. The contact electrodes 40a and 40b may also include a transparent oxide layer as an ohmic contact layer. In order to reduce contact resistance and improve current diffusion efficiency, the material of the transparent oxide layer includes a material that is transparent to the light emitted by the active layers 23a and 23b. The contact electrodes 40a, 40b include indium tin oxide (ITO), zinc oxide (Zinc Oxide, ZnO), zinc indium tin oxide (ZITO), indium zinc oxide (Zinc Indium Oxide, ZIO), oxide Zinc Tin Oxide (ZTO), Gallium Indium Tin Oxide (GITO), Gallium Indium Oxide (GIO), Gallium Zinc Oxide (GZO), aluminum-doped zinc oxide Translucent conductive oxides such as (Aluminum doped Zinc Oxide, AZO), fluorine doped tin oxide (Fluorine Tin Oxide, FTO), and aluminum (Al), nickel (Ni), gold (Au), etc. have thicknesses less than At least one of the light-transmitting metal layers with a thickness of 500 Angstroms. The light-transmissive conductive oxide may also include various dopants.

於本發明之實施例中,發光元件1或2之第一電極51b,51a及第二電極52b,52a形成於基板10之同一側。發光元件1或2可以為倒裝晶片(flip chip)結構或是正裝的水平晶片(lateral chip)結構。In the embodiment of the present invention, the first electrodes 51b, 51a and the second electrodes 52b, 52a of the light-emitting element 1 or 2 are formed on the same side of the substrate 10. The light-emitting element 1 or 2 can be a flip chip structure or a formal lateral chip structure.

如第1圖~第2圖及第4圖~第5圖所示,第一電極51b,51a分別設置於第一發光單元1b及第二發光單元1a的第一半導體層21b,21a上。第二電極52b,52a分別設置於第一發光單元1b及第二發光單元1a的第二半導體層21b,21a及/或接觸電極40b,40a上。As shown in Figures 1 to 2 and Figures 4 to 5, the first electrodes 51b and 51a are respectively provided on the first semiconductor layers 21b and 21a of the first light-emitting unit 1b and the second light-emitting unit 1a. The second electrodes 52b, 52a are respectively provided on the second semiconductor layers 21b, 21a and/or the contact electrodes 40b, 40a of the first light-emitting unit 1b and the second light-emitting unit 1a.

第一電極51b,51a及第二電極52b,52a可以在同一製程中使用相同材料而一起形成為具有相同的金屬疊層。第一電極51b,51a及第二電極52b,52a包括例如鋁(A1)層等具有高反射率的金屬,且高反射率金屬層可以在包含鈦(Ti)、鉻(Cr)或鎳(Ni)的黏結層上形成。並且,在所述具有高反射率的金屬層上可以形成鎳(Ni)、鉻(Cr)、金(Au)等的單層或複合層結構的阻障層以保護具有高反射率的金屬層並避免其表面氧化。第一電極51b,51a及第二電極52b,52a例如可以包含Cr/Al/Ni/Ti/Ni/Ti/Au/Ti的多層結構。The first electrodes 51b, 51a and the second electrodes 52b, 52a can be formed together using the same material in the same process to have the same metal stack. The first electrodes 51b, 51a and the second electrodes 52b, 52a include a metal with high reflectivity, such as an aluminum (A1) layer, and the high-reflectivity metal layer may include titanium (Ti), chromium (Cr) or nickel (Ni). ) formed on the adhesive layer. Furthermore, a barrier layer of single layer or composite layer structure of nickel (Ni), chromium (Cr), gold (Au), etc. can be formed on the metal layer with high reflectivity to protect the metal layer with high reflectivity. and avoid surface oxidation. The first electrodes 51b, 51a and the second electrodes 52b, 52a may include, for example, a multi-layer structure of Cr/Al/Ni/Ti/Ni/Ti/Au/Ti.

如第1圖~第2圖及第4圖~第5圖所示,電流阻擋層30b,30a分別設置於第二電極52b,52a及接觸電極40b,40a之間,防止電流集中到第二電極52b,52a附近,從而幫助電流的水平分散。電流阻擋層30b,30a的線寬大於第二電極52b,52a的線寬。電流阻擋層30b,30a由絕緣物質所構成,並且可以形成為單層或者是多層。例如,電流阻擋層30b,30a可以包含SiO x或SiN x,並且可以包含折射率互相不同的絕緣性材料層交互堆疊的布拉格反射鏡(DBR)。於俯視圖中,如第1圖所示,電流阻擋層30b,30a的上視圖案與第二電極52b,52a的上視圖案可以相同,或如第4圖所示,電流阻擋層30b,30a的上視圖案與第二電極52b,52a的上視圖案可以不相同。 As shown in Figures 1 to 2 and Figures 4 to 5, the current blocking layers 30b and 30a are respectively disposed between the second electrodes 52b and 52a and the contact electrodes 40b and 40a to prevent current from concentrating on the second electrode. 52b, near 52a, thus helping the horizontal dispersion of the current. The line width of the current blocking layers 30b, 30a is greater than the line width of the second electrodes 52b, 52a. The current blocking layers 30b, 30a are made of insulating material, and may be formed as a single layer or multiple layers. For example, the current blocking layers 30b, 30a may include SiOx or SiNx , and may include a Bragg reflector (DBR) in which insulating material layers with different refractive indexes are alternately stacked. In a top view, as shown in FIG. 1 , the top-view patterns of the current blocking layers 30b and 30a can be the same as the top-view patterns of the second electrodes 52b and 52a , or as shown in FIG. 4 , the top-view patterns of the current blocking layers 30b and 30a can be the same. The top view pattern may be different from the top view pattern of the second electrodes 52b, 52a.

如第2圖或第5圖所示,絕緣層60自發光單元1b,1a的周圍覆蓋第一半導體層21b,21a及半導體台面20mb,20ma的側面。絕緣層60在第一發光單元1b之第一凸部210b處局部性覆蓋第一半導體層21b並形成第一絕緣層開口601b,在第二發光單元1a之通孔200處局部性覆蓋第一半導體層21a並形成第一絕緣層開口601a。絕緣層60在第一發光單元1b之半導體台面20mb處局部性覆蓋第二半導體層22b並形成第二絕緣層開口602b,在第二發光單元1a之半導體台面20ma處局部性覆蓋第二半導體層22a並形成第二絕緣層開口602a。As shown in Figure 2 or Figure 5, the insulating layer 60 covers the first semiconductor layers 21b, 21a and the side surfaces of the semiconductor mesas 20mb, 20ma from around the light-emitting units 1b, 1a. The insulating layer 60 partially covers the first semiconductor layer 21b at the first convex portion 210b of the first light-emitting unit 1b and forms the first insulating layer opening 601b, and partially covers the first semiconductor layer at the through hole 200 of the second light-emitting unit 1a. layer 21a and form a first insulating layer opening 601a. The insulating layer 60 partially covers the second semiconductor layer 22b at the semiconductor mesa 20mb of the first light-emitting unit 1b and forms a second insulating layer opening 602b, and partially covers the second semiconductor layer 22a at the semiconductor mesa 20ma of the second light-emitting unit 1a. And the second insulation layer opening 602a is formed.

如第1圖~第2圖及第4圖~第5圖所示,第一延伸電極71及第二延伸電極72分別位於第二發光單元1a的半導體台面20ma及第一發光單元1b的半導體台面20mb上,並且分別電連接於第二發光單元1a的第一半導體層21a及第一發光單元1b的第二半導體層22b。第一延伸電極71可以藉由第一絕緣層開口601a而直接接觸第二發光單元1a的第一電極51a,第二延伸電極72可以藉由第二絕緣層開口602a而直接接觸第一發光單元1b的第二電極52b。As shown in Figures 1-2 and 4-5, the first extended electrode 71 and the second extended electrode 72 are respectively located on the semiconductor mesa 20ma of the second light-emitting unit 1a and the semiconductor mesa of the first light-emitting unit 1b. 20mb, and are electrically connected to the first semiconductor layer 21a of the second light-emitting unit 1a and the second semiconductor layer 22b of the first light-emitting unit 1b respectively. The first extended electrode 71 can directly contact the first electrode 51a of the second light-emitting unit 1a through the first insulating layer opening 601a, and the second extended electrode 72 can directly contact the first light-emitting unit 1b through the second insulating layer opening 602a. second electrode 52b.

絕緣層60設置於第一電極51b,51a、第二電極52b,52a及第一延伸電極71、第二延伸電極72之間,並且包含第一絕緣層開口601b,601a以分別露出第一電極51b,51a以及第二絕緣層開口602b,602a以分別露出第二電極52b,52a。如第1圖或第4圖所示,絕緣層60的第一絕緣層開口601b使位於第一發光單元1b之第一凸部210b處的第一電極51b暴露出來,絕緣層60的第二絕緣層開口601a使位於第二發光單元1a之通孔200處的第一電極51a暴露出來。如第2圖或第5圖所示,第一延伸電極71藉由第一絕緣層開口601a而接觸第一電極51a並電連接至第二發光單元1a的第一半導體層21a。第二延伸電極72藉由第二絕緣層開口602b而接觸第二電極52b並電連接至第一發光單元1b的第二半導體層22b。The insulating layer 60 is disposed between the first electrodes 51b, 51a, the second electrodes 52b, 52a, the first extended electrodes 71, and the second extended electrodes 72, and includes first insulating layer openings 601b, 601a to expose the first electrodes 51b respectively. , 51a and the second insulating layer openings 602b, 602a to expose the second electrodes 52b, 52a respectively. As shown in Figure 1 or Figure 4, the first insulation layer opening 601b of the insulation layer 60 exposes the first electrode 51b located at the first protrusion 210b of the first light-emitting unit 1b, and the second insulation layer of the insulation layer 60 The layer opening 601a exposes the first electrode 51a located at the through hole 200 of the second light emitting unit 1a. As shown in FIG. 2 or FIG. 5 , the first extended electrode 71 contacts the first electrode 51 a through the first insulating layer opening 601 a and is electrically connected to the first semiconductor layer 21 a of the second light-emitting unit 1 a. The second extended electrode 72 contacts the second electrode 52b through the second insulating layer opening 602b and is electrically connected to the second semiconductor layer 22b of the first light emitting unit 1b.

如第1圖~第2圖及第4圖~第5圖所示,連接電極70局部性地覆蓋第一發光單元1b,第二發光單元1a,以及溝渠1000。連接電極70包括位於第一發光單元1b之第一凸部210b上並與第一發光單元1b之第一電極51b接觸的第一連接部702,位於第二發光單元1a之半導體台面20ma上並與第二發光單元1a之第二電極52a接觸的第二連接部701,以及位於溝渠1000上的跨橋部700。As shown in Figures 1 to 2 and Figures 4 to 5, the connection electrode 70 partially covers the first light-emitting unit 1b, the second light-emitting unit 1a, and the trench 1000. The connection electrode 70 includes a first connection portion 702 located on the first protrusion 210b of the first light-emitting unit 1b and in contact with the first electrode 51b of the first light-emitting unit 1b, and located on the semiconductor mesa 20ma of the second light-emitting unit 1a and in contact with The second connection portion 701 contacted by the second electrode 52a of the second light-emitting unit 1a, and the bridge portion 700 located on the trench 1000.

為了連接相鄰的發光單元1a,1b,如第3圖及第6圖所示,連接電極70之跨橋部700跨越溝渠1000並覆蓋相鄰的發光單元1a,1b之第一半導體層21a,21b的第一側邊211a,211b。即,在本實施例中,各個發光單元1a,1b的半導體疊層20b,20a具有四個邊緣部位,但是連接電極70僅覆蓋這些邊緣部位中的一個。In order to connect the adjacent light-emitting units 1a and 1b, as shown in Figures 3 and 6, the bridge portion 700 of the connecting electrode 70 spans the trench 1000 and covers the first semiconductor layer 21a of the adjacent light-emitting units 1a and 1b, The first side 211a, 211b of 21b. That is, in this embodiment, the semiconductor stack 20b, 20a of each light-emitting unit 1a, 1b has four edge portions, but the connection electrode 70 only covers one of these edge portions.

第1圖的連接電極70例示了第一連接部702覆蓋兩個第一電極51b,然而第一連接部702也可以如第4圖所示的覆蓋一個第一電極51b或是三個以上的第一電極51b (圖未示)。根據一實施例,如第1圖或第4圖所示,與第二連接部701相接觸的第二電極52a的數量大於與第一連接部702相接觸的第一電極51b的數量。增加連接電極70與第一電極51b及第二電極52a相接觸的數量可以改善發光元件1或2的電流分散。連接電極70通過第一絕緣層開口601b而與第一發光單元1b上的第一電極51b電連接,並且可以通過第二發光單元1a的第二絕緣層開口602a而與第二發光單元1a的第二電極52a電連接。因此,第一發光單元1b及第二發光單元1a通過連接電極70而彼此電性串聯連接。The connection electrode 70 in Figure 1 illustrates that the first connection part 702 covers two first electrodes 51b. However, the first connection part 702 can also cover one first electrode 51b or three or more first electrodes 51b as shown in Figure 4. An electrode 51b (not shown). According to an embodiment, as shown in FIG. 1 or FIG. 4 , the number of second electrodes 52 a in contact with the second connection part 701 is greater than the number of first electrodes 51 b in contact with the first connection part 702 . Increasing the number of connecting electrodes 70 in contact with the first electrode 51b and the second electrode 52a can improve the current dispersion of the light emitting element 1 or 2. The connection electrode 70 is electrically connected to the first electrode 51b on the first light-emitting unit 1b through the first insulating layer opening 601b, and may be connected to the second light-emitting unit 1a through the second insulating layer opening 602a of the second light-emitting unit 1a. The two electrodes 52a are electrically connected. Therefore, the first light-emitting unit 1 b and the second light-emitting unit 1 a are electrically connected to each other in series through the connecting electrode 70 .

根據一實施例,在俯視時,如第3圖及第6圖所示,連接電極70的第一連接部702覆蓋第一發光單元1b之半導體台面20mb及第一凸部210b,並具有相對應於第二凹部220b的形狀。具體而言,第一連接部702包含一第一連接部平邊7021,以及一第一連接凸部7022突出於第一連接部平邊7021。第一連接凸部7022之形成位置及/或形狀係相應於第一發光單元1b之半導體台面20mb的第二凹部220b。第二連接部701包含一第二連接部平邊7011不平行於第二發光單元1a之半導體台面20ma的第三凹部220a。第一連接部702之第一連接部平邊7021可大致平行於第二連接部701之第二連接部平邊7011。According to an embodiment, when viewed from above, as shown in Figures 3 and 6, the first connection portion 702 of the connection electrode 70 covers the semiconductor mesa 20mb and the first convex portion 210b of the first light-emitting unit 1b, and has corresponding in the shape of the second recess 220b. Specifically, the first connecting portion 702 includes a first connecting portion flat side 7021, and a first connecting protrusion 7022 protruding from the first connecting portion flat side 7021. The formation position and/or shape of the first connection protrusion 7022 corresponds to the second recess 220b of the semiconductor mesa 20mb of the first light-emitting unit 1b. The second connection portion 701 includes a third recess 220a whose flat side 7011 is not parallel to the semiconductor mesa 20ma of the second light-emitting unit 1a. The first connecting portion flat edge 7021 of the first connecting portion 702 may be substantially parallel to the second connecting portion flat edge 7011 of the second connecting portion 701 .

根據一實施例,在俯視時,如第1圖及第4圖所示,複數個第二電極52a,52b係設置於第二凹部220a,220b之兩相對側以分散電流。According to an embodiment, when viewed from above, as shown in Figures 1 and 4, a plurality of second electrodes 52a, 52b are disposed on two opposite sides of the second recesses 220a, 220b to disperse the current.

第一絕緣層開口601a,601b以及第二絕緣層開口602a,602b的數目可以為一個,然而並不局限於此,也可以為多個。第一絕緣層開口601a,601b以及第二絕緣層開口602a,602b的數目依第一電極51b,51a及第二電極52b,52a的數目而定以電性連接第一電極51a,51b,第二電極52a,52b,連接電極70,第一延伸電極71,以及第二延伸電極72。The number of the first insulating layer opening 601a, 601b and the second insulating layer opening 602a, 602b may be one, but is not limited thereto, and may also be multiple. The number of the first insulating layer openings 601a, 601b and the second insulating layer openings 602a, 602b depends on the number of the first electrodes 51b, 51a and the second electrodes 52b, 52a to electrically connect the first electrodes 51a, 51b, the second Electrodes 52a, 52b, connection electrode 70, first extension electrode 71, and second extension electrode 72.

如第3圖及第6圖所示,第一電極51b與第一凸部210b之間具有一第一間距D1,第一電極51b與第二凹部220b具有一第二間距D2,且第一間距D1大於第二間距D2。於另一實施例中,第一間距D1小於或大致相同於第二間距D2。第一電極51b包含一直徑或一寬度大於或等於第一間距D1,及/或大於或等於第二間距D2。第一電極51b之一半徑R可以小於或等於第一間距D1。第一側邊211b與第二側邊222b之間具有一第三間距D3,第三間距D3小於或等於第一間距D1,及/或第三間距D3大於或等於第二間距D2。於本實施例中,第三間距D3大於第二間距D2但小於第一間距D1。如第3圖所示,溝渠1000之間距S小於第一間距D1,第二間距D2,及/或第三間距D3。如第6圖所示,溝渠1000之間距S1或S2小於第一間距D1及/或第三間距D3,但大於、小於或等於第二間距D2。As shown in Figures 3 and 6, there is a first distance D1 between the first electrode 51b and the first protrusion 210b, a second distance D2 between the first electrode 51b and the second recess 220b, and the first distance D1 is greater than the second distance D2. In another embodiment, the first distance D1 is smaller than or substantially the same as the second distance D2. The first electrode 51b includes a diameter or a width greater than or equal to the first pitch D1, and/or greater than or equal to the second pitch D2. A radius R of the first electrode 51b may be less than or equal to the first distance D1. There is a third distance D3 between the first side 211b and the second side 222b. The third distance D3 is less than or equal to the first distance D1, and/or the third distance D3 is greater than or equal to the second distance D2. In this embodiment, the third distance D3 is larger than the second distance D2 but smaller than the first distance D1. As shown in FIG. 3 , the distance S between the trenches 1000 is smaller than the first distance D1 , the second distance D2 , and/or the third distance D3 . As shown in FIG. 6 , the distance S1 or S2 between the trenches 1000 is less than the first distance D1 and/or the third distance D3, but is greater than, less than, or equal to the second distance D2.

如第3圖所示,第一連接凸部7022與第二凹部220b之間具有一第一最小寬度W1,第一連接部平邊7021與第二側邊222b之間具有一第二最小寬度W2,其中第一最小寬度W1小於第二最小寬度W2。如第6圖所示,第一連接凸部7022與第二凹部220b之間具有一第一最小寬度W1,第一連接部平邊7021與第二側邊222b之間具有一第二最小寬度W2,其中第一最小寬度W1大致相同於第二最小寬度W2。於另一實施例中(圖未示),第一最小寬度W1可以大於第二最小寬度W2。As shown in Figure 3, there is a first minimum width W1 between the first connection convex part 7022 and the second recess 220b, and there is a second minimum width W2 between the first connection part flat edge 7021 and the second side 222b. , where the first minimum width W1 is smaller than the second minimum width W2. As shown in Figure 6, there is a first minimum width W1 between the first connection convex part 7022 and the second recess 220b, and there is a second minimum width W2 between the first connection part flat edge 7021 and the second side 222b. , where the first minimum width W1 is approximately the same as the second minimum width W2. In another embodiment (not shown), the first minimum width W1 may be larger than the second minimum width W2.

第一延伸電極71及第二延伸電極72可以包括具有反射性的金屬層,因此,可以將在活性層23b,23a生成而向第一延伸電極71及第二延伸電極72傳播的光向基板10之一側反射。例如,第一延伸電極71及第二延伸電極72可以形成為單一反射金屬層,然而並不局限於此,也可以包括反射層及阻擋層。第一延伸電極71及第二延伸電極72可以使用諸如鎳(Ni)、鈦(Ti)、或鎢(W)等金屬層作為阻擋層,可以使用諸如銀(Ag)或鋁(Al)等反射率高的金屬層作為反射層。The first extended electrode 71 and the second extended electrode 72 may include reflective metal layers. Therefore, the light generated in the active layers 23b and 23a and propagated toward the first extended electrode 71 and the second extended electrode 72 may be directed toward the substrate 10 One side reflection. For example, the first extended electrode 71 and the second extended electrode 72 may be formed as a single reflective metal layer, but are not limited thereto, and may also include a reflective layer and a blocking layer. The first extended electrode 71 and the second extended electrode 72 may use a metal layer such as nickel (Ni), titanium (Ti), or tungsten (W) as a barrier layer, and may use a reflective layer such as silver (Ag) or aluminum (Al). A metal layer with high efficiency is used as a reflective layer.

第一電極墊91及第二電極墊92具有不同的導電性,例如第一電極墊91可以是N型電極墊,第二電極墊92可以是P型電極墊。第一電極墊91及第二電極墊92分別位於第二發光單元1a及第一發光單元1b的半導體台面20m上,沿著第一延伸電極71及第二延伸電極72的周圍而設立,且具有大致相同的形狀。第一電極墊91及第二電極墊92分別藉由保護層80的第一保護層開口801及第二保護層開口802以接觸第一延伸電極71及第二延伸電極72,並分別電連接至第二發光單元1a及第一發光單元1b。第一保護層開口801及第二保護層開口802的開口數目依第一電極51a及第二電極52b的數目而定。如第1圖所示,複數個第一保護層開口801各位於兩相鄰的第二電極52a之間,且複數個第一保護層開口801的開口數目與第一電極51a的數目相同。複數個第二保護層開口802各位於兩相鄰的第二電極52b之間。The first electrode pad 91 and the second electrode pad 92 have different conductivities. For example, the first electrode pad 91 can be an N-type electrode pad, and the second electrode pad 92 can be a P-type electrode pad. The first electrode pad 91 and the second electrode pad 92 are respectively located on the semiconductor mesa 20m of the second light-emitting unit 1a and the first light-emitting unit 1b, are established along the periphery of the first extended electrode 71 and the second extended electrode 72, and have Roughly the same shape. The first electrode pad 91 and the second electrode pad 92 contact the first extended electrode 71 and the second extended electrode 72 through the first protective layer opening 801 and the second protective layer opening 802 of the protective layer 80 respectively, and are electrically connected to The second light-emitting unit 1a and the first light-emitting unit 1b. The number of the first protective layer opening 801 and the second protective layer opening 802 depends on the number of the first electrode 51a and the second electrode 52b. As shown in Figure 1, the plurality of first protective layer openings 801 are each located between two adjacent second electrodes 52a, and the number of the plurality of first protective layer openings 801 is the same as the number of the first electrodes 51a. Each of the plurality of second protective layer openings 802 is located between two adjacent second electrodes 52b.

由於第一電極墊91設置於第二發光單元1a之第一電極51a及第二電極52a上,且第二電極墊92設置於第一發光單元1b之第二電極52b上,使得第一電極墊91及第二電極墊92的上表面是非平坦的。Since the first electrode pad 91 is disposed on the first electrode 51a and the second electrode 52a of the second light-emitting unit 1a, and the second electrode pad 92 is disposed on the second electrode 52b of the first light-emitting unit 1b, the first electrode pad The upper surfaces of 91 and the second electrode pad 92 are non-flat.

如第1圖~第2圖及第4圖~第5圖所示,保護層80的第一保護層開口801與絕緣層60的第一絕緣層開口601a不重疊,且保護層80的第二保護層開口802與絕緣層60的第二絕緣層開口602b不重疊。因此,即使焊料通過保護層80的第一絕緣層開口801、第二絕緣層開口802而侵入發光元件1或2,也能夠防止焊料向絕緣層60的第一絕緣層開口601a、第二絕緣層開口602b擴散,從而能夠防止焊料污染接觸電極40a,40b。As shown in Figures 1 to 2 and Figures 4 to 5, the first protective layer opening 801 of the protective layer 80 does not overlap with the first insulating layer opening 601a of the insulating layer 60, and the second protective layer opening 801 of the protective layer 80 does not overlap. The protective layer opening 802 does not overlap with the second insulation layer opening 602b of the insulation layer 60 . Therefore, even if the solder invades the light-emitting element 1 or 2 through the first insulating layer opening 801 and the second insulating layer opening 802 of the protective layer 80 , the solder can be prevented from entering the first insulating layer opening 601 a and the second insulating layer of the insulating layer 60 The opening 602b is diffused, thereby preventing solder from contaminating the contact electrodes 40a, 40b.

位於第一發光單元1a的第二電極52b及第二保護層開口802沿橫向相互交替佈置。位於第二發光單元1a的第二電極52a及第一保護層開口801沿橫向相互交替佈置。保護層開口801,802的數量或其佈置不僅考慮延伸電極71,72被焊料的污染,還可以考慮電流分散的效率性及發光圖案的對稱性等來選擇,因此可以進行多種變更。The second electrodes 52b and the second protective layer openings 802 located in the first light-emitting unit 1a are arranged alternately with each other in the lateral direction. The second electrodes 52a and the first protective layer openings 801 located in the second light-emitting unit 1a are arranged alternately with each other in the lateral direction. The number or arrangement of the protective layer openings 801 and 802 can be selected considering not only the contamination of the extended electrodes 71 and 72 by solder but also the efficiency of current dispersion and the symmetry of the light-emitting pattern, and therefore can be modified in various ways.

於一俯視圖下,如第7圖所示,半導體台面20m包含一圓弧角半徑大於或等於5μm,較佳大於或等於10μm,更佳大於或等於15μm以避免自第二延伸電極72或第二電極墊92注入之電流聚集於半導體台面20m的角落。第二延伸電極72或第二電極墊92相應於半導體台面20m亦具有一圓弧角,並且第二延伸電極72或第二電極墊92之圓弧角與半導體台面20m之圓弧角具有一最大距離R1或R2大於第二延伸電極72或第二電極墊92之一側與半導體台面20m之一側間的一最大距離。In a top view, as shown in FIG. 7 , the semiconductor mesa 20m includes an arc angular radius greater than or equal to 5 μm, preferably greater than or equal to 10 μm, and more preferably greater than or equal to 15 μm to avoid interference from the second extended electrode 72 or the second extended electrode 72 . The current injected from the electrode pad 92 is concentrated at the corners of the semiconductor mesa 20m. The second extended electrode 72 or the second electrode pad 92 also has an arc angle corresponding to the semiconductor mesa 20m, and the arc angle of the second extended electrode 72 or the second electrode pad 92 has a maximum arc angle with the arc angle of the semiconductor mesa 20m. The distance R1 or R2 is greater than a maximum distance between one side of the second extended electrode 72 or the second electrode pad 92 and one side of the semiconductor mesa 20 m.

第一電極51a,51b,第二電極52a,52b,第一延伸電極72,連接電極70,第二延伸電極71,第一電極墊91,以及第二電極墊92包含金屬材料,例如鉻(Cr)、鈦(Ti)、鎢(W)、金(Au)、鋁(Al)、銦(In)、錫(Sn)、鎳(Ni)、鉑(Pt)、銀(Ag)等金屬或上述材料之合金。第一電極51a,51b,第二電極52a,52b,第一延伸電極72,連接電極70,第二延伸電極71,第一電極墊91,以及第二電極墊92可由單層或是多層所組成。例如,第一電極51a,51b,第二電極52a,52b,第一延伸電極72,連接電極70,第二延伸電極71,第一電極墊91,以及第二電極墊92可包括Ti/Au層、Ti/Pt/Au層、Cr/Au層、Cr/Pt/Au層、Ni/Au層、Ni/Pt/Au層、Cr/Al/Ni/Ti/Ni/Ti/Au/Ti、Cr/Al/Cr/Ni/Au層或Ag/NiTi/TiW/Pt層。第一電極墊91及第二電極墊92可做為外部電源供電至第一發光單元1b及第二發光單元1a之電流路徑。第一電極51a,51b,第二電極52a,52b,第一延伸電極72,連接電極70,第二延伸電極71,第一電極墊91,或第二電極墊92包含一厚度介於1μm~100μm之間,較佳為1.2μm~60μm之間,更佳為1.5μm~6μm之間。The first electrodes 51a, 51b, the second electrodes 52a, 52b, the first extended electrode 72, the connecting electrode 70, the second extended electrode 71, the first electrode pad 91, and the second electrode pad 92 include metallic materials, such as chromium (Cr). ), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), silver (Ag) and other metals or the above Material alloy. The first electrodes 51a, 51b, the second electrodes 52a, 52b, the first extended electrode 72, the connecting electrode 70, the second extended electrode 71, the first electrode pad 91, and the second electrode pad 92 may be composed of a single layer or multiple layers. . For example, the first electrodes 51a, 51b, the second electrodes 52a, 52b, the first extension electrode 72, the connection electrode 70, the second extension electrode 71, the first electrode pad 91, and the second electrode pad 92 may include a Ti/Au layer , Ti/Pt/Au layer, Cr/Au layer, Cr/Pt/Au layer, Ni/Au layer, Ni/Pt/Au layer, Cr/Al/Ni/Ti/Ni/Ti/Au/Ti, Cr/ Al/Cr/Ni/Au layer or Ag/NiTi/TiW/Pt layer. The first electrode pad 91 and the second electrode pad 92 can be used as current paths for external power supply to the first light-emitting unit 1b and the second light-emitting unit 1a. The first electrodes 51a, 51b, the second electrodes 52a, 52b, the first extended electrode 72, the connecting electrode 70, the second extended electrode 71, the first electrode pad 91, or the second electrode pad 92 include a thickness between 1 μm and 100 μm. is preferably between 1.2 μm and 60 μm, and more preferably between 1.5 μm and 6 μm.

第一延伸電極72,連接電極70,及第二延伸電極71可以在同一道製程中一同形成為具有相同的金屬疊層。第一電極墊91及第二電極墊92可以在同一道製程中一同形成為具有相同的金屬疊層。於本實施例中,不同道製程中的金屬疊層具有不同的厚度與疊層結構。The first extension electrode 72, the connection electrode 70, and the second extension electrode 71 can be formed together in the same process to have the same metal stack. The first electrode pad 91 and the second electrode pad 92 can be formed together in the same process to have the same metal stack. In this embodiment, the metal stacks in different processes have different thicknesses and stack structures.

絕緣層60或保護層80可以為一單層結構,由氧化矽、氮化矽或是氮氧化矽所構成。絕緣層60或保護層80也可以藉由高折射率層和低折射率層交替堆疊以形成一分布式布拉格反射鏡(DBR)結構,選擇性地反射特定波長之光。例如,可通過層疊SiO 2/TiO 2或SiO 2/Nb 2O 5等層來形成高反射率的絕緣反射結構。當SiO 2/TiO 2或SiO 2/Nb 2O 5形成分布式布拉格反射鏡(DBR)結構時,分布式布拉格反射鏡(DBR)結構的每一個層被設計成活性層23a,23b發出的光的波長的四分之一的光學厚度的一或整數倍。分布式布拉格反射鏡(DBR)結構的每一個層的光學厚度在λ/4的一或整數倍的基礎上可具有±30%的偏差。由於分布式布拉格反射鏡(DBR)結構的的每一個層的光學厚度會影響到反射率,因此優選地利用電子束蒸鍍(E-beam evaporation)來形成以穩定的控制分布式布拉格反射鏡(DBR)結構的每一個層的厚度。絕緣層60或保護層80優選的具有0.5μm~4μm的厚度,較佳具有2.5μm~3.5μm的厚度,更佳具有2.7μm~3.3μm的厚度。兩相鄰的高折射率層及低折射率層的光學厚度差小於0.05λ,更佳小於0.025λ。光學厚度(optical thickness)為物理厚度(physical thickness)與材料層折射率(n)的乘積。 The insulating layer 60 or the protective layer 80 may be a single-layer structure composed of silicon oxide, silicon nitride or silicon oxynitride. The insulating layer 60 or the protective layer 80 can also be alternately stacked by high refractive index layers and low refractive index layers to form a distributed Bragg reflector (DBR) structure to selectively reflect light of specific wavelengths. For example, an insulating reflective structure with high reflectivity can be formed by stacking layers of SiO 2 /TiO 2 or SiO 2 /Nb 2 O 5 . When SiO 2 /TiO 2 or SiO 2 /Nb 2 O 5 forms a distributed Bragg reflector (DBR) structure, each layer of the distributed Bragg reflector (DBR) structure is designed to emit light from the active layers 23a, 23b One or an integer multiple of the optical thickness that is one quarter of the wavelength. The optical thickness of each layer of a distributed Bragg reflector (DBR) structure can have a deviation of ±30% based on one or an integer multiple of λ/4. Since the optical thickness of each layer of the distributed Bragg reflector (DBR) structure will affect the reflectivity, E-beam evaporation is preferably used to form the distributed Bragg reflector (DBR) with stable control. The thickness of each layer of the DBR) structure. The insulating layer 60 or the protective layer 80 preferably has a thickness of 0.5 μm ~ 4 μm, preferably a thickness of 2.5 μm ~ 3.5 μm, and more preferably a thickness of 2.7 μm ~ 3.3 μm. The optical thickness difference between two adjacent high refractive index layers and low refractive index layers is less than 0.05λ, preferably less than 0.025λ. Optical thickness is the product of physical thickness and the refractive index of the material layer (n).

於本發明之一實施例中,發光元件1或2更包含一調變層90設於基板10之第二表面110上。調變層90包含一光場調變層,可以藉由高折射率層和低折射率層交替堆疊以形成一分布式布拉格反射鏡(DBR)結構。光場調變層90對半導體疊層20a,20b所發出之一具有一峰值波長λ之光線具有選擇性反射及穿透的作用,使得光線的穿透率因入射角而變化,藉以調整發光元件1或2的光場分布。光場調變層90優選的具有0.5μm~5μm,較佳為1μm~3μm,更佳為1.5μm~2μm。兩相鄰的高折射率層及低折射率層的光學厚度差大於0.025λ,較佳大於0.05λ,更佳大於0.1λ。光學厚度(optical thickness)為物理厚度(physical thickness)與材料層折射率(n)的乘積。於一實施例中,調變層90包含一濾光層,可以藉由高折射率層和低折射率層交替堆疊以將波長大於,及/或小於特定波長的光反射或吸收,僅穿透特定波長的光,藉此純化發光元件1或2發出的光。於一實施例中,調變層90包含一濾光層,可以藉由高折射率層和低折射率層交替堆疊以將大於特定角度範圍的光反射或吸收,僅穿透特定角度範圍的光,藉此縮小發光元件1或2的出光角度。In an embodiment of the present invention, the light-emitting element 1 or 2 further includes a modulation layer 90 disposed on the second surface 110 of the substrate 10 . The modulation layer 90 includes a light field modulation layer, which can be formed by alternately stacking high refractive index layers and low refractive index layers to form a distributed Bragg reflector (DBR) structure. The light field modulation layer 90 selectively reflects and penetrates light emitted by the semiconductor stacks 20a and 20b with a peak wavelength λ, so that the transmittance of the light changes due to the incident angle, thereby adjusting the light-emitting element. Light field distribution of 1 or 2. The light field modulation layer 90 preferably has a thickness of 0.5 μm ~ 5 μm, preferably 1 μm ~ 3 μm, and more preferably 1.5 μm ~ 2 μm. The optical thickness difference between two adjacent high refractive index layers and low refractive index layers is greater than 0.025λ, preferably greater than 0.05λ, and more preferably greater than 0.1λ. Optical thickness is the product of physical thickness and the refractive index of the material layer (n). In one embodiment, the modulation layer 90 includes a filter layer, which can be alternately stacked by high refractive index layers and low refractive index layers to reflect or absorb light with wavelengths greater than, and/or less than a specific wavelength, and only transmit the light. Light of a specific wavelength, thereby purifying the light emitted by the light-emitting element 1 or 2. In one embodiment, the modulation layer 90 includes a filter layer, which can reflect or absorb light greater than a specific angle range by alternately stacking high refractive index layers and low refractive index layers, and only transmit light within a specific angle range. , thereby reducing the light emission angle of the light-emitting element 1 or 2.

第8圖係為依本發明一實施例之發光裝置3之示意圖。將前述實施例中的發光元件1,2以倒裝晶片之形式安裝於封裝基板51之第一墊片511、第二墊片512上。第一墊片511、第二墊片512之間藉由一包含絕緣材料之絕緣部53做電性絕緣。倒裝晶片之安裝係將發光元件1,2之基板10的第二表面110設為主要的光取出面。為了增加發光裝置3之光取出效率,可於發光元件1或2之周圍設置一反射結構54。發光元件1或2藉於第一電極墊91及第二電極墊92分別電連接至封裝基板51之第一墊片511及第二墊片512。Figure 8 is a schematic diagram of a light emitting device 3 according to an embodiment of the present invention. The light-emitting elements 1 and 2 in the aforementioned embodiment are mounted on the first pad 511 and the second pad 512 of the packaging substrate 51 in the form of flip-chip. The first gasket 511 and the second gasket 512 are electrically insulated by an insulating portion 53 containing insulating material. In flip-chip mounting, the second surface 110 of the substrate 10 of the light-emitting elements 1 and 2 is used as the main light extraction surface. In order to increase the light extraction efficiency of the light-emitting device 3, a reflective structure 54 can be provided around the light-emitting element 1 or 2. The light-emitting element 1 or 2 is electrically connected to the first pad 511 and the second pad 512 of the packaging substrate 51 via the first electrode pad 91 and the second electrode pad 92 respectively.

第9圖係為依本發明一實施例之發光裝置4之示意圖。發光裝置4為一球泡燈包括一燈罩603、一反射鏡604、一發光模組611、一燈座610、一散熱片614、一連接部616、以及一電連接元件618。發光模組611包含一承載部606,以及複數個發光體608位於承載部606上,其中複數個發光體608可為前述實施例中的發光元件1,2或發光裝置3。Figure 9 is a schematic diagram of a light emitting device 4 according to an embodiment of the present invention. The light-emitting device 4 is a bulb lamp and includes a lampshade 603, a reflector 604, a light-emitting module 611, a lamp holder 610, a heat sink 614, a connecting part 616, and an electrical connection component 618. The light-emitting module 611 includes a carrying part 606, and a plurality of light-emitting bodies 608 located on the carrying part 606, where the plurality of light-emitting bodies 608 can be the light-emitting elements 1, 2 or the light-emitting device 3 in the aforementioned embodiments.

本發明所列舉之各實施例僅用以說明本發明,並非用以限制本發明之範圍。任何人對本發明所作之任何顯而易知之修飾或變更皆不脫離本發明之精神與範圍。Each embodiment listed in the present invention is only used to illustrate the present invention and is not intended to limit the scope of the present invention. Any obvious modifications or changes made by anyone to the present invention shall not depart from the spirit and scope of the present invention.

1,2:發光元件1, 2: Light-emitting components

1a:第二發光單元1a: Second light-emitting unit

1b:第一發光單元1b: First light-emitting unit

10:基板10:Substrate

10s:側面10s: Side

100:第一表面100: first surface

110:第二表面110: Second surface

1000:溝渠1000:Ditch

11:第一邊11: First side

12:第二邊12: Second side

20a,20b:半導體疊層20a, 20b: Semiconductor stack

20a1,20b1:內側面20a1, 20b1: medial side

20a2,20b2:外側面20a2, 20b2: outer side

20ma,20mb:半導體台面20ma, 20mb: semiconductor mesa

200:通孔200:Through hole

21a,21b:第一半導體層21a, 21b: first semiconductor layer

210a:第一凹部210a: first recess

210b:第一凸部210b: first convex part

211a,211b:第一側邊211a, 211b: first side

22a,22b:第二半導體層22a, 22b: second semiconductor layer

220a:第三凹部220a: The third recess

220b:第二凹部220b: Second recess

222a,222b:第二側邊222a, 222b: second side

23a,23b:活性層23a, 23b: active layer

3:發光裝置3:Lighting device

30a,30b:電流阻擋層30a, 30b: current blocking layer

4:發光裝置4:Lighting device

40a,40b:接觸電極40a, 40b: Contact electrode

51:封裝基板51:Package substrate

51a,51b:第一電極51a, 51b: first electrode

511:第一墊片511:First gasket

512:第二墊片512:Second gasket

52a,52b:第二電極52a, 52b: second electrode

53:絕緣部53:Insulation Department

54:反射結構54: Reflective structure

60:絕緣層60:Insulation layer

601a,601b:第一絕緣層開口601a, 601b: first insulation layer opening

602a,602b:第二絕緣層開口602a, 602b: Second insulation layer opening

603:燈罩603:Lampshade

604:反射鏡604:Reflector

606:承載部606: Bearing part

608:發光體608: Luminous body

610:燈座610: Lamp holder

611:發光模組611:Light-emitting module

614:散熱片614:Heat sink

616:連接部616:Connection Department

618:電連接元件618: Electrical connection components

70:連接電極70: Connect the electrode

700:跨橋部700: Bridge crossing department

701:第二連接部701: Second connection part

7011:第二連接部平邊7011: Second connection part flat edge

702:第一連接部702: First connection part

7021:第一連接部平邊7021: First connecting part flat edge

7022:第一連接凸部7022: First connecting convex part

71:第一延伸電極71: First extension electrode

72:第二延伸電極72: Second extension electrode

80:保護層80:Protective layer

801:第一保護層開口801: First protective layer opening

802:第二保護層開口802: Second protective layer opening

90:光場調變層90:Light field modulation layer

91:第一電極墊91: First electrode pad

92:第二電極墊92: Second electrode pad

D1:第一間距D1: first distance

D2:第二間距D2: second distance

D3:第三間距D3: The third distance

d1:第一距離d1: first distance

d2:第二距離d2: second distance

ISO:分離區域ISO: separation area

m1,m1’,m2,m2’:側邊m1, m1’, m2, m2’: side

R:半徑R:radius

R1,R2:最大距離R1, R2: maximum distance

S:間距S: spacing

S1:第一間距S1: first spacing

S2:第二間距S2: second spacing

W1:第一最小寬度W1: first minimum width

W2:第二最小寬度W2: The second smallest width

第1圖係本發明一實施例所揭示之一發光元件1的上視圖。Figure 1 is a top view of a light-emitting element 1 disclosed in an embodiment of the present invention.

第2圖係沿著第1圖之切線Y-Y’的發光元件1的剖面圖。Figure 2 is a cross-sectional view of the light-emitting element 1 taken along the tangent line Y-Y' in Figure 1.

第3圖係第1圖之位置Ⅰ的部分放大圖。Figure 3 is a partially enlarged view of position I of Figure 1.

第4圖係本發明一實施例所揭示之一發光元件2的上視圖。Figure 4 is a top view of a light-emitting element 2 disclosed in an embodiment of the present invention.

第5圖係沿著第4圖之切線Y-Y’的發光元件2的剖面圖。Figure 5 is a cross-sectional view of the light-emitting element 2 taken along the tangent line Y-Y' in Figure 4.

第6圖係第4圖之位置Ⅱ的部分放大圖。Figure 6 is a partially enlarged view of position II of Figure 4.

第7圖係第1圖之位置Ⅲ或第4圖之位置Ⅲ的部分上視圖。Figure 7 is a partial top view of position III in Figure 1 or position III in Figure 4.

第8圖係為依本發明一實施例之發光裝置3之示意圖。Figure 8 is a schematic diagram of a light emitting device 3 according to an embodiment of the present invention.

第9圖係為依本發明一實施例之發光裝置4之示意圖。Figure 9 is a schematic diagram of a light emitting device 4 according to an embodiment of the present invention.

1:發光元件 1:Light-emitting component

1b:第一發光單元 1b: First light-emitting unit

1a:第二發光單元 1a: Second light-emitting unit

10:基板 10:Substrate

100:第一表面 100: first surface

1000:溝渠 1000:Ditch

11:第一邊 11: First side

12:第二邊 12: Second side

20a,20b:半導體疊層 20a, 20b: Semiconductor stack

20ma,20mb:半導體台面 20ma, 20mb: semiconductor mesa

200:通孔 200:Through hole

21a,21b:第一半導體層 21a, 21b: first semiconductor layer

210a:第一凹部 210a: first recess

210b:第一凸部 210b: first convex part

220a:第三凹部 220a: The third recess

220b:第二凹部 220b: Second recess

30a,30b:電流阻擋層 30a, 30b: current blocking layer

40a,40b:接觸電極 40a, 40b: Contact electrode

51a,51b:第一電極 51a, 51b: first electrode

52a,52b:第二電極 52a, 52b: second electrode

601a,601b:第一絕緣層開口 601a, 601b: first insulation layer opening

602a,602b:第二絕緣層開口 602a, 602b: Second insulation layer opening

70:連接電極 70: Connect the electrode

700:跨橋部 700: Bridge crossing department

701:第二連接部 701: Second connection part

702:第一連接部 702: First connection part

71:第一延伸電極 71: First extension electrode

72:第二延伸電極 72: Second extension electrode

801:第一保護層開口 801: First protective layer opening

802:第二保護層開口 802: Second protective layer opening

91:第一電極墊 91: First electrode pad

92:第二電極墊 92: Second electrode pad

ISO:分離區域 ISO: separation area

m1,m1’,m2,m2’:側邊 m1, m1’, m2, m2’: side

Claims (10)

一發光元件,包含:一基板包含一第一表面及一與該第一表面相對之第二表面;以及一第一發光單元位於該基板之該第一表面上,包含一第一半導體層及一半導體台面位於該第一半導體層上;以及一第一電極設置於該第一發光單元之該第一半導體層上,其中自該發光元件之一上視圖觀之,該第一半導體層包含一第一側邊,該半導體台面包含一第二側邊及一第二凹部凹陷於該第二側邊,並且該第一側邊與該第二側邊之間具有一第三間距大於或等於該第一電極與該第二凹部之間之一第二間距。 A light-emitting element, including: a substrate including a first surface and a second surface opposite to the first surface; and a first light-emitting unit located on the first surface of the substrate, including a first semiconductor layer and a The semiconductor mesa is located on the first semiconductor layer; and a first electrode is provided on the first semiconductor layer of the first light-emitting unit, wherein when viewed from above one of the light-emitting elements, the first semiconductor layer includes a On one side, the semiconductor mesa includes a second side and a second recess recessed in the second side, and there is a third spacing between the first side and the second side that is greater than or equal to the first side. a second distance between an electrode and the second recess. 如申請專利範圍第1項所述的發光元件,其中該發光元件之任一邊具有一長度小於或等於200μm。 The light-emitting element described in item 1 of the patent application, wherein any side of the light-emitting element has a length less than or equal to 200 μm. 如申請專利範圍第1項所述的發光元件,其中該第一半導體層包含一第一凸部突出於該第一側邊,且該第一電極與該第一凸部之間包含一第一間距大於該第一電極與該第二凹部之間之該第二間距。 The light-emitting element according to claim 1, wherein the first semiconductor layer includes a first convex portion protruding from the first side, and a first convex portion is included between the first electrode and the first convex portion. The distance is greater than the second distance between the first electrode and the second recess. 如申請專利範圍第1項所述的發光元件,其中該第一電極包含一寬度大於該第二間距。 As described in claim 1 of the patent application, the first electrode includes a width greater than the second spacing. 如申請專利範圍第1項所述的發光元件,包含一分離區域露出該基板之該第一表面,其中該發光元件具有一第一邊以及一與第一邊相接之第二邊,該分離區域於該第一邊上具有一第一距離且於該第二邊上具有一第二距離,且該第一距離與該第二距離具有不同的寬度。 The light-emitting element described in item 1 of the patent application includes a separation area exposing the first surface of the substrate, wherein the light-emitting element has a first side and a second side connected to the first side, and the separation area The area has a first distance on the first side and a second distance on the second side, and the first distance and the second distance have different widths. 如申請專利範圍第5項所述的發光元件,其中該第一距離包含一寬度介於5μm~15μm之間。 For the light-emitting element described in item 5 of the patent application, the first distance includes a width between 5 μm and 15 μm. 如申請專利範圍第6項所述的發光元件,其中該第二距離包含一寬度介於3μm~9μm之間。 For the light-emitting element described in item 6 of the patent application, the second distance includes a width between 3 μm and 9 μm. 如申請專利範圍第3項所述的發光元件,更包含一電極墊位於該半導體台面上,其中該半導體台面包含一第一圓弧角,該電極墊相應於該半導體台面具有一第二圓弧角,該電極墊之該第二圓弧角與該半導體台面之該第一圓弧角具有一最大距離大於該電極墊之一側與該半導體台面之一側間的一最大距離。 The light-emitting element described in item 3 of the patent application further includes an electrode pad located on the semiconductor mesa, wherein the semiconductor mesa includes a first arc angle, and the electrode pad has a second arc corresponding to the semiconductor mesa. The second arc angle of the electrode pad and the first arc angle of the semiconductor mesa have a maximum distance greater than a maximum distance between one side of the electrode pad and one side of the semiconductor mesa. 如申請專利範圍第3項所述的發光元件,更包含一第二發光單元位於該基板上,以及一溝渠位於該第一發光單元與該第二發光單元之間,其中該溝渠包含一間距小於於該第二間距。 The light-emitting element described in Item 3 of the patent application further includes a second light-emitting unit located on the substrate, and a trench located between the first light-emitting unit and the second light-emitting unit, wherein the trench includes a distance less than at this second distance. 如申請專利範圍第9項所述的發光元件,其中該第一發光單元與該第二發光單元分別包括一內側面及一外側面,且相較於該內側面,該外側面較陡峭。 For the light-emitting element described in claim 9, the first light-emitting unit and the second light-emitting unit respectively include an inner side and an outer side, and compared with the inner side, the outer side is steeper.
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* Cited by examiner, † Cited by third party
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TW202111967A (en) * 2015-11-13 2021-03-16 晶元光電股份有限公司 Light-emitting device
TW202006978A (en) * 2018-07-12 2020-02-01 晶元光電股份有限公司 Light-emitting device

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