TW202349746A - Light-emitting device - Google Patents

Abstract

A light-emitting device includes a light-emitting stack including a first semiconductor layer and a second semiconductor layer, wherein in a top view, the light-emitting stack includes an outer peripheral portion and an inner region, the outer peripheral portion exposes the first semiconductor layer, and the second semiconductor layer is disposed on the inner region besides the outer periphery portion; an insulating layer including a plurality of first insulating layer external openings and a second insulating layer opening; a first electrode covering the plurality of first insulating layer external openings to contact the first semiconductor layer through the plurality of first insulating layer external openings; a second electrode covering the second insulating layer opening; and a protective layer covering the insulating layer, wherein a part at the outer periphery portion where the insulating layer and the protective layer are in contact includes a total thickness gradually decreasing from the outer periphery portion to the inner region.

Description

Light emitting element

The present invention relates to a light-emitting element, and in particular to a flip-chip light-emitting element including a plurality of electrode contact regions.

Light-Emitting Diode (LED) is a solid-state semiconductor light-emitting element. Its advantages are low power consumption, low heat energy generation, long working life, shockproof, small size, fast response speed and good optoelectronic properties, such as Stable luminescence wavelength. Therefore, light-emitting diodes are widely used in household appliances, equipment indicators, and optoelectronic products.

A light-emitting element includes a semiconductor stack including a first semiconductor layer and a second semiconductor layer, wherein in a top view, the semiconductor stack includes an outer peripheral portion and an inner region, the outer peripheral portion exposes the first semiconductor layer, and the third Two semiconductor layers are disposed in the inner area outside the outer peripheral portion; an insulating layer includes a plurality of outer openings of the first insulating layer and a second opening of the second insulating layer; a first electrode covers a plurality of outer openings of the first insulating layer, and is formed by A plurality of outer openings of the first insulating layer contact the first semiconductor layer; a second electrode covers the opening of the second insulating layer; and a protective layer covers the insulating layer, wherein the portion where the insulating layer and the protective layer contact at the outer periphery includes a total thickness It gradually decreases from the outer circumference to the inner area.

In order to make the description of the present invention more detailed and complete, please refer to the description of the following embodiments and the relevant illustrations. However, the embodiments shown below are used to illustrate the light-emitting element of the present invention, and the present invention is not limited to the following embodiments. In addition, the size, material, shape, relative arrangement, etc. of the constituent parts described in the embodiments described in this specification are not described as limiting, and the scope of the present invention is not limited thereto, but is merely explained. In addition, the size and positional relationship of components shown in each diagram may be exaggerated for clear explanation. Moreover, in the following description, in order to omit detailed explanation appropriately, components of the same or similar nature are shown with the same names and symbols.

Figure 1 is a top view of the structure of a light-emitting element 1 disclosed in an embodiment of the present invention. Figure 2 is a structural cross-sectional view along the tangent line X-X’ of Figure 1.

As shown in Figures 1 and 2, the light-emitting element 1 includes a substrate 10; and a semiconductor stack 20 is located on the substrate 10, which includes a first semiconductor layer 201, a second semiconductor layer 202, and an active Layer 203 is located between the first semiconductor layer 201 and the second semiconductor layer 202 . In a top view and a side view of the light-emitting element 1 , the semiconductor stack 20 includes an outer peripheral portion 2011 and an inner region 2010 . The first semiconductor layer 201 is exposed in the outer peripheral portion 2011, and the second semiconductor layer 202 and the active layer 203 are provided in the inner region 2010 surrounded by the outer peripheral portion 2011. An insulating layer 50 includes a plurality of first insulating layer outer openings 5011 located in the outer peripheral portion 2011 , a first insulating layer inner opening 5012 located in the inner region 2010 , and a second insulating layer opening 502 located in the inner region 2010 . A first electrode 61 covers the plurality of outer openings 5011 of the first insulating layer, and contacts the first semiconductor layer 201 at the outer peripheral portion 2011 through the plurality of outer openings 5011 of the first insulating layer to form a plurality of first electrode first contact areas 611 . The first electrode 61 covers the inner opening 5012 of the first insulating layer, and contacts the first semiconductor layer 201 in the inner region 2010 through the inner opening 5012 of the first insulating layer to form the first electrode second contact region 612. A second electrode 62 covers the second insulation layer opening 502 and is electrically connected to the second semiconductor layer 202 through the second insulation layer opening 502 . A protective layer 70 covers the insulating layer 50 , the first electrode 61 , and the second electrode 62 . The portion where the insulating layer 50 and the protective layer 70 contact the outer peripheral portion 2011 includes a total thickness that gradually decreases from the outer peripheral portion 2011 toward the inner region 2010 .

The substrate 10 may be a growth substrate for epitaxially growing the semiconductor stack 20 . The substrate 10 includes a gallium arsenide (GaAs) wafer for epitaxial growth of aluminum gallium indium phosphide (AlGaInP), or for the growth of gallium nitride (GaN), indium gallium nitride (InGaN), or aluminum gallium nitride. (AlGaN) sapphire (Al ₂ O ₃ ) wafer, gallium nitride (GaN) wafer, silicon carbide (SiC) wafer, or aluminum nitride (AlN) wafer.

Figure 3A is a partial cross-sectional view of the light-emitting element 1 disclosed according to an embodiment of the present invention, and is an enlarged view of the area P indicated by a dotted line in Figure 2. The surface of the substrate 10 that is in contact with the semiconductor stack 20 may have a roughened surface. The roughened surface may be a surface with irregular morphology or a surface with regular morphology. For example, relative to the upper surface 101 of the substrate 10 , the substrate 10 includes one or a plurality of convex portions 100 protruding from the upper surface 101 , or one or a plurality of recessed portions (not shown) recessed in the upper surface 101 . In a cross-sectional view, the convex part 100 or the concave part (not shown) may be in the shape of a hemisphere or a polygonal cone.

The plurality of protrusions 100 include a first layer 1001 and a second layer 1002. The first layer 1001 includes the same material as the substrate 10, such as gallium arsenide (GaAs), sapphire (Al ₂ O ₃ ), gallium nitride ( GaN), silicon carbide (SiC), or aluminum nitride (AlN). The second layer 1002 includes materials different from those constituting the first layer 1001 and the substrate 10 . The material of the second layer 1002 includes an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. Viewed from the side of the light-emitting element 1 , the convex portion 100 includes a hemispherical shape, a cannonball shape or a conical shape. The top end of the convex portion 100 may be a curved surface or a sharp point. In one embodiment of the present invention, the convex portion 100 only includes the second layer 1002 and lacks the first layer 1001 , wherein a bottom surface of the second layer 1002 is flush with the upper surface 101 of the substrate 10 .

In one embodiment of the present invention, by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), physical vapor deposition (PVD), or The ion plating method is used to form a semiconductor stack 20 with optoelectronic properties, such as a light-emitting stack, on the substrate 10 . The physical vapor deposition method includes sputtering or evaporation.

The semiconductor stack 20 includes a first semiconductor layer 201, a second semiconductor layer 202, and an active layer 203 formed between the first semiconductor layer 201 and the second semiconductor layer 202. The wavelength of light emitted by the light-emitting element 1 is adjusted by changing the physical and chemical composition of one or more layers in the semiconductor stack 20 . The material of the semiconductor stack 20 includes III-V group semiconductor materials, such as Al _x In _y Ga _(1-xy) N or Al _x In _y Ga _(1-xy) P, where 0≦x, y≦1; (x +y)≦1. When the material of the semiconductor stack 20 is an AlInGaP series material, it can emit red light with a wavelength between 610 nm and 650 nm. When the material of the semiconductor stack 20 is an InGaN series material, it can emit blue light with a wavelength between 400 nm and 490 nm, or green light with a wavelength between 530 nm and 570 nm. When the material of the semiconductor stack 20 is an AlGaN series material or an AlInGaN series material, it can emit ultraviolet light with a wavelength between 250 nm and 400 nm.

The first semiconductor layer 201 and the second semiconductor layer 202 can be a cladding layer or a confinement layer. They have different conductive types, electrical properties, polarities, or are doped with elements to provide Electrons or holes, for example, the first semiconductor layer 201 is an n-type semiconductor, and the second semiconductor layer 202 is a p-type semiconductor. The active layer 203 is formed between the first semiconductor layer 201 and the second semiconductor layer 202. Electrons and holes are driven by a current to recombine in the active layer 203, converting electrical energy into light energy to emit light. The active layer 203 may be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum structure (multi-quantum). well, MQW). The material of the active layer 203 may be a neutral, p-type or n-type electrical semiconductor. The first semiconductor layer 201, the second semiconductor layer 202, or the active layer 203 may be a single layer or a structure including a plurality of sub-layers.

In one embodiment of the present invention, the semiconductor stack 20 may further include a buffer layer (not shown) between the first semiconductor layer 201 and the substrate 10 to release material between the substrate 10 and the semiconductor stack 20. The stress caused by lattice mismatch can reduce misalignment and lattice defects, thereby improving the epitaxial quality. The buffer layer may be a single layer or a structure including multiple sub-layers. In one embodiment, PVD aluminum nitride (AlN) can be used as a buffer layer formed between the semiconductor stack 20 and the substrate 10 to improve the epitaxial quality of the semiconductor stack 20 . In one embodiment, the target used to form PVD aluminum nitride (AlN) is composed of aluminum nitride. In another embodiment, a target composed of aluminum can be used, and aluminum nitride can be formed by reacting with the aluminum target in a nitrogen source environment.

In one embodiment of the present invention, as shown in FIGS. 1 and 2 , the light-emitting element 1 includes a first electrode pad 81 and a second electrode pad 82 formed on the same side of the semiconductor stack 20 and formed in an inverted manner. Chip mounting (flip chip) structure or formal horizontal chip (lateral chip) structure.

As shown in FIG. 1 , the semiconductor stack 20 is generally rectangular in plan view and includes four corners and four side walls. The four side walls include straight lines, square corrugations, wavy patterns or a combination of any two of the above. The four sidewalls of the semiconductor stack 20 include a first sidewall 21 , a second sidewall 22 opposite to the first sidewall 21 , a third sidewall 23 , and a fourth sidewall 24 opposite to the third sidewall 23 . The four corners contain arcs or straight lines. The four corners of the semiconductor stack 20 include a first corner C1, a second corner C2, a third corner C3, and a fourth corner C4.

In this embodiment, the semiconductor stack 20 is patterned through an etching process, part of the second semiconductor layer 202 and the active layer 203 are removed, and the first semiconductor layer 201 is exposed to form the outer peripheral portion 2011 and the peripheral portion 2011 . Surrounded medial area 2010. The inner region 2010 includes one or a plurality of semiconductor mesas 20m and one or a plurality of holes 2000. Viewed from a top view of the self-luminous element 1, as shown in Figure 1, the outer peripheral portion 2011 includes a plurality of recessed portions 2006, and two adjacent recessed portions 2006 are separated by a protruding portion 2007. The recessed portion 2006 is not provided with the second semiconductor layer 202 and the active layer 203 , and the recessed portion 2006 exposes the first semiconductor layer 201 . The protruding portion 2007 has a first semiconductor layer 201, a second semiconductor layer 202, and an active layer 203. Compared with the recessed portion 2006, a plan view shape of the protruding portion 2007 includes an arc or a rectangle. In this embodiment, a plurality of semicircular first insulating layer outer openings 5011 are formed on each sidewall 21 to 24 of the light-emitting stack 20 and have the same size. The top view shape of the outer opening 5011 of the first insulating layer may be a semicircle, a triangle, a trapezoid or a rectangle. The size and shape of the opening 5011 on the outside of the first insulating layer are not limited thereto. In addition, the first insulating layer outer opening 5011 with different sizes or shapes may also be included.

The first spacing between the plurality of first insulating layer outer openings 5011 adjacent to the first sidewall 21 is the same as the second spacing between the plurality of first insulating layer outer openings 5011 adjacent to the second sidewall 22 . However, the first spacing between the plurality of first insulating layer outer openings 5011 adjacent to the first sidewall 21 is different from the third spacing between the plurality of first insulating layer outer openings 5011 adjacent to the third sidewall 23 .

Accordingly, each of the second semiconductor layer 202 and the active layer 203 has a smaller upper surface area than the first semiconductor layer 201 . The semiconductor mesa 20m is located on the first semiconductor layer 201 and includes the second semiconductor layer 202 and the active layer 203. The recessed portion 2006 and the hole 2000 expose the first semiconductor layer 201 . A plurality of holes 2000 are formed in the inner region 2010 and are arranged in a straight line or an array at a fixed distance from each other.

In the top view or side view of the light-emitting element 1, the hole 2000 includes a width between 5 μm and 20 μm, preferably between 8 μm and 15 μm. The top view shape of the hole 2000 includes a circle, an ellipse, a semicircle, a rectangle, or a strip.

One of the plurality of holes 2000 is separated from a first side 11 of the light-emitting element 1 by a first shortest distance, and one of the plurality of holes 2000 is separated from a second side 12 of the light-emitting element 1 by a second shortest distance. The first side and the second side are opposite sides, and the first shortest distance is greater than or equal to the second shortest distance. One of the plurality of holes 2000 is spaced apart from a third side 13 of the light-emitting element 1 by a third shortest distance. The third side is orthogonal to the first side, and the first shortest distance and/or the second shortest distance is greater than the third shortest distance. Three shortest distances.

The plurality of holes 2000 and the peripheral portion 2011 are formed by removing portions of the second semiconductor layer 202 and the active layer 203 to expose the first semiconductor layer 201 . The side 20S of the second semiconductor layer 202 and the active layer 203 exposed by etching is an inclined surface relative to the exposed first semiconductor layer 201 , where the inclined surface may include a surface covering multiple slopes.

The first electrode 61 contacts the first semiconductor layer 201 through the plurality of holes 2000 located in the inner region 2010 and the recessed portion 2006 located in the outer peripheral portion 2011, and forms an electrical connection with the first semiconductor layer 201. The second electrode 62 is formed on the second semiconductor layer 202 and is electrically connected to the second semiconductor layer 202 through a contact electrode 40 .

Figure 3A is a partial cross-sectional view of the light-emitting element 1 disclosed according to an embodiment of the present invention, and is an enlarged view of the area P indicated by a dotted line in Figure 2. Figure 3B is a partial cross-sectional view of the light-emitting element 1 disclosed according to another embodiment of the present invention, and is an enlarged view of the area P indicated by a dotted line in Figure 2.

A passivation layer 30 covers the semiconductor mesa 20m and includes one or a plurality of first passivation layer openings 301 and one or a plurality of second passivation layer openings 302. Viewed from a top view of the light-emitting element 1 , the first passivation layer opening 301 is disposed on the hole 2000 and the recessed portion 2006 and exposes the first semiconductor layer 201 . The second passivation layer opening 302 is disposed on the semiconductor mesa 20m and exposes the second semiconductor layer 202. As shown in Figures 3A and 3B, the passivation layer 30 includes a first passivation layer portion 31 contacting the first semiconductor layer 201, and a second passivation layer portion 32 contacting the second semiconductor layer 202. The first passivation layer portion 31 includes a first length L1 between 5 μm and 10 μm. The second passivation layer portion 32 includes a second length L2 between 13 μm and 16 μm.

The contact electrode 40 is disposed in the second passivation layer opening 302 and contacts the second semiconductor layer 202 . The contact electrode 40 substantially covers the upper surface of the semiconductor mesa 20m. For example, the contact electrode 40 can cover more than 80% of the semiconductor mesa 20m, preferably more than 90%. In an embodiment of the present invention, the contact electrode 40 may include any one or more of a transparent conductive layer 401, a reflective layer 402, and a barrier layer 403.

The transparent conductive layer 401 may be disposed between the reflective layer 402 and the second semiconductor layer 202 . In order to reduce the contact resistance and improve the efficiency of current diffusion, the material of the transparent conductive layer 401 includes a material that is transparent to the light emitted by the active layer 203, such as a transparent conductive oxide. Transparent conductive oxides include indium tin oxide (ITO) or indium zinc oxide (IZO). In one embodiment of the present invention, the transparent conductive layer 401 may be a metal layer with a thickness less than 500 angstroms.

The material of the reflective layer 402 includes reflective metals, such as aluminum (Al), silver (Ag), rhodium (Rh), platinum (Pt), or alloys of the above materials. The reflective layer 402 is used to reflect the light emitted by the active layer 203 and to emit the reflected light toward the substrate 10 .

As shown in FIG. 3B , the barrier layer 403 can cover one side of the reflective layer 402 to prevent the reflective layer 402 from oxidizing and degrading its reflectivity. The material of the barrier layer 403 includes metal materials, such as titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), chromium (Cr), platinum (Pt) and other metals or alloys of the above materials. In one embodiment, as shown in FIG. 3A , the barrier layer 403 does not cover the reflective layer 402 , and one side of the barrier layer 403 can be flush with one side of the reflective layer 402 or expose part of the reflective layer 402 upper surface.

The contact electrode 40 can diffuse the current supplied via the second electrode 62 to the second semiconductor layer 202 . In addition, the contact electrode 40 has good light reflectivity and can be used as a layer that reflects the light emitted by the light-emitting element 1 toward the light output surface (that is, one side of the substrate 10 ).

As shown in FIG. 3A , the contact electrode 40 does not contact the passivation layer 30 , and a spacing S is located between the passivation layer 30 and the contact electrode 40 . A portion of the insulating layer 50 is located within the spacing S between the contact electrode 40 and the passivation layer 30 , so that the insulating layer 50 includes an insulating recess 50 a corresponding to the spacing S.

As shown in FIG. 3B , the contact electrode 40 includes a first contact portion 40 a covering the passivation layer 30 and a second contact portion 40 b directly contacting the second semiconductor layer 202 . The first contact portion 40a of the contact electrode 40 includes a thickness smaller than the second contact portion 40b, and the thickness of the first contact portion 40a gradually decreases from the inside to the outside of the semiconductor mesa 20m. The thickness corresponds to the thickness measured in a direction perpendicular to the upper surface of the second semiconductor layer 202 . The third length L3 between the edge of the first contact portion 40a and the side 20S of the semiconductor mesa 20m may be smaller than the fourth length L4 of the first contact portion 40a covering the passivation layer 30 to increase the adhesion of the electrode and increase the reflection area. Taking process variations into account, the third length L3 between the edge of the first contact portion 40 a and the side 20S of the semiconductor mesa 20 m may be greater than the fourth length L4 of the first contact portion 40 a covering the passivation layer 30 . In this embodiment, the third length L3 can be between 0 μm and 8 μm, preferably between 0 μm and 3 μm. The fourth length L4 can be between 5 μm and 18 μm, preferably between 10 μm and 13 μm.

The insulating layer 50 covers the semiconductor mesa 20m and includes one or several first insulating layer outer openings 5011, first insulating layer inner openings 5012, and a second insulating layer opening 502. From the top view of the light-emitting element 1 , the outer opening 5011 of the first insulating layer is provided on the recess 2006 and exposes the first semiconductor layer 201 . The inner opening 5012 of the first insulating layer is disposed on the hole 2000 to correspond to the position of the hole 2000 and expose the first semiconductor layer 201 . The second insulating layer opening 502 is disposed on the contact electrode 40 and exposes any one or more layers of the transparent conductive layer 401 , the reflective layer 402 and/or the barrier layer 403 of the contact electrode 40 . A plurality of first insulating layer outer openings 5011 located in the outer peripheral portion 2011 are sequentially arranged along the four sides of the light-emitting element 1 . The insulating layer 50 of the light-emitting element 1 covers the four corners of the semiconductor stack 20 .

In one embodiment of the invention, as shown in FIG. 2 , the insulating layer 50 includes an insulating layer platform 500 located under the second electrode 62 and the second electrode pad 82 . In the top view of the light-emitting element 1, as shown in FIG. 1, the insulating layer platform 500 is surrounded by the second insulating layer opening 502. The insulating layer platform 500 may be formed within or outside a projected area of the second electrode pad 82 . In the side view of the light-emitting element 1 , the insulating layer platform 500 is covered by the second electrode 62 .

The first electrode 61 covers the plurality of first insulating layer outer openings 5011 and the first insulating layer inner openings 5012 of the insulating layer 50 and contacts the first semiconductor layer 201 . The second electrode 62 covers the second insulation layer opening 502 of the insulation layer 50 and contacts the second semiconductor layer 202 and/or the contact electrode 40 . In a top view of the light-emitting element 1 , the second electrode 62 and the second insulation layer opening 502 have the same shape. In one embodiment, the second electrode 62 and the second insulation layer opening 502 are also substantially rectangular. In one embodiment, the second electrode 62 may be formed larger than the second insulation layer opening 502 . The first electrode 61 and the second electrode 62 are separated by the insulating layer 50 . There is a gap G between the first electrode 61 and the second electrode 62, which is located on the semiconductor mesa 20m and exposes the insulating layer 50. The gap G is between 3 μm and 30 μm, preferably between 5 μm and 25 μm, and more preferably between 18 μm and 18 μm. ~22μm.

As shown in FIGS. 1 and 2 , the first electrode 61 covers the plurality of inner openings 5012 of the first insulating layer, and contacts the first semiconductor layer 201 through the plurality of inner openings 5012 of the first insulating layer to form a plurality of first Electrode second contact area 612. The first electrode 61 covers the plurality of first insulating layer outer openings 5011 and contacts the first semiconductor layer 201 at the outer peripheral portion 2011 through the plurality of first insulating layer outer openings 5011 to form a plurality of first electrode first contact regions 611 . Each of the plurality of first electrode first contact areas 611 includes a first contact area smaller than a second contact area of each of the plurality of first electrode second contact areas 612 . The plurality of first electrode first contact areas 611 includes a first total contact area that is larger than a second total contact area of the plurality of first electrode second contact areas 612 .

In this embodiment, by arranging a plurality of first electrode first contact areas 611 in the outer peripheral portion 2011 and reducing the total second contact area of the first electrode second contact areas 612 in the inner area 2010, it is possible to suppress the increase in the forward voltage V _f Ascending, it can ensure a wider luminous area.

In a plan view of the light-emitting element 1 , a plurality of first electrode first contact areas 611 are formed in areas other than the four corners, and a plurality of first electrode first contact areas 611 are formed at equal or non-equal intervals around the periphery. above 2011 to improve the distribution of current density.

As shown in FIG. 1 , the light-emitting element 1 includes a pin area 60 located at the geometric center of the semiconductor stack 20 . The ejector region 60 is not in contact with the first electrode 61 and the second electrode 62 and is electrically isolated from the first electrode 61 and the second electrode 62 . The ejection pin area 60 is used as a structure to protect the epitaxial layer to prevent the epitaxial layer from being damaged by the ejection pins during subsequent processes, such as die separation, flipping, testing die, and packaging.

The protective layer 70 includes a first protective layer opening 701 located in the inner region 2010 and a second protective layer opening 702 located in the inner region 2010, and the first protective layer opening 701 includes a first opening width W1 larger than the second protective layer opening 702. a second opening width W2.

The light-emitting element 1 includes a first electrode pad 81 and a second electrode pad 82 . As shown in FIG. 1 , the first electrode pad 81 is adjacent to the first sidewall 21 of the semiconductor stack 20 and the second electrode pad 82 is adjacent to the second sidewall 22 of the semiconductor stack 20 . A first distance between the first electrode pad 81 and the first side wall 21 is smaller than a second distance between the second electrode pad 82 and the second side wall 22 .

As shown in FIG. 2 , the first electrode pad 81 contacts the first electrode 61 through the first protective layer opening 701 , and the second electrode pad 82 contacts the second electrode 62 through the second protective layer opening 702 .

The first electrode pad 81 and the second electrode pad 82 have different conductivities. For example, the first electrode pad 81 can be an N-type electrode pad, and the second electrode pad 82 can be a P-type electrode pad. The first electrode pad 81 and the second electrode pad 82 are located on the semiconductor mesa 20m, and are respectively located on the first protective layer opening 701 and the second protective layer opening 702 to contact the first electrode 61 and the second electrode 62, and are electrically connected respectively. to the first semiconductor layer 201 and the second semiconductor layer 202 .

The ejector region 60, the first electrode 61, the second electrode 62, the first electrode pad 81 and the second electrode pad 82 include metal materials, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), Aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), silver (Ag) and other metals or alloys of the above materials. The ejector region 60, the first electrode 61, the second electrode 62, the first electrode pad 81 and the second electrode pad 82 may be composed of a single layer or multiple layers. For example, the ejector region 60, the first electrode 61, the second electrode 62, the first electrode pad 81 or the second electrode pad 82 may include a Ti/Au layer, a Ti/Pt/Au layer, a Cr/Au layer, a Cr/Pt/ Au layer, Ni/Au layer, Ni/Pt/Au layer, Cr/Al/Cr/Ni/Au layer or Ag/NiTi/TiW/Pt layer. The first electrode pad 81 and the second electrode pad 82 can serve as current paths for external power supply to the first semiconductor layer 201 and the second semiconductor layer 202 . The first electrode 61, the second electrode 62, the first electrode pad 81 and the second electrode pad 82 each include a thickness between 1 μm and 100 μm, preferably between 1.2 μm and 60 μm, and more preferably between 1.5 μm and 6 μm. between.

The passivation layer 30 , the insulating layer 50 and/or the protective layer 70 are provided on the semiconductor stack 20 and serve as a protective film and an antistatic interlayer insulating film for the light-emitting element 1 . As the insulating film, the passivation layer 30 , the insulating layer 50 and/or the protective layer 70 may be a single-layer structure, including metal oxide or metal nitride. For example, it may be preferably selected from the group consisting of Si, Ti, Zr, Nb, Ta, and Al. At least one oxide or nitride from the group consisting of. The passivation layer 30 , the insulating layer 50 , and/or the protective layer 70 may also include two or more materials with different refractive indexes that are alternately stacked to form a distributed Bragg reflector (DBR) structure to selectively reflect light of specific wavelengths. For example, an insulating reflective structure with high reflectivity can be formed by stacking layers of SiO ₂ /TiO ₂ or SiO ₂ /Nb ₂ O ₅ . When SiO ₂ /TiO ₂ or SiO ₂ /Nb ₂ O ₅ forms a distributed Bragg reflector (DBR) structure, each layer of the distributed Bragg reflector (DBR) structure is designed to be the wavelength of the light emitted by the active layer 212 One or an integral multiple of one quarter of the optical thickness. The thickness of each layer of a distributed Bragg reflector (DBR) structure can have a deviation of ±30% based on one or an integer multiple of λ/4. Since the thickness of each layer of the distributed Bragg reflector (DBR) structure will affect the reflectivity, E-beam evaporation is preferably used to form the dielectric layer 30, the insulating layer 50, and/or Or the protective layer 70 to stably control the thickness of each layer of the distributed Bragg reflector (DBR) structure.

The light-emitting element 1 includes a scribe line 10d located between the side 10S of the substrate 10 and the side 21S of the first semiconductor layer 201, and the scribe line 10d includes a width between 5 μm and 50 μm, preferably less than 30 μm, and more preferably Less than 15μm. The cutting lines 10d expose the upper surface 101 of the substrate 10 and are located around the light-emitting element 1 to surround the semiconductor stack 20.

Figure 4 is an enlarged view of area I indicated by a dotted line in Figure 1. Figure 5 is a structural cross-sectional view along the tangent line I-I’ in Figure 4. Figure 6 is an enlarged view of area II indicated by a dotted line in Figure 1. Figure 7 is a structural cross-sectional view along the tangent line II-II' of Figure 6. As shown in FIGS. 4 and 5 , in the direction parallel to the first side 11 or the second side 12 of the light-emitting element 1 , the protruding portion 2007 includes a maximum width between 30 μm and 60 μm. The recessed portion 2006 has a maximum width between 30 μm and 60 μm.

The portion where the insulating layer 50 and the protective layer 70 contact the outer peripheral portion 2011 includes a first thickness T1 and a second thickness T2, and the second thickness T2 is greater than the first thickness T1. In one embodiment of the invention, the first thickness T1 is between 3 μm and 30 μm, and the second thickness T2 is between 6 μm and 60 μm. The thickness corresponds to the thickness measured in a direction perpendicular to the upper surface of the second semiconductor layer 202 .

The portion where the passivation layer 30 and the insulating layer 50 contact on the semiconductor mesa 20m includes a third thickness T3 and a fourth thickness T4, and the fourth thickness T4 is greater than the third thickness T3. In one embodiment of the invention, the third thickness T3 is between 3 μm and 30 μm, and the fourth thickness T4 is between 6 μm and 60 μm. The thickness corresponds to the thickness measured in a direction perpendicular to the upper surface of the second semiconductor layer 202 .

As shown in FIG. 5 , the cutting track 10d adjacent to the first side 11 of the light-emitting element 1 includes a first width D1. As shown in FIG. 7 , the cutting track 10d adjacent to the second side 12 of the light-emitting element 1 includes a second width D2. The first width D1 and the second width D2 may be the same or different. In this embodiment, the second width D2 is greater than the first width D1, and there is a ratio (D2/D1) between the second width D2 and the first width D1 that is greater than 2 but less than 4.

Figure 8 is an enlarged view of area III indicated by a dotted line in Figure 1 . Figure 9 is a structural cross-sectional view along the tangent line III-III' of Figure 8. Figure 10 is an enlarged view of area IV indicated by a dotted line in Figure 1 . Figure 11 is a structural cross-sectional view of the tangent line IV-IV’ in Figure 10. In a direction parallel to the third side 13 or the fourth side 14 of the light-emitting element 1 , the protruding portion 2007 includes a maximum width between 30 μm and 60 μm. The recessed portion 2006 has a maximum width between 30 μm and 60 μm.

As shown in FIG. 9 , a portion of the cutting track 10d adjacent to the third side 13 or the fourth side 14 (not shown) of the light-emitting element 1 includes a third width D3. As shown in FIG. 11, another part of the cutting track 10d adjacent to the third side 13 or the fourth side 14 (not shown) of the light-emitting element 1 includes a fourth width D4. The third width D3 and the fourth width D4 are different. In other words, the cutting lane 10d adjacent to the third side 13 or the fourth side 14 of the light-emitting element 1 includes more than two widths, the fourth width D4 is larger than the third width D3, and the distance between the fourth width D4 and the third width D3 is The ratio (D4/D3) is greater than 2 but less than 4. In a direction parallel to the third side 13 or the fourth side 14 of the light-emitting element 1, the length of a portion of the cutting lane 10d having the third width D3 may be greater than, less than, or equal to the length of the other portion of the cutting lane 10d having the fourth width D4. part length. In order to retain more light emitting area, it is preferable that the length of a part of the cutting track 10d having the third width D3 is greater than the length of another part of the cutting track 10d having the fourth width D4.

As shown in FIGS. 5 and 7 , the first electrode 61 includes a first electrode first side surface 611S adjacent to the first side 11 of the light-emitting element 1 and a first electrode second side surface 612S adjacent to the first side 11 of the light-emitting element 1 . 12 on both sides. The distance between the first side surface 611S of the first electrode and the first side 11 of the light-emitting element 1 is smaller than the distance between the second side surface 612S of the first electrode and the second side 12 of the light-emitting element 1 .

As shown in Figures 9 and 11, the first electrode 61 further includes a first electrode third side surface 613S adjacent to the third side 13 of the light-emitting element 1 and the first side 11 of the light-emitting element 1, and a first electrode The fourth side surface 614S is adjacent to the third side 13 of the light-emitting element 1 and the second side 12 of the light-emitting element 1 . The distance between the third side surface 613S of the first electrode and the third side 13 of the light-emitting element 1 is smaller than the distance between the fourth side surface 614S of the first electrode and the third side 13 of the light-emitting element 1 .

Figure 13 is a schematic diagram of a light emitting device 2 according to an embodiment of the present invention. The light-emitting element 1 in the aforementioned embodiment is mounted on the first pad 511 and the second pad 512 of the packaging substrate 51 in the form of a flip chip. The first gasket 51511 and the second gasket 512 are electrically insulated by an insulating portion 53 containing insulating material. In flip-chip mounting, the side of the growth substrate opposite to the electrode pad formation surface is set upward as the main light extraction surface. For example, the substrate 10 of the light-emitting element 1 is the main light extraction surface of the light-emitting element 1 . In order to increase the light extraction efficiency of the light-emitting device 2, a reflective structure 54 can be provided around the light-emitting element 1.

Figure 14 is a schematic diagram of a light emitting device 3 according to an embodiment of the present invention. The light-emitting device 3 is a bulb lamp and includes a lampshade 602, a reflector 604, a light-emitting module 600, a lamp holder 610, a heat sink 614, a connecting part 616 and an electrical connection component 618. The light-emitting module 600 includes a carrying part 606, and a plurality of light-emitting units 608 located on the carrying part 606, where the plurality of light-emitting bodies 608 can be the light-emitting elements 1 or the light-emitting devices 2 in the aforementioned embodiments.

Each embodiment listed in the present invention is only used to illustrate the present invention and is not intended to limit the scope of the present invention. Any obvious modifications or changes made by anyone to the present invention shall not depart from the spirit and scope of the present invention.

1:Light-emitting component

10:Substrate

10d: cutting lane

10S: Side

100:convex part

1001:First floor

1002:Second floor

101: Upper surface

11: First side

12: Second side

13:Third side

2:Lighting device

20: Semiconductor stack

20m:Semiconductor table

20S: Side

201: First semiconductor layer

202: Second semiconductor layer

203:Active layer

2000: Holes

2006: Depression

2007: Bulge

2010:Inside area

2011: Peripheral Department

21:Side wall

21S: Side

22:Side wall

23:Side wall

24:Side wall

3:Lighting device

30: Passivation layer

301: First passivation layer opening

302: Second passivation layer opening

31: First passivation layer part

32: Second passivation layer part

40: Contact electrode

40a: First contact part

40b: Second contact part

401:Transparent conductive layer

402: Reflective layer

403:Barrier layer

50:Insulation layer

50a: Insulating recess

502: Second insulation layer opening

500:Insulation layer platform

5011: Opening on the outside of the first insulation layer

5012: Opening inside the first insulation layer

51:Package substrate

511:First gasket

512:Second gasket

53:Insulation Department

54: Reflective structure

60: thimble area

600:Light-emitting module

602:Lampshade

604:Reflector

606: Bearing part

608:Light-emitting unit

61: First electrode

610: Lamp holder

611: first electrode first contact area

611S: first side surface of first electrode

612: First electrode second contact area

612S: First electrode second side surface

613S: The third side surface of the first electrode

614S: The fourth side surface of the first electrode

614:Heat sink

616:Connection Department

618: Electrical connection components

62: Second electrode

70: Second electrode

701: First protective layer opening

702: Second protective layer opening

81: First electrode pad

82: Second electrode pad

C1:First corner

C2:Second corner

C3:Third corner

C4:Fourth corner

D1: first width

D2: second width

D3: third width

D4: fourth width

G: spacing

L1: first length

L2: second length

L3: The third length

L4: The fourth length

S: spacing

T1: first thickness

T2: second thickness

T3: The third thickness

T4: The fourth thickness

W1: first opening width

W2: Second opening width

Figure 1 is a top view of the structure of a light-emitting element 1 disclosed in an embodiment of the present invention.

Figure 2 is a structural cross-sectional view along the tangent line X-X’ of Figure 1.

Figure 3A is a partial cross-sectional view of the light-emitting element 1 disclosed according to an embodiment of the present invention, and is an enlarged view of the area P indicated by a dotted line in Figure 2.

Figure 3B is a partial cross-sectional view of the light-emitting element 1 disclosed according to another embodiment of the present invention, and is an enlarged view of the area P indicated by a dotted line in Figure 2.

Figure 4 is an enlarged view of area I indicated by a dotted line in Figure 1.

Figure 5 is a structural cross-sectional view along the tangent line I-I’ in Figure 4.

Figure 6 is an enlarged view of area II indicated by a dotted line in Figure 1.

Figure 7 is a structural cross-sectional view along the tangent line II-II' of Figure 6.

Figure 8 is an enlarged view of area III indicated by a dotted line in Figure 1 .

Figure 9 is a structural cross-sectional view along the tangent line III-III' of Figure 8.

Figure 10 is an enlarged view of area IV indicated by a dotted line in Figure 1 .

Figure 11 is a structural cross-sectional view along the tangent line IV-IV’ in Figure 10.

Figure 12 is a schematic diagram of a light emitting device 2 according to an embodiment of the present invention.

Figure 13 is a schematic diagram of a light emitting device 3 according to an embodiment of the present invention.

without

1:Light-emitting component

10:Substrate

10d: cutting lane

10S: Side

101: Upper surface

20: Semiconductor stack

20m:Semiconductor table

20S: Edge

201: First semiconductor layer

202: Second semiconductor layer

203:Active layer

2000: Holes

2006: Depression

2010:Inside area

2011: Peripheral Department

21S: Side

30: Passivation layer

301: First passivation layer opening

302: Second passivation layer opening

40: Contact electrode

50:Insulation layer

500:Insulation layer platform

502: Second insulation layer opening

5011: Opening on the outside of the first insulation layer

5012: Opening inside the first insulation layer

61: First electrode

611: first electrode first contact area

612: First electrode second contact area

62: Second electrode

70: Second electrode

701: First protective layer opening

702: Second protective layer opening

81: First electrode pad

82: Second electrode pad

Claims (10)

A light-emitting component including: a substrate; A semiconductor stack includes a first semiconductor layer, an active layer and a second semiconductor layer located on the substrate, wherein in a top view of the light-emitting element, the semiconductor stack includes a peripheral portion and an outer peripheral portion. A surrounding inner region, the outer peripheral portion exposes the first semiconductor layer, and the second semiconductor layer is disposed in the inner region; A plurality of holes are located in the inner region and pass through the active layer and the second semiconductor layer to expose the first semiconductor layer; An insulating layer includes a plurality of inner openings of the first insulating layer corresponding to the plurality of holes, a plurality of outer openings of the first insulating layer located in the peripheral portion, and a second insulating layer opening located in the inner region; A first electrode covers the plurality of inner openings of the first insulating layer and the plurality of outer openings of the first insulating layer, and contacts the first semiconductor layer at the outer peripheral portion through the plurality of outer openings of the first insulating layer to form a plurality of The first electrode first contact area, and contacts the first semiconductor layer through the inner openings of the first insulating layer to form a plurality of first electrode second contact areas; A second electrode covers the second insulating layer opening and is electrically connected to the second semiconductor layer through the second insulating layer opening; and A protective layer covers the insulating layer, the first electrode and the second electrode, Wherein, each of the first contact areas of the plurality of first electrodes includes a first contact area smaller than a second contact area of each of the second contact areas of the plurality of first electrodes. The light-emitting element described in item 1 of the patent application, wherein from the top view of the light-emitting element, the semiconductor stack includes four corners and four side walls, and the plurality of outer openings of the first insulating layer are located on the four side walls. on the four side walls outside the corners. The light-emitting element described in claim 2 of the patent application, wherein when viewed from the top view of the light-emitting element, the four side walls of the semiconductor stack include straight lines, square corrugations, wavy patterns, or a combination of any two of the foregoing. The light-emitting element as described in item 2 of the patent application includes a first electrode pad and a second electrode pad, wherein from the top view of the light-emitting element, the four side walls of the semiconductor stack include a first a side wall, a second side wall opposite to the first side wall, a third side wall, a fourth side wall opposite to the third side wall, and the first electrode pad is adjacent to the first side wall and the second electrode pad is adjacent to the The second side wall, wherein a first distance between the first electrode pad and the first side wall is less than a second distance between the second electrode pad and the second side wall. The light-emitting element as described in item 4 of the patent application, wherein the protective layer includes a first protective layer opening and a second protective layer opening located in the inner region, and the first protective layer opening includes a first opening with a width greater than The second protective layer opening includes a second opening width. The light-emitting element described in Item 4 of the patent application, wherein one of the plurality of holes is separated from a first side of the light-emitting element by a first shortest distance, and the one of the plurality of holes is separated from the first side of the light-emitting element. A second side is spaced apart by a second shortest distance, the one of the plurality of holes and a third side of the light-emitting element are spaced apart by a third shortest distance, and the first shortest distance is greater than or equal to the second The shortest distance, the first shortest distance is greater than the third shortest distance. The light-emitting element as described in claim 5, wherein the first electrode pad contacts the first electrode through the first protective layer opening, and the second electrode pad contacts the third electrode through the second protective layer opening. Two electrodes. As described in claim 1 of the patent application, the light-emitting element, wherein the plurality of first electrode first contact areas are scattered and formed at equal intervals on the outer peripheral portion. As described in claim 1 of the patent application, the light-emitting element, wherein the plurality of first electrode first contact areas are scattered and formed on the outer peripheral portion at non-equal intervals. The light-emitting element as described in claim 1 of the patent application, wherein the first contact areas of the plurality of first electrodes include a total first contact area that is larger than a total second contact area of the second contact areas of the first electrodes. area.

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