TWI801752B - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a connection structure including at least one first conductive wire and at least one second conductive wire. The first conductive wire is disposed on an active area of a substrate and extended along a first direction. The second conductive wire is disposed on the active area of the substrate and extended along the first direction. The length of the first conductive wire in the first direction is less than that of the second conductive wire in the first direction at the end portion of the connection structure.

Description

Semiconductor element and its manufacturing method

The present invention relates to a semiconductor element and its manufacturing method, and in particular to a self-aligned double patterned semiconductor element and its manufacturing method.

With the advancement of science and technology, semiconductor components are constantly developing towards "light, thin, short, and small". Therefore, how to reduce the line width and line spacing and improve the accuracy of pattern transfer has become a topic of concern for R&D personnel. . For example, self-aligned double patterning (Self-Aligned Double Patterning, SADP) can be used to achieve small line width, line pitch and improve the accuracy of pattern transfer. However, in the process of making semiconductor devices by self-aligned double patterning, it is easy to be affected by the line end cut process and the etching loading effect, which will cause short circuit and other problems, which will affect the subsequent formation. components, resulting in poor component yield. Therefore, how to prevent short circuits and improve component yields while meeting the requirements for integration and miniaturization has become one of the problems that researchers are eager to solve.

The invention provides a semiconductor element and a manufacturing method thereof, which can effectively avoid the short-circuit problem caused by the influence of wire end cutting process or etching load effect, so that the semiconductor element has good electrical performance.

An embodiment of the present invention provides a semiconductor device, which includes a connection structure including at least one first wire and at least one second wire. At least one first wire is disposed on the device area of the base and extends along a first direction. At least one second wire is disposed on the device area of the base and extends along the first direction. At the end of the connection structure, the length of the at least one first wire in the first direction is smaller than the length of the at least one second wire in the first direction.

In an embodiment of the present invention, the above-mentioned at least one first wire includes a plurality of first wires, the above-mentioned at least one second wire includes a plurality of second wires, and the plurality of first wires and the plurality of second wires are along different The second directions in the first direction are arranged alternately with each other.

In an embodiment of the present invention, the above-mentioned semiconductor device further includes pads. The pad is disposed on at least one second wire. The at least one second wire has a first line segment adjacent to the at least one first wire and a second line segment extending from the first line segment along a first direction, and the pad is disposed on the first line segment or the second line segment.

An embodiment of the invention provides a method for manufacturing a semiconductor device, which includes the following steps. A plurality of conductor patterns are formed on the element area of the substrate, each conductor pattern includes a first section and a second section parallel to each other and extending along a first direction, and a curved section connecting the first section and the second section, and the plurality of conductors The patterns are arranged along a second direction different from the first direction. A patterned mask with a wavy contour is covered on the plurality of conductor patterns, and the patterned mask exposes the curved section and a part of the adjacent curved section of the first section. removing the curved section exposed by the patterned mask and the portion of the first section adjacent to the curved section to form a connection structure comprising a plurality of first wires and a plurality of second wires, wherein the plurality of first wires are connected to the plurality of The second wires are arranged alternately along the second direction, and at the end of the connecting structure, the lengths of the plurality of first wires in the first direction are smaller than the lengths of the plurality of second wires in the first direction.

In an embodiment of the present invention, the peaks of the wavy profile are located on the second segment, and the troughs of the wavy profile are located on the first segment.

In an embodiment of the present invention, the above-mentioned manufacturing method of the semiconductor device further includes forming a plurality of pads on the plurality of second wires. Each second wire has a first line segment and a second line segment, the first line segment is located between two adjacent first wires, the second line segment extends from the first line segment along the first direction, and the pad forms on the first line segment or the second line segment.

Another embodiment of the present invention provides a method for manufacturing a semiconductor device, which includes the following steps. A conductor layer, a hard mask layer and a first mask pattern are sequentially formed on the device area of the substrate, the first mask pattern includes a first section and a second section parallel to each other and extending along a first direction and connecting the first section and a curved section of the second section, wherein the first section includes a first section and a second section, and the curved section includes a third section and a fourth section adjacent to the second section, wherein the height of the second section and the third section is smaller than that of the first section , the height of the fourth section and the second section. Using the first mask pattern as a mask, the hard mask layer is patterned to form a first spacer and a second spacer, wherein the length of the first spacer extending in the first direction is smaller than that of the second spacer in the first direction. The length of the direction extension. Using the first spacer and the second spacer as a mask, the conductor layer is patterned to form a connection structure comprising a first wire and a second wire, wherein at the end of the connection structure, the first wire is aligned in a first direction The extended length is less than the extended length of the second wire in the first direction.

In an embodiment of the present invention, the connection structure further includes a pad pattern, wherein the step of forming the pad pattern includes the following steps. Before forming the first spacer and the second spacer, a second mask pattern is formed on the second section of the first mask pattern. Using the first mask pattern and the second mask pattern as a mask, the hard mask layer is patterned to form a first spacer and a second spacer, wherein the second spacer has the same pattern as the pad pattern. Using the first spacer and the second spacer as a mask, the conductor layer is patterned to form a first wire and a second wire with a pad pattern.

In an embodiment of the present invention, the second wire has a first line segment adjacent to the first wire and a second line segment extending from the first line segment along a first direction, and the pad pattern is located on the first line segment or at the second line segment.

In an embodiment of the present invention, the manufacturing method of the above-mentioned semiconductor device further includes forming a dielectric layer covering the first wire and the second wire on the device area of the substrate after forming the first wire and the second wire. A contact window connected with the pad pattern is formed in the dielectric layer.

In an embodiment of the present invention, the ratio of the height of the second part and the third part to the height of the first part, the fourth part and the second section is between 0 and 1/3.

In an embodiment of the present invention, the first mask pattern is formed in multiples and arranged along a second direction different from the first direction, so that when the hard mask layer is subsequently patterned, the first spacers and A plurality of second spacers are formed and arranged alternately along the second direction, and subsequently, when the conductor layer is patterned, a plurality of first wires and second wires are formed and arranged alternately along the second direction.

Based on the above, in the semiconductor element and its manufacturing method of the present invention, the ends of the first wire and the second wire can be spaced apart from each other, so that the effects of the wire end cutting process or etching load effect can be effectively avoided. The resulting short circuit problem makes the semiconductor element have good electrical performance.

The present invention will be described more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

It will be understood that when an element is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. When an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connection" may refer to physical and/or electrical connection, while "electrical connection" or "coupling" may refer to the presence of other elements between two elements. "Electrical connection" as used herein may include physical connection (such as wired connection) and physical disconnection (such as wireless connection).

As used herein, "about" includes the stated value and the average within acceptable deviations from the particular value ascertained by one of ordinary skill in the art, taking into account the measurements in question and errors associated with the measurements A specific amount of (that is, a limitation of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the "about" used herein can select a more acceptable deviation range or standard deviation according to optical properties, etching properties or other properties, instead of using one standard deviation to apply to all properties.

The terms used herein are only used to illustrate exemplary embodiments, not to limit the present disclosure. In such cases, singular forms include plural forms unless the context explains otherwise.

1 to 2 are schematic partial top views of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

First, please refer to FIG. 1 , a plurality of conductive patterns 110 are formed on the device area AA of the substrate 100 . Here, the “device region” referred to herein refers to the region on the substrate 100 where devices such as active devices are formed. The substrate 100 may include a semiconductor substrate. The semiconductor substrate can be, for example, a doped silicon substrate, an undoped silicon substrate or a silicon-on-insulator (SOI) substrate. The doped silicon substrate can be P-type doped, N-type doped or a combination thereof. The substrate 100 may include active devices (such as PMOS, NMOS or CMOS), interlayer dielectric layers and/or contact windows, intermetal dielectric layers (IMD), conductive patterns and/or via windows of multiple metal interconnections, etc. member. However, in order to more clearly describe the manufacturing method of the semiconductor structure of the present invention, these components are not shown in the figure one by one.

Each conductor pattern 110 may include a first segment 110a and a second segment 110b parallel to each other and extending along the first direction X, and a curved segment 110c connecting the first segment 110a and the second segment 110b, and the conductor pattern 110 may be along different Arranged in the second direction Y of the first direction X. In this embodiment, the second direction Y and the first direction X may intersect each other, but the invention is not limited thereto. In this embodiment, the conductor pattern 110 may be a pattern with a U-shaped end, for example, the bent section 110c may constitute the U-shaped end of the conductor pattern 110 , but the invention is not limited thereto.

Next, a patterned mask 120 with a wave-shaped contour is covered on the plurality of conductor patterns 110 , wherein the patterned mask 120 exposes the curved section 110 c and a part Pa of the first section 110 a adjacent to the curved section 110 c. In this embodiment, the portion of the conductive pattern 110 covered by the patterned mask 120 can be defined as the second segment 110b, and the first segment 110a of the conductive pattern 110 can be defined as the second direction Y in FIG. Observe the part flush with the second segment 110b, so that the curved segment 110c can constitute the U-shaped end of the conductor pattern 110, and the patterned mask 120 exposes the curved segment 110c and a part Pa of the first segment 110a adjacent to the curved segment 110c . In this embodiment, the crest Wa of the wavy profile can be located on the second segment 110b, and the trough Wb of the wavy profile can be located on the first segment 110a. In this way, the first wire 130 and the second wire 132 formed in the subsequent process can have a good length difference in the first direction X at the end of the connection structure CS, so as to avoid the problem of short circuit. In this embodiment, the wavy profile may have a zig-zag profile, but the present invention is not limited thereto, as long as the first wire 130 and the second wire 132 can be connected in a subsequent process. A good length difference at the ends of the CS is sufficient. The material of the patterned mask 120 may include a photoresist material, but the invention is not limited thereto.

Then, referring to FIG. 2 , the curved segment 110 c and a portion Pa of the first segment 110 a exposed by the patterned mask 120 are removed to form a connection structure CS including the first wire 130 and the second wire 132 . The first wires 130 and the second wires 132 may respectively extend along the first direction X and be arranged alternately along the second direction Y. In this embodiment, at the end of the connection structure CS, the length L1 extending along the first direction X of the first wire 130 may be smaller than the length L2 extending along the first direction X of the second wire 132 . In this way, viewed from the top view direction of the substrate 100, the first conductive wires 130 and the second conductive wires 132 can be arranged in a staggered manner, and the positions of the ends of the first conductive wires 130 and the second conductive wires 132 can correspond to the trough Wb of the wavy profile, respectively. and the wave front Wa, so that the ends of the first wire 130 and the second wire 132 are spaced apart from each other, so the short circuit problem caused by the wire end cutting process or the effect of etching load can be effectively avoided, so that the semiconductor element has a good electrical performance. In this embodiment, the curved section 110c and a part Pa of the first section 110a exposed by the patterned mask 120 may be removed by etching. In this embodiment, the patterned mask 120 may be removed, for example, by an ashing process after the formation of the first wires 130 and the second wires 132 .

The second wire 132 can have a first line segment 132a and a second line segment 132b. The first line segment 132a of the second conducting wire 132 can be defined as the part that is flush with the first conducting wire 130 viewed from the second direction Y in FIG. The section 132a extends along the first direction X, but the present invention is not limited thereto. For example, in the case where the first wire 130 and the second wire 132 are formed in multiples, the first line segment 132a can be defined as a part located between two adjacent first wires 130; and the second line segment 132b It can be defined as a portion extending from the first line segment 132a along the first direction X.

Afterwards, the pad 140 may be formed on the first line segment 132 a or the second line segment 132 b of the second wire 132 . In some embodiments, the pad 140 may be formed on the second segment 132 b of the second wire 132 . In this way, since the first conductive wire 130 and the second conductive wire 132 are spaced apart from each other at the end of the connection structure CS, when the pad 140 is formed on the second line segment 132b, the short circuit problem can be further avoided or the formation can be further improved. The process window of the pad 140 .

3A to 13A are schematic partial top views of a method for manufacturing a semiconductor element according to another embodiment of the present invention; FIG. 3B to FIG. 13B are schematic cross-sectional views along line II' in FIG. 3A to FIG. The same element symbols in Fig. 2 represent the same or similar components, and some omitted technical descriptions, such as the dimensions, materials, and functions of each layer or region, can refer to the relevant content in Fig. 1 and Fig. Let me repeat.

First, please refer to FIG. 3A and FIG. 3B simultaneously, a conductor layer 200 , a hard mask layer 210 , an etch stop layer 220 , a first material layer 230 and a patterned mask layer 240 are sequentially formed on the device area AA of the substrate 100 . The material of the conductive layer 200 may include conductive materials such as metal, metal silicide or metal nitride. In this embodiment, the metal may be, for example, tungsten or titanium. The metal silicide can be, for example, tungsten silicide. The metal nitride may, for example, be titanium nitride. The hard mask layer 210 may be a single layer or multiple layers. In order to clearly express the present invention, FIG. 3B uses a single-layer hard mask layer 210 as an exemplary embodiment for illustration, but the present invention is not limited thereto. The hard mask layer 210 may also be multi-layered, for example It includes a nitride layer, an oxide layer and a carbon layer sequentially formed on the conductor layer 200 . The material of the nitride layer can be, for example, silicon nitride. The material of the oxide layer can be, for example, silicon oxide. The material of the carbon layer may be, for example, amorphous carbon. The material of the etch stop layer 220 may include nitride, such as silicon nitride. The material of the first material layer 230 may include amorphous silicon.

In this embodiment, the patterned mask layer 240 may include a plurality of strip patterns extending along the first direction X. As shown in FIG. The material of the patterned mask layer 240 may include a bottom anti-reflection coating (Bottom Anti-Reflection Coating, BARC) material. The method for forming the patterned mask layer 240 can be formed through the following steps. First, a mask material layer (not shown) is formed on the first material layer 230 . Next, a patterning process is performed on the above mask material layer to form a patterned mask layer 240 . In some embodiments, the patterned mask layer 240 can be formed, for example, by the following steps. Firstly, a multilayer photoresist (Multilayer Resist, MLR) and a mask pattern (not shown) are sequentially formed. The multilayer photoresist includes, for example, a lower photoresist layer and an upper photoresist layer. The material of the lower photoresist layer is, for example, bottom anti-reflection coating material. The material of the upper photoresist layer is, for example, Si-Bottom Anti-Reflection Coating (Si-BARC) material containing silicon. Next, the lower photoresist layer and the upper photoresist layer exposed by the patterned mask may be removed by means of dry etching to form the patterned mask layer 240 . Then, the mask pattern and the remaining upper photoresist layer are removed.

Next, referring to FIG. 4A and FIG. 4B , a second material layer 250 is formed on the first material layer 230 to cover the first material layer 230 and the patterned mask layer 240 . In this embodiment, the second material layer 250 can be conformally formed on the first material layer 230 and the patterned mask layer 240 . For example, the second material layer 250 may cover the top surface of the first material layer 230 exposed by the patterned mask layer 240 and the top surface and side surfaces of the patterned mask layer 240 . The method for forming the second material layer 250 may be molecular layer deposition (MLD). The material of the second material layer 250 may include silicon oxide, silicon nitride or silicon oxynitride, but the present invention is not limited thereto.

Then, please refer to FIG. 5A and FIG. 5B at the same time, remove the second material layer 250 disposed on the top surface of the patterned mask layer 240 and the first material layer 230 to form a layer on the sidewall of the patterned mask layer 240 The patterned second material layer 252 . Since the patterned mask layer 240 may include a plurality of strip patterns extending along the first direction X, the patterned second material layer 252 formed on the sidewalls of the strip patterns has a U-shaped end profile. In some embodiments, the second material layer 250 disposed on the top surfaces of the patterned mask layer 240 and the first material layer 230 may be removed by using methods such as each back. Next, the patterned mask layer 240 between the patterned second material layers 252 is removed. In some embodiments, an ashing process may be used to remove the patterned mask layer 240 between the patterned second material layers 252 .

Afterwards, please refer to FIG. 6A and FIG. 6B at the same time, using the patterned second material layer 252 as a mask, remove the first material layer 230 exposed by the patterned second material layer 252 to form a patterned first material layer 232 . The patterned first material layer 232 may include a first segment 232a and a second segment 232b parallel to each other and extending along the first direction X, and a curved segment 232c connecting the first segment 232a and the second segment 232b. In this embodiment, the curved section 232c may constitute a U-shaped end of the patterned first material layer 232 . In some embodiments, the first material layer 230 exposed by the patterned second material layer 252 may be removed by dry etching or the like. Then, after the patterned first material layer 232 is formed, the patterned second material layer 252 may be removed.

Then, referring to FIG. 7A and FIG. 7B , a mask material layer (not shown) is formed on the etch stop layer 220 to cover the patterned first material layer 232 . Next, a patterning process is performed on the mask material layer to form a patterned mask layer 260 exposing a portion of Pb of the patterned first material layer 232 . In this embodiment, the exposed portion Pb of the patterned mask layer 260 refers to the portion where the first segment 232a and the curved segment 232c of the patterned first material layer 232 are adjacent to each other, while the first segment 232a of the patterned first material layer 232 is adjacent to each other. The second segment 232b is completely covered by the patterned mask layer 260 without being exposed. The material of the patterned mask layer 260 may include photoresist, but the invention is not limited thereto.

Next, referring to FIG. 8A and FIG. 8B , a part of Pb of the patterned first material layer 232 exposed by the patterned mask layer 260 is partially removed to form a first mask pattern 234 . The first mask pattern 234 may include a first segment 234a and a second segment 234b parallel to each other and extending along the first direction X, and a curved segment 234c connecting the first segment 234a and the second segment 234b, wherein the first segment 234a may include The first portion P1 and the second portion P2, and the curved section 234c may include a third portion P3 and a fourth portion P4 adjacent to the second portion P2. In this embodiment, the second portion P2 and the third portion P3 may correspond to a portion Pb of the patterned first material layer 232 exposed by the patterned mask layer 260 . Since the part Pb of the patterned first material layer 232 exposed by the patterned mask layer 260 is partially removed, the second part P2 of the first segment 234a and the third part of the curved segment 234c The height H1 of P3 may be smaller than the height H2 of the first portion P1 of the first segment 234a, the fourth portion P4 of the curved segment 234c, and the second segment 234b. For example, the ratio (H1/H2) of the height H1 of the second part P2 and the third part P3 to the height H2 of the first part P1, the fourth part P4 and the second section 234b may be between 0 and 1/3 . When the ratio (H1/H2) of the height H1 to the height H2 is about 1/3, not only the manufacturing cost can be further reduced, but also the remaining second part P2 and the third part P3 can maintain the shape of the first mask pattern 234. Structural stability avoids problems such as structural collapse in subsequent processes, thereby improving the resolution of patterns formed in subsequent processes. In this embodiment, the first mask pattern 234 may be formed in multiples and arranged along the second direction Y different from the first direction X, but the invention is not limited thereto. In some embodiments, etching may be used to partially remove a portion of Pb exposed by the patterned mask layer 260 of the patterned first material layer 232 , but the invention is not limited thereto. The patterned mask layer 260 can be removed after the first mask pattern 234 is formed. In some embodiments, an ashing process may be used to remove the patterned mask layer 260 , but the invention is not limited thereto.

Then, referring to FIG. 9A and FIG. 9B simultaneously, a third material layer 270 may be formed on the first mask pattern 234 . The third material layer 270 may be a single layer or multiple layers. In this embodiment, the third material layer 270 may include a lower mask layer 272 and an upper mask layer 274 sequentially formed on the etch stop layer 220 . The first mask pattern 234 can be embedded in the lower mask layer 272 . For example, the height H3 of the lower mask layer 272 may be greater than the height H1 and the height H2, but the invention is not limited thereto. The material of the lower mask layer 272 is, for example, a bottom anti-reflection coating material. The material of the upper mask layer 274 is, for example, silicon-containing bottom anti-reflection coating material.

Next, a second mask pattern 280 can be formed on the third material layer 270 , wherein the second mask pattern 280 can define an area of a pad pattern to be formed later. In this embodiment, as shown in FIG. 9B , the second mask pattern 280 may be formed on the second section 234 b of the first mask pattern 234 . As shown in FIG. 9A , the second mask pattern 280 may be formed on the second section 234b adjacent to the curved section 234c and overlaps a part of the curved section 234c, but the invention is not limited thereto. In other embodiments, the second mask pattern 280 may be formed on the second section 234b away from the curved section 234c, that is, viewed from the top view direction of the substrate 100, the second mask pattern 280 may be located on two adjacent second sections. A section between 234a. The material of the second mask pattern 280 may include a photoresist material.

Afterwards, please refer to FIG. 10A and FIG. 10B at the same time, using the first mask pattern 234 and the second mask pattern 280 as masks, the hard mask layer 210 is patterned to form the first spacer 210a and the second spacer 210b, wherein the second spacer 210b has the same pattern PP as the pad pattern CP formed in the subsequent process. In this embodiment, the length extending along the first direction X of the first spacer wall 210 a may be smaller than the length extending along the first direction X of the second spacer wall 210 b. In this embodiment, the first spacers 210a and the second spacers 210b may be formed in multiples and arranged alternately along the second direction Y, but the invention is not limited thereto.

In this embodiment, the hard mask layer 210 exposed by the first mask pattern 234 and the second mask pattern 280 can be removed by dry etching, and the first spacer 210 a and the second spacer 210 a can be formed. After 210b, the second mask pattern 280 , the remaining third material layer 270 , the remaining etch stop layer 220 and the remaining first mask pattern 234 may be removed.

Next, please refer to FIG. 11A and FIG. 11B at the same time, using the first spacer 210a and the second spacer 210b as a mask, the conductor layer 200 is patterned to form a connection structure CS including the first wire 200a and the second wire 200b. , wherein the second wire 200b has a pad pattern CP. In this embodiment, the length L1' of the first wire 200a in the first direction X may be smaller than the length L2' of the second wire 200b in the first direction X. In this embodiment, the first wires 200a and the second wires 200b may be formed in multiples and arranged alternately along the second direction Y, but the invention is not limited thereto. In this way, viewed from the top view direction of the substrate 100, the first conductive wires 200a and the second conductive wires 200b can be arranged in a staggered manner, so that the ends of the first conductive wires 200a and the second conductive wires 200b are spaced apart from each other. The short circuit problem caused by the wire end cutting process or the etching loading effect makes the semiconductor device have good electrical performance.

In this embodiment, the method of removing the conductor layer 200 exposed by the first spacer 210a and the second spacer 210b may be dry etching, and after forming the first wire 200a and the second wire 200b, the first The spacer 210a and the second spacer 210b are removed.

In this embodiment, the second wire 200b may have a first line segment S1 adjacent to the first wire 200a and a second line segment S2 extending from the first line segment S1 along the first direction X, and the pad pattern CP may Located at the second line segment S2. In some embodiments, the pad pattern CP may also be located at the first line segment S1. In some embodiments, the first line segment S1 of the second wire 200b can be defined as a line segment that is flush with the first wire 200a when viewed in the second direction Y in FIG. 11A , and the second line segment S2 of the second wire 200b can be It is defined as a portion extending from the first line segment S1 along the first direction X, but the present invention is not limited thereto.

In some embodiments, the steps shown in FIGS. 9A and 9B can also be omitted, and the subsequent steps shown in FIGS. 10A , 10B, 11A and 11B can be performed using the first mask pattern 234 as a mask. In this way, since the height H1 of the second portion P2 of the first segment 234a of the first mask pattern 234 and the third portion P3 of the curved segment 234c is not enough to block the film layer to be removed by the subsequent etching process, the formed The connection structure (not shown) may also include a first wire and a second wire extending in the first direction longer than the first wire, and the pad pattern may be formed on the second wire by another process as the aforementioned process.

Then, please refer to FIG. 12A and FIG. 12B at the same time, a dielectric layer 300 covering the first wire 200a and the second wire 200b is formed on the element area AA of the substrate 100, and a contact pad pattern CP is formed in the dielectric layer 300 The contact window opening O. The dielectric layer 300 may include a spin-on dielectric (SOD), but the present invention is not limited thereto. The contact opening O can be formed, for example, by the following steps. First, a patterned mask (not shown) is formed on the dielectric layer 300 . Next, the dielectric layer 300 exposed by the patterned mask is removed to form a contact window opening O exposing a portion of the second conductive line 200b. Then, the patterned mask is removed. In some embodiments, the dielectric layer 300 exposed by the patterned mask may be removed by dry etching, but the invention is not limited thereto.

Afterwards, referring to FIG. 13A and FIG. 13B , the conductive material is filled into the contact opening O to form the contact C. In this embodiment, the contact window C can be electrically connected to the second wire 200b. The conductive material can be, for example, metal, metal alloy, metal nitride, metal silicide, or a combination thereof. In some exemplary embodiments, metals and metal alloys may be, for example, copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), platinum (Pt), chromium (Cr), molybdenum (Mo) or its alloys. The metal nitride can be, for example, titanium nitride, tungsten nitride, tantalum nitride, silicon tantalum nitride, silicon titanium nitride, silicon tungsten nitride or combinations thereof. The metal silicide can be, for example, tungsten silicide, titanium silicide, cobalt silicide, zirconium silicide, platinum silicide, molybdenum silicide, copper silicide, nickel silicide or combinations thereof. The contact C may include a barrier layer 310 and a conductive layer 312 . The contact window C can be formed through the following steps. Firstly, a barrier layer 310 is formed on the surface of the contact opening O. Next, a conductive layer 312 is formed on the barrier layer 310 . The material of the barrier layer 310 can be, for example, titanium nitride. The material of the conductive layer 312 can be, for example, metal, metal alloy, metal nitride, metal silicide or a combination thereof. In some exemplary embodiments, metals and metal alloys may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof. The metal nitride can be, for example, titanium nitride, tungsten nitride, tantalum nitride, silicon tantalum nitride, silicon titanium nitride, silicon tungsten nitride or combinations thereof. The metal silicide is, for example, tungsten silicide, titanium silicide, cobalt silicide, zirconium silicide, platinum silicide, molybdenum silicide, copper silicide, nickel silicide or combinations thereof.

Hereinafter, the semiconductor element of this embodiment will be described with reference to FIGS. 13A and 13B. It should be noted that although the manufacturing method of the semiconductor element in this embodiment is manufactured using the above-mentioned manufacturing method as an example, the manufacturing method of the semiconductor element in this embodiment is not limited thereto.

Please refer to FIG. 13A and FIG. 13B at the same time, the semiconductor device may include a connection structure CS including a first wire 200a and a second wire 200b. The first wire 200a may be disposed on the device area AA of the substrate 100 and extend along the first direction X. Referring to FIG. The second wire 200b may be disposed on the device area AA of the substrate 100 and extend along the first direction X. Referring to FIG. The first conductive wires 200a and the second conductive wires 200b are arranged alternately along the second direction Y different from the first direction X, and at the end of the connection structure CS, the length of the first conductive wires 200a in the first direction X can be less than the length of the second wire 200b in the first direction X.

In this embodiment, the connection structure CS may include a pad pattern CP. The pad pattern CP may be disposed on the second wire 200b. Each second wire 200b has a first line segment S1 and a second line segment S2 (as shown in FIG. 11A ), wherein the first line segment S1 is located between two adjacent first wires 200a, and the second line segment S2 starts from the A segment S1 extends along the first direction X. The pad pattern CP may be disposed on the first line segment S1 or the second line segment S2.

To sum up, in the above-mentioned embodiment of the semiconductor device and the manufacturing method thereof, by spacing the ends of the first wire and the second wire from each other, it is possible to effectively avoid the wire end cutting process or the etching load effect. The short circuit problem caused by other influences makes the semiconductor element have good electrical performance.

100: base 110: Conductor pattern 110a: first paragraph 110b: Second paragraph 110c: curved section 120: Patterned mask 130: the first wire 132: second wire 132a, S1: the first line segment 132b, S2: the second line segment 140: Pad 200: conductor layer 200a: first wire 200b: second wire 210: hard mask layer 210a: first spacer 210b: second spacer 220: etch stop layer 230: the first material layer 232: Patterning the first material layer 234: The first mask pattern 232a, 234a: first paragraph 232b, 234b: the second paragraph 232c, 234c: bending section 240, 260: patterned mask layer 250: second material layer 252: Patterning the second material layer 270: third material layer 272: Lower mask layer 274: Upper mask layer 280: Second mask pattern 300: dielectric layer 310: barrier layer 312: conductive layer AA: component area C: contact window CS: Connection Structure CP: Pad pattern H1, H2, H3: Height L1, L2, L1’, L2’: Length O: contact window opening P1: part one P2: Part Two P3: the third part P4: Part Four Pa, Pb: part PP: pattern Wa: crest Wb: valley X: first direction Y: the second direction

1 to 2 are schematic partial top views of a method for manufacturing a semiconductor device according to an embodiment of the present invention. 3A to 13A are schematic partial top views of a method for manufacturing a semiconductor device according to another embodiment of the present invention. 3B to 13B are schematic cross-sectional views along the line I-I' in FIGS. 3A to 13A, respectively.

200a: first wire

200b: second wire

300: dielectric layer

310: barrier layer

312: conductive layer

C: contact window

CP: Pad pattern

CS: Connection Structure

X: first direction

Y: the second direction

Claims (10)

A semiconductor element, comprising: a connection structure, including: at least one first wire disposed on an element region of a substrate and extending along a first direction; and at least one second wire disposed on the element region of the substrate and extending along the first direction, wherein at the end of the connection structure, the length of the at least one first wire in the first direction is smaller than the length of the at least one second wire in the first direction length, wherein the at least one first conducting wire includes a plurality of first conducting wires, the at least one second conducting wire includes a plurality of second conducting wires, and the plurality of first conducting wires is different from the plurality of second conducting wires along The second directions in the first direction are arranged alternately with each other, and the plurality of second conducting wires are spaced apart from each other. The semiconductor device according to claim 1, further comprising: a pad disposed on the at least one second wire, wherein the at least one second wire has a first line adjacent to the at least one first wire segment and a second segment extending from the first segment along the first direction, and the pad is disposed on the first segment or the second segment. A method of manufacturing a semiconductor element, comprising: forming a plurality of conductor patterns on an element region of a substrate, each conductor pattern including a first section and a second section parallel to each other and extending along a first direction and connecting the first section and the curved section of the second section, and the plurality of conductor patterns are arranged along a second direction different from the first direction; covering the plurality of conductor patterns with a patterned mask with a wavy outline , the patterned mask exposes the curved segment and a portion of the first segment adjacent to the curved segment; and removing the exposed curved segment and the first segment of the patterned mask The portion of the segment adjacent to the curved segment to form a connection structure comprising a plurality of first wires and a plurality of second wires, wherein the plurality of first wires and the plurality of second wires are along the The second directions are arranged alternately with each other, the plurality of second conducting wires are spaced apart from each other, and at the end of the connecting structure, the length of the plurality of first conducting wires in the first direction is shorter than the plurality of first conducting wires The length of the second wire in the first direction. The method of manufacturing a semiconductor element according to claim 3, wherein crests of the wavy profile are located on the second segment, and troughs of the wavy profile are located on the first segment. The method for manufacturing a semiconductor device according to claim 3, further comprising: forming a plurality of pads on the plurality of second wires, wherein each second wire has a first line segment and a second line segment, and the first line segment A line segment is located between two adjacent first wires, the second line segment extends from the first line segment along the first direction, and the pad is formed on the first line segment or on the second line segment. A method of manufacturing a semiconductor device, comprising: A conductor layer, a hard mask layer, and a first mask pattern are sequentially formed on the device area of the substrate, and the first mask pattern includes a first section and a second section parallel to each other and extending along a first direction and connecting the A curved section of the first section and the second section, wherein the first section includes a first portion and a second portion, and the curved section includes a third portion and a fourth portion adjacent to the second portion, wherein The heights of the second part and the third part are smaller than the heights of the first part, the fourth part and the second section; the first mask pattern is used as a mask, and the hard mask the curtain layer is patterned to form a first spacer and a second spacer, wherein the length of the first spacer extending in a first direction is less than the length of the second spacer extending in the first direction; and The first spacer and the second spacer are masks, and the conductor layer is patterned to form a connection structure including a first wire and a second wire, wherein at the end of the connection structure, The length of the first conductive wire extending in the first direction is smaller than the length of the second conductive wire extending in the first direction, wherein the first mask pattern is formed in multiples and along a direction different from that of the first mask pattern. One direction is arranged in a second direction, so that when the hard mask layer is subsequently patterned, the first spacers and the second spacers are formed in multiples and arranged alternately along the second direction , and subsequently when patterning the conductor layer, the first wires and the second wires are formed in multiples and arranged alternately along the second direction, and the plurality of second wires are spaced apart from each other open. The method for manufacturing a semiconductor element as claimed in item 6, wherein the connection structure further includes a pad pattern, wherein the step of forming the pad pattern includes: Before forming the first spacer and the second spacer, a second mask pattern is formed on the second segment of the first mask pattern; with the first mask pattern and the The second mask pattern is a mask patterning the hard mask layer to form first spacers and second spacers, wherein the second spacers have the same pattern as the pad pattern; and Using the first spacer and the second spacer as a mask, the conductor layer is patterned to form the first wire and the second wire having the pad pattern. The method for manufacturing a semiconductor element according to claim 7, wherein the second wire has a first segment adjacent to the first wire and a first segment extending from the first segment along the first direction. Two line segments, and the pad pattern is located at the first line segment or at the second line segment. The method for manufacturing a semiconductor element according to claim 7, further comprising: after forming the first wire and the second wire, forming a wire covering the first wire and the second wire on the element region of the substrate a dielectric layer of the second wire; and forming a contact window connected with the pad pattern in the dielectric layer. The method for manufacturing a semiconductor element as claimed in item 6, wherein the ratio of the heights of the second portion and the third portion to the heights of the first portion, the fourth portion, and the second segment is between Between 0 and 1/3.

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