TWI776648B - Integrated circuit product and chip floorplan arrangement thereof - Google Patents

Abstract

An integrated circuit product includes: a first chip to a twelfth chip. The first to fourth chips are respectively arranged in a first quadrant, a fourth quadrant, a third quadrant, and a second quadrant of the integrated circuit product, and the first chip is adjacent to the second chip and the fourth chip. The fifth to eighth chips are respectively arranged in the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant of the integrated circuit product, and any two of the fifth to eighth chips are not adjacent. The ninth to twelfth chips are respectively arranged in the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant of the integrated circuit product, and any two of the ninth to twelfth chips are not adjacent.

Description

Integrated circuit products and their chip arrangements

The present invention relates to the packaging of integrated circuits (ICs), and more particularly to the floorplan arrangement of chips and/or chiplets (hereinafter collectively referred to as chips) of the integrated circuit packaging.

Advanced packaging is the current trend for integrated circuits. However, poor die layout can have the following disadvantages: wasted area (resulting in an oversized and uncompetitive finished product), poor die heat dissipation (reduces die performance), difficult output and/or input routing (increases packaging difficulty) And/or the relative position of the wafers is not ideal (causing waste of wafer pins). Accordingly, there is a need for a wafer arrangement that addresses at least one of the aforementioned problems.

In view of this, how to alleviate or eliminate the lack of wafer arrangement in the above-mentioned related fields is a problem to be solved.

This specification provides an embodiment of an integrated circuit product, which includes: a first chip; a second chip; a third chip; a fourth chip; a fifth chip; a sixth chip; a seventh chip; An eighth wafer; a ninth wafer; a tenth wafer; an eleventh wafer; and a twelfth wafer. The first chip, the second chip, the third chip, and the fourth chip are located in a first quadrant, a fourth quadrant, a third quadrant, and a second quadrant of the integrated circuit product, respectively, and The first wafer is adjacent to the second wafer and the fourth wafer. The fifth die, the sixth die, the seventh die, and the eighth die are located in the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant of the integrated circuit product, respectively, and The fifth wafer, the sixth wafer, the seventh wafer, and the first wafer No two of the eight wafers are contiguous. The ninth chip, the tenth chip, the eleventh chip, and the twelfth chip are located in the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant of the integrated circuit product, respectively , and any two of the ninth wafer, the tenth wafer, the eleventh wafer, and the twelfth wafer are not adjacent.

This specification further provides an embodiment of an integrated circuit product, which includes: a first chip; a second chip; a third chip; a fourth chip; a fifth chip; a sixth chip; and a seventh chip ; an eighth wafer; a ninth wafer; a tenth wafer; an eleventh wafer; and a twelfth wafer. The first wafer, the second wafer, the third wafer, the fourth wafer, the fifth wafer, the sixth wafer, the seventh wafer, and the eighth wafer, the ninth wafer, the tenth wafer , the eleventh wafer, and the twelfth wafer are substantially in a plane. If the first chip is rotated ninety degrees on the plane relative to a center of the integrated circuit product, the first chip and the second chip or the fourth chip substantially overlap, and if the first chip When the wafer is rotated 180 degrees relative to the center on the plane, the first wafer and the third wafer are substantially overlapped. If the fifth wafer is rotated ninety degrees relative to the center on the plane, the fifth wafer substantially overlaps the sixth wafer or the eighth wafer, and if the fifth wafer is opposite in the plane Rotating one hundred and eighty degrees from the center, the fifth wafer and the seventh wafer are substantially overlapped. If the ninth wafer is rotated ninety degrees relative to the center in the plane, the ninth wafer substantially overlaps the tenth wafer or the twelfth wafer, and if the ninth wafer is in the plane Rotated one hundred and eighty degrees relative to the center, the ninth wafer and the eleventh wafer are substantially overlapped.

One of the advantages of the above embodiments is that the substrate area can be fully utilized, chip pin waste is avoided, and communication between logic chips is easy.

Another advantage of the above-mentioned embodiment is that the substrate area can be fully utilized, the complexity of the photomask can be simplified, and the competitiveness of integrated circuit products can be improved.

Other advantages of the present invention will be explained in more detail in conjunction with the following description and drawings.

100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200: Integrated circuit products

112, 312, 412: the first logic chip

114, 314, 414: Second logic chip

116, 316, 416: The third logic chip

118, 318, 418: Fourth logic chip

122, 322, 422, 722, 922, 1022: the first memory chip

124, 332, 432, 724, 932, 1032: the second memory chip

126, 324, 424, 726, 924, 1024: the third memory chip

128, 334, 434, 728, 934, 1034: Fourth memory chip

132, 442: The first other chip

134, 444: The second other chip

136, 446: The third other chip

138, 448: the fourth other chip

150: Substrate

PL: Plane

152: Micro bumps

154: bump

140:Intermediary Layer

102: First side

104: Second side

106: Third Side

108: Fourth side

101, 301, 401: Center

Q1: Quadrant 1

Q4: Fourth quadrant

Q3: The third quadrant

Q2: The second quadrant

326, 426, 926, 1026: Fifth memory chip

336, 436, 936, 1036: sixth memory chip

328, 428, 928, 1028: seventh memory chip

338, 438, 938, 1038: Eighth memory chip

W1, W2, W3, W4: Width

L1, L2, L3, L4: length

FIG. 1 is a schematic diagram of a simplified chip arrangement of an integrated circuit product according to an embodiment of the present invention.

FIG. 2 shows a simplified side view of an integrated circuit product according to an embodiment of the present invention.

3 shows a simplified side view of an integrated circuit product according to another embodiment of the present invention.

FIG. 4 shows the distribution of center points and quadrants of the integrated circuit product of the present invention.

FIG. 5 is a schematic diagram of a simplified chip arrangement of an integrated circuit product according to another embodiment of the present invention.

6 is a schematic diagram of a simplified chip arrangement of an integrated circuit product according to another embodiment of the present invention.

7 is a schematic diagram of a simplified chip arrangement of an integrated circuit product according to another embodiment of the present invention.

8 is a schematic diagram of a simplified chip arrangement of an integrated circuit product according to another embodiment of the present invention.

FIG. 9 is a schematic diagram of a simplified chip arrangement of an integrated circuit product according to another embodiment of the present invention.

10 is a schematic diagram of a simplified chip arrangement of an integrated circuit product according to another embodiment of the present invention.

11 is a schematic diagram of a simplified chip arrangement of an integrated circuit product according to another embodiment of the present invention.

12 is a schematic diagram of a simplified chip arrangement of an integrated circuit product according to another embodiment of the present invention.

13 is a schematic diagram of a simplified chip arrangement of an integrated circuit product according to another embodiment of the present invention.

14 is a schematic diagram of a simplified chip arrangement of an integrated circuit product according to another embodiment of the present invention.

15 is a schematic diagram of a simplified chip arrangement of an integrated circuit product according to another embodiment of the present invention.

The embodiments of the present invention will be described below with reference to the relevant drawings. In the drawings, the same reference numbers refer to the same or similar elements or method flows.

FIG. 1 is a schematic diagram of a simplified chip arrangement of an integrated circuit product according to an embodiment of the present invention. The integrated circuit product 100 includes a first logic chip 112 , a second logic chip 114 , a third logic chip 116 , a fourth logic chip 118 , a first memory chip 122 , a second memory chip 124 , and a third memory chip 126 , a fourth memory chip 128 , a first other chip 132 , a second other chip 134 , a third other chip 136 , and a fourth other chip 138 . 1 shows a top view of an integrated circuit product 100, and FIGS. 2 and 3 each show a simplified side view (cross-section along AA' of FIG. 1) of an integrated circuit product according to an embodiment of the present invention. In the embodiment of FIG. 2 , the integrated circuit product 100 includes a substrate 150 , and the logic chips, the memory chips, and the other chips shown in FIG. 1 are located on the same plane PL above the substrate 150 . There are a plurality of micro-bumps 152 between the substrate 150 and logic chips, memory chips, and other chips, and a plurality of bumps 154 under the substrate 150 . In the embodiment of FIG. 3 , the integrated circuit product 100 includes an interposer 140 over which the logic chips, the memory chips, and the other chips shown in FIG. 1 are located. There are a plurality of micro-bumps 152 between the interposer 140 and the substrate 150 , and a plurality of bumps 154 under the substrate 150 . The first logic chip 112 , the second logic chip 114 , the third logic chip 116 , and the fourth logic chip 118 may be logic circuits with computing capabilities, such as a system on a chip (SoC). The logic chip can access the memory chip to implement a specific function, for example, the logic chip implements the function by reading and executing code or program instructions stored in the memory chip.

Back to Figure 1. The integrated circuit product 100 has a first side 102 , a second side 104 , a third side 106 , and a fourth side 108 . The four sides of the integrated circuit product 100 may be the four sides of the substrate 150 . The integrated circuit product 100 also has a center 101 . One side of the first logic die 112 is substantially overlapped with the second side 104 (ie, one side of the first logic die 112 is substantially aligned with the second side 104 ), that is, the first logic die 112 is adjacent The second side 104 . Similarly, one side of the second logic die 114 substantially overlaps the third side 106, one side of the third logic die 116 substantially overlaps the fourth side 108, and one side of the fourth logic die 118 substantially overlaps the first side 102 overlapping.

Similarly, the respective edges of the first other wafer 132, the second other wafer 134, the third other wafer 136, and the fourth other wafer 138 are associated with the first edge 102, the second edge 104, the third edge 106, and the fourth edge, respectively. Edges 108 substantially overlap.

Similarly, the respective sides of the first memory chip 122 , the second memory chip 124 , the third memory chip 126 , and the fourth memory chip 128 are connected to the first side 102 , the second side 104 , and the third side 106 , respectively. , and the fourth side 108 substantially overlap. In addition, since the first memory chip 122, the second memory chip 124, the third memory chip 126, and the fourth memory chip 128 are arranged at the four corners of the integrated circuit product 100, the first memory chip 122. The other sides of the second memory chip 124, the third memory chip 126, and the fourth memory chip 128 are further connected to the second side 104, the third side 106, the fourth side 108, and the first side 102, respectively substantially overlap.

As shown in FIG. 1 , the first logic die 112 is adjacent to the second logic die 114 and the fourth logic die 118 , the second logic die 114 is adjacent to the first logic die 112 and the third logic die 116 , and the third logic die 116 is adjacent to the The second logic die 114 and the fourth logic die 118 are adjacent, and the fourth logic die 118 is adjacent to the first logic die 112 and the third logic die 116 . In some embodiments, the vertices of the first logic die 112 , the second logic die 114 , the third logic die 116 , and the fourth logic die 118 contact each other at the center 101 . However, the first memory chip 122, the second memory chip 124, the third memory chip 126, and the fourth memory chip 128 are not adjacent to each other, and the first other chip 132, the second other chip 134, the third other chip The wafer 136 and the fourth other wafer 138 are not adjacent to each other.

In some embodiments, the first logic chip 112 , the second logic chip 114 , the third logic chip 116 , and the fourth logic chip 118 have substantially the same area, and the first memory chip 122 , the second memory chip 124 , the The third memory chip 126, and the fourth memory chip The areas of the wafers 128 are substantially the same, and the areas of the first other wafer 132, the second other wafer 134, the third other wafer 136, and the fourth other wafer 138 are substantially the same.

In some embodiments, the components of the first logic chip 112 , the second logic chip 114 , the third logic chip 116 , and the fourth logic chip 118 are substantially the same, and the first memory chip 122 , the second memory chip 124 , the components of the third memory chip 126 , and the fourth memory chip 128 are substantially the same, and the components of the first other chip 132 , the second other chip 134 , the third other chip 136 , and the fourth other chip 138 substantially the same. The aforementioned constituent elements include, but are not limited to, transistors, resistors, capacitors, and/or inductors. In other embodiments, the components of the first logic chip 112 , the second logic chip 114 , the third logic chip 116 , and the fourth logic chip 118 are the same in type and quantity. The components of the memory chip 124, the third memory chip 126, and the fourth memory chip 128 are the same in type and number, and the first other chip 132, the second other chip 134, the third other chip 136, and the first other chip 132, the third other chip 136, and the third The components of the four other chips 138 are the same in type and quantity.

In some embodiments, the first other die 132, the second other die 134, the third other die 136, and the fourth other die 138 are input/output die, including input/output circuits, the first logic die 112, the second other die 138 The logic die 114, the third logic die 116, and the fourth logic die 118 transmit or receive signals using input/output circuits. In other embodiments, the first other chip 132, the second other chip 134, the third other chip 136, and the fourth other chip 138 are silicon chips that do not contain any circuits.

Please refer to Figure 1 and Figure 4. The integrated circuit product 100 is divided into four quadrants by the X axis and the Y axis that are perpendicular to each other, and the X axis and the Y axis intersect at the center 101 . The first chip group (including the first logic chip 112, the first memory chip 122, and the first other chip 132) is located in the first quadrant Q1; the second chip group (including the second logic chip 114, the second memory chip 114) The chip 124, and the second other chip 134) are located in the fourth quadrant Q4; the third chip group (including the third logic chip 116, the third memory chip 126, and the third other chip 136) is located in the third quadrant Q3; Four chip groups (including the fourth logic chip 118, the fourth chip The memory chip 128, and the fourth other chip 138) are located in the second quadrant Q2. The relative positions of the first logic chip 112 and the first memory chip 122 are equal to that of the second logic chip 114 (the third logic chip 116, or the fourth logic chip 118) and the second memory chip 124 (the third memory chip 126, or the relative position of the fourth memory chip 128); the relative position of the first logic chip 112 and the first other chip 132 is equal to the relative position of the second logic chip 114 (the third logic chip 116, or the fourth logic chip 118) and the second other chip The relative position of the chip 134 (the third other chip 136, or the fourth other chip 138); the relative position of the first memory chip 122 and the first other chip 132 is equal to the second memory chip 124 (the third memory chip 126, or the fourth memory chip 128) and the relative position of the second other chip 134 (the third other chip 136, or the fourth other chip 138).

If the first wafer group is rotated 90 degrees clockwise relative to the center 101 on the plane PL, the first wafer group and the second wafer group substantially overlap (ie, the first logic wafer 112 and the second logic wafer 114 appear rotational symmetry, the first memory chip 122 and the second memory chip 124 exhibit rotational symmetry, and the first other chip 132 and the second other chip 134 exhibit rotational symmetry, wherein the rotational symmetry center is the center 101 and the rotation angle is 90 Spend). Similarly, if the first wafer group is rotated 90 degrees counterclockwise or 270 degrees clockwise with respect to the center 101 on the plane PL, the first wafer group and the fourth wafer group substantially overlap.

If the first wafer group is rotated 180 degrees relative to the center 101 on the plane PL, the first wafer group and the third wafer group substantially overlap. In other words, the first chip group and the third chip group are point symmetric with respect to the center 101 (ie, the first logic chip 112 and the third logic chip 116 are point symmetric, the first memory chip 122 and the third The memory chip 126 is point-symmetrical, and the first other chip 132 and the third other chip 136 are point-symmetrical, and the center of symmetry is the center 101). Similarly, the second wafer group and the fourth wafer group are point-symmetrical with respect to the center 101 .

In other words, in some embodiments, the first chip group, the second chip group, the third chip group, and the fourth chip group are each a constituent unit of the integrated circuit product 100, That is, the first logic chip 112, the second logic chip 114, the third logic chip 116, and the fourth logic chip 118 can access or be coupled to the first memory chip 122, the second memory chip 124, The third memory chip 126 and the fourth memory chip 128, and the first logic chip 112, the second logic chip 114, the third logic chip 116, and the fourth logic chip 118 can be respectively coupled to the first other chip 132 , a second other wafer 134 , a third other wafer 136 , and a fourth other wafer 138 . One of the advantages of such an arrangement is that the external (ie external to the integrated circuit product 100 ) pins of the first logic die 112 (the second logic die 114 , the third logic die 116 , or the fourth logic die 118 ) can be arranged On the second side 104 (the third side 106 , the fourth side 108 , or the first side 102 ), the internal pins (eg, with the first memory chip 122 , the second memory chip 124 , the third memory chip 122 , the third memory chip The pins of the chip 126, the fourth other chip 128, the first other chip 132, the second other chip 134, the third other chip 136, or the fourth other chip 138) can be arranged in the same position as the memory chip or the other chip. on the adjacent edge. In this way, because the chip arrangement of the integrated circuit product 100 is simple (just rotate the first chip group by 90 degrees, 180 degrees, and 270 degrees), different areas of the integrated circuit product 100 can use the same light It can be manufactured with a cover, which greatly simplifies the process and does not waste pins.

In some embodiments, by arranging the heat-prone portions of the first logic die 112 , the second logic die 114 , the third logic die 116 , and the fourth logic die 118 close to the side of the integrated circuit product 100 , The heat dissipation performance of the integrated circuit product 100 is improved. In addition, because the first logic chip 112, the second logic chip 114, the third logic chip 116, and the fourth logic chip 118 are adjacent to each other, it is easier to implement the first logic chip 112, the second logic chip 114, and the third logic chip Connections between die 116, and fourth logic die 118 (eg, through interposer 140 and/or substrate 150), in other words, first logic die 112, second logic die 114, third logic die 116, and fourth logic die Communication (eg, exchanging data) and collaborative processing between logic chips 118 become easier to achieve.

In other embodiments, the first wafer group, the second wafer group, the third wafer group, and the fourth chip group are each a square; more specifically, taking the first chip group in FIG. 1 as an example, W1+W2=L1+L2, wherein W1 is the first memory chip 122 and the first other chip The width of the die 132, W2 is the width of the first logic die 112, L1 is the length of the first memory die 122, L2 is the length of the first other die 132, and the length of the first logic die 112 is L1+L2. Furthermore, since the first chip group, the second chip group, the third chip group, and the fourth chip group are all square, the integrated circuit product 100 is also a square.

FIG. 5 is a schematic diagram of a simplified chip arrangement of an integrated circuit product according to another embodiment of the present invention. FIG. 5 shows a top view of the integrated circuit product 200 . The integrated circuit product 200 is similar to the integrated circuit product 100 except that the first memory chip 122 and the first other chip 132 exchange positions, the second memory chip 124 and the second other chip 134 exchange positions, and the third memory chip 126 exchanges positions with the third other chip 136 , and the fourth memory chip 128 exchanges positions with the fourth other chip 138 . As such, in the embodiment of FIG. 2, the first other die 132, the second other die 134, the third other die 136, and the fourth other die 138 are arranged at the four corners of the integrated circuit product 200; thus , the respective sides of the first other chip 132 , the second other chip 134 , the third other chip 136 , and the fourth other chip 138 are respectively connected with the first side 102 , the second side 104 , the third side 106 , and the fourth side 108 Substantially overlap, and the other side of each further substantially overlaps with the second side 104 , the third side 106 , the fourth side 108 , and the first side 102 , respectively.

6 is a schematic diagram of a simplified chip arrangement of an integrated circuit product according to another embodiment of the present invention. FIG. 6 shows a top view of the integrated circuit product 300 . The integrated circuit product 300 includes a first logic chip 312 , a second logic chip 314 , a third logic chip 316 , a fourth logic chip 318 , a first memory chip 322 , a second memory chip 332 , and a third memory chip 324 , a fourth memory chip 334 , a fifth memory chip 326 , a sixth memory chip 336 , a seventh memory chip 328 , and an eighth memory chip 338 . The chip arrangement and features of the integrated circuit product 300 are similar to those of the integrated circuit product 100 and the integrated circuit product 200, except that one chip group of the integrated circuit product 300 includes one logic chip. A computer chip and 2 memory chips, but no other chips.

In some embodiments, the first chip group (including the first logic chip 312, the first memory chip 322, and the second memory chip 332), the second chip group (including the second logic chip 314, the third memory chip 324, and fourth memory chip 334), third chip group (including third logic chip 316, fifth memory chip 326, and sixth memory chip 336), and fourth chip group ( The fourth logic chip 318, the seventh memory chip 328, and the eighth memory chip 338) are each a square. Taking the first chip group as an example, W1+W3=L1+L3, where W1 is the width of the first memory chip 322 and the second memory chip 332 , W3 is the width of the first logic chip 312 , and L1 is the width of the first logic chip 312 . The length of a memory chip 322, L3 is the length of the second memory chip 332, and the length of the first logic chip 312 is L1+L3. If the first wafer group is rotated 90 degrees, 180 degrees, and 270 degrees clockwise with respect to the center 301 , each wafer of the rotated first wafer group will be respectively aligned with the second wafer group and the third wafer group. , and the corresponding chips in the fourth chip group substantially overlap (the first logic chip 312, the second logic chip 314, the third logic chip 316, and the fourth logic chip 318 correspond to each other, the first memory chip 322, The third memory chip 324, the fifth memory chip 326, and the seventh memory chip 328 correspond to each other, and the second memory chip 332, the fourth memory chip 334, the sixth memory chip 336, and the eighth memory chip The bulk wafers 338 correspond to each other). Furthermore, since the first chip group, the second chip group, the third chip group, and the fourth chip group are all square, the integrated circuit product 300 is also a square.

For the first chip group, the first logic chip 312 can access the first memory chip 322 and the second memory chip 332 . The same is true for other chip groups, so it is not repeated here.

In some embodiments, the components of the first logic chip 312 , the second logic chip 314 , the third logic chip 316 , and the fourth logic chip 318 are substantially the same, and the first memory chip 322 , the third memory chip 324 The components of the fifth memory chip 326 and the seventh memory chip 328 are substantially the same, and the second memory chip 332, the fourth memory chip 334, the sixth memory chip 336, and the eighth memory chip Group of 338 The components are substantially the same. The aforementioned constituent elements include, but are not limited to, transistors, resistors, capacitors, and/or inductors. In other embodiments, the components of the first logic chip 312 , the second logic chip 314 , the third logic chip 316 , and the fourth logic chip 318 are the same in type and quantity. The components of the memory chip 324 , the fifth memory chip 326 , and the seventh memory chip 328 are the same in type and number, and the second memory chip 332 , the fourth memory chip 334 , and the sixth memory chip 336 , and the constituent elements of the eighth memory chip 338 are the same in type and quantity.

In some embodiments, the 8 memory chips in FIG. 6 are identical; in other words, L1=L3.

In other embodiments, the eight memory chips in FIG. 6 are high bandwidth memory generation 3 (HBM3), and W1=L1=L3.

7 is a schematic diagram of a simplified chip arrangement of an integrated circuit product according to another embodiment of the present invention. FIG. 7 shows a top view of the integrated circuit product 400 . The integrated circuit product 400 includes a first logic chip 412 , a second logic chip 414 , a third logic chip 416 , a fourth logic chip 418 , a first memory chip 422 , a second memory chip 432 , and a third memory chip 424 , the fourth memory chip 434, the fifth memory chip 426, the sixth memory chip 436, the seventh memory chip 428, the eighth memory chip 438, the first other chip 442, the second other chip 444, the third Other wafer 446 , and fourth other wafer 448 . The chip arrangement and features of the integrated circuit product 400 are similar to those of the integrated circuit product 100 and the integrated circuit product 200, except that one chip group of the integrated circuit product 400 includes one logic chip, two memory chips, and 1 other chip.

In some embodiments, the first chip group (including the first logic chip 412, the first memory chip 422, the second memory chip 432, and the first other chip 442), the second chip group (including the second The logic chip 414, the third memory chip 424, the fourth memory chip 434, and the second other chip 444), the third chip group (including the third logic chip 316, the fifth memory chip 326, the sixth memory chip chip 336, and the third other chip 446), and the fourth chip group (including the fourth logic chip 318, the seventh memory chip The chip 328, the eighth memory chip 338, and the fourth other chip 448) are each a square. Taking the first chip group as an example, W1+W4=L1+L3+L4, wherein W1 is the width of the first memory chip 422, the second memory chip 432, and the first other chip 442, and W4 is the first The width of the logic chip 412, L1 is the length of the first memory chip 422, L3 is the length of the second memory chip 432, L4 is the length of the first other chip 442, and the length of the first logic chip 412 is L1+L3 +L4. If the first wafer group is rotated 90 degrees, 180 degrees, and 270 degrees clockwise with respect to the center 401 , each wafer of the rotated first wafer group will be respectively aligned with the second wafer group and the third wafer group. , and the corresponding chips in the fourth chip group substantially overlap (the first logic chip 412, the second logic chip 414, the third logic chip 416, and the fourth logic chip 418 correspond to each other, the first memory chip 422, The third memory chip 424, the fifth memory chip 426, and the seventh memory chip 428 correspond to each other, the second memory chip 432, the fourth memory chip 434, the sixth memory chip 436, and the eighth memory chip The wafers 438 correspond to each other, and the first other wafer 442, the second other wafer 444, the third other wafer 446, and the fourth other wafer 448 correspond to each other). Furthermore, since the first chip group, the second chip group, the third chip group, and the fourth chip group are all square, the integrated circuit product 400 is also a square.

For the first chip group, the first logic chip 412 can access the first memory chip 422 and the second memory chip 432 . The same is true for other chip groups, so it is not repeated here.

In some embodiments, the components of the first logic chip 412 , the second logic chip 414 , the third logic chip 416 , and the fourth logic chip 418 are substantially the same, and the first memory chip 422 , the third memory chip 424 The components of the fifth memory chip 426 and the seventh memory chip 428 are substantially the same, the second memory chip 432 , the fourth memory chip 434 , the sixth memory chip 436 , and the eighth memory chip 438 The constituent elements are substantially the same, and the constituent elements of the first other chip 442, the second other chip 444, the third other chip 446, and the fourth other chip 448 are substantially the same. The aforementioned constituent elements include, but are not limited to, transistors, resistors, capacitors, and/or inductors. in other In the embodiment, the components of the first logic chip 412 , the second logic chip 414 , the third logic chip 416 , and the fourth logic chip 418 are the same in type and quantity, and the first memory chip 422 , the third memory chip 418 424, the fifth memory chip 426, and the seventh memory chip 428 have the same types and numbers of components, the second memory chip 432, the fourth memory chip 434, the sixth memory chip 436, and the eighth memory chip 432 The constituent elements of the memory chip 438 are the same in type and quantity, and the constituent elements of the first other chip 442 , the second other chip 444 , the third other chip 446 , and the fourth other chip 448 are the same in type and quantity.

In some embodiments, the 8 memory chips in FIG. 7 are identical; in other words, L1=L3.

In the embodiment of FIG. 7 , the second memory chip 432 , the fourth memory chip 434 , the sixth memory chip 436 , and the eighth memory chip 438 are arranged at four corners of the integrated circuit product 400 . A memory chip 422 (the third memory chip 424, the fifth memory chip 426, or the seventh memory chip 428) is arranged on the second memory chip 432 (the fourth memory chip 434, the sixth memory chip 428) 436, or the eighth memory chip 438) and the first other chip 442 (the second other chip 444, the third other chip 446, or the fourth other chip 448).

8 is a schematic diagram of a simplified chip arrangement of an integrated circuit product according to another embodiment of the present invention. FIG. 8 shows a top view of an integrated circuit product 500 . The integrated circuit product 500 is similar to the integrated circuit product 400, except that the first other die 442, the second other die 444, the third other die 446, and the fourth other die 448 are arranged in four of the integrated circuit product 500 corner, the second memory chip 432 (the fourth memory chip 434, the sixth memory chip 436, or the eighth memory chip 438) is arranged on the first memory chip 422 (the third memory chip 424, the fifth between the memory chip 426, or the seventh memory chip 428) and the first other chip 442 (the second other chip 444, the third other chip 446, or the fourth other chip 448).

FIG. 9 is a schematic diagram of a simplified chip layout of an integrated circuit product according to another embodiment of the present invention. intention. FIG. 9 shows a top view of an integrated circuit product 600 . The integrated circuit product 600 is similar to the integrated circuit product 400, except that the first other die 442 (the second other die 444, the third other die 446, or the fourth other die 448) is arranged on the first memory die 422 ( The third memory chip 424, the fifth memory chip 426, or the seventh memory chip 428) and the second memory chip 432 (the fourth memory chip 434, the sixth memory chip 436, or the eighth memory chip 438) between.

The memory chips in FIGS. 1 and 5 to 9 are high bandwidth memory generation 3 (HBM3) of the third generation, and their shape is square. However, the above-mentioned memory chip may also be a high bandwidth memory generation 2 (HBM2), as shown in FIGS. 10-15 (corresponding to FIGS. 1 and 5-9 respectively). The first memory chip 722 , the second memory chip 724 , the third memory chip 726 , the fourth memory chip 728 of the integrated circuit product 700 and the integrated circuit product 800 , the first memory chip of the integrated circuit product 900 chip 922, second memory chip 932, third memory chip 924, fourth memory chip 934, fifth memory chip 926, sixth memory chip 936, seventh memory chip 928, eighth memory chip 938. Integrated circuit product 1000, integrated circuit product 1100, and first memory chip 1022, second memory chip 1032, third memory chip 1024, fourth memory chip 1034, and first memory chip 1022 of integrated circuit product 1200 The fifth memory chip 1026, the sixth memory chip 1036, the seventh memory chip 1028, and the eighth memory chip 1038 are the second-generation high-bandwidth memories. The descriptions of FIGS. 10 to 15 may correspond to the descriptions of FIGS. 1 and 5 to 9 respectively, and thus are not repeated here.

In addition, in other embodiments, the memory chips in FIGS. 10-15 may be enhanced high bandwidth memory generation 2 (Enhanced high bandwidth memory generation 2).

To sum up, the chip arrangement proposed in this case can make the chips closely arranged in the integrated circuit product, so that the substrate area can be fully utilized to improve the competitiveness of the integrated circuit product. Furthermore, the chips on the integrated circuit product are arranged in a rotationally symmetrical and/or point-symmetrical manner. In addition to avoiding the waste of pins, it is also beneficial to use the same mask to manufacture different parts of the integrated circuit product, thus simplifying the complexity of the mask.

From another perspective, by arranging the chips on the integrated circuit product in the aforementioned rotational symmetry and/or point symmetry, semiconductor manufacturers can use the same set of masks to manufacture an integrated circuit with an area nearly 4 times the size Therefore, the manufacturing cost of integrated circuit products can be greatly reduced.

Please note that the above-mentioned arrangement of the chips on the integrated circuit product is only an exemplary embodiment, and is not intended to limit the actual implementation of the present invention. For example, in certain embodiments, the aforementioned logic chips, memory chips, and/or other chips may be modified to exhibit line symmetry with respect to the central axis of the integrated circuit product (through the center and perpendicular to either side). Arranged in the four quadrants of integrated circuit products.

Certain terms are used in the description and the scope of the claims to refer to specific elements, and those skilled in the art may refer to the same elements by different terms. This specification and the scope of the patent application do not use the difference in name as a way to distinguish elements, but use the difference in function of the elements as a criterion for distinguishing. The "comprising" mentioned in the description and the scope of the patent application is an open-ended term, and should be interpreted as "including but not limited to". In addition, the term "coupled" herein includes any direct and indirect means of connection. Therefore, if it is described in the text that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection such as wireless transmission or optical transmission, or through other elements or connections. The means is indirectly electrically or signally connected to the second element.

The descriptions of "and/or" used in the specification include any combination of one or more of the listed items. In addition, unless otherwise specified in the specification, any term in the singular also includes the meaning in the plural.

The size and relative size of certain elements in the drawings may be exaggerated, or the shapes of certain elements may be simplified so as to more clearly convey the contents of the embodiments. Therefore, unless otherwise specified by the applicant, the shape, size, relative size and relative position of each element in the drawings The setting and the like are only for convenience of description, and should not be used to limit the patent scope of the present invention. Furthermore, the present invention may be embodied in many different forms, and the present invention should not be limited to the embodiments set forth in this specification in explaining the present invention.

For the convenience of description, some descriptions related to relative positions in space may be used in the specification to describe the function of an element in the drawings or the relative spatial relationship between the element and other elements. For example, "above", "above", "below", "below", "above...", "below...", "Up", "Down", etc. Those with ordinary knowledge in the technical field should understand that these descriptions related to relative positions in space not only include the orientation of the described elements in the drawings, but also include the use and operation of the described elements. , or various pointing relationships during assembly. For example, if the drawing is turned upside down, the element originally described as "on" will become "under". Therefore, the description method of "on" used in the specification includes two different pointing relationships of "under" and "on". Similarly, the word "upward" used here includes two different pointing relationships of "upward" and "downward".

In the description and the scope of the patent application, if it is described that the first element is located on, above the second element, connected, joined, coupled to or connected with the second element, it means that the first element can be directly Being located on, directly connected to, directly joined, or directly coupled to the second element may also mean that other elements exist between the first element and the second element. In contrast, if it is described that the first element is directly on, directly connected, directly joined, directly coupled, or directly connected to the second element, it means that no other element exists between the first element and the second element .

The above are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

100: Integrated circuit products

112: The first logic chip

114: Second logic chip

116: Third logic chip

118: Fourth logic chip

122: first memory chip

124: Second memory chip

126: Third memory chip

128: Fourth memory chip

132: The first other chip

134: Second other chip

136: The third other chip

138: Fourth other chip

102: First side

104: Second side

106: Third Side

108: Fourth side

101: Center

W1, W2: width

L1, L2: length

Claims (27)

An integrated circuit product (100; 200; 300; 400; 500; 600), comprising: a first chip (112; 312; 412); a second chip (114; 314; 414); a third chip (116; 316; 416); a fourth wafer (118; 318; 418); a fifth wafer (122; 322; 422); a sixth wafer (124; 324; 424); a seventh wafer (126 ; 326; 426); an eighth wafer (128; 328; 428); a ninth wafer (132; 332; 432); a tenth wafer (134; 334; 434); an eleventh wafer (136; 336; 436); and a twelfth wafer (138; 338; 438); wherein, the first wafer (112; 312; 412), the second wafer (114; 314; 414), the third wafer ( 116; 316; 416), and the fourth chip (118; 318; 418) are respectively located in a first quadrant, a fourth quadrant, a third quadrant, and a second quadrant of the integrated circuit product, and the The first wafer (112; 312; 412) is adjacent to the second wafer (114; 314; 414) and the fourth wafer (118; 318; 418); the fifth wafer (122; 322; 422), the sixth wafer (122; 322; 422), the fourth wafer (118; 318; 418) The chip (124; 324; 424), the seventh chip (126; 326; 426), and the eighth chip (128; 328; 428) are respectively located in the first quadrant and the fourth quadrant of the integrated circuit product , the third quadrant, and the second quadrant, and the fifth wafer (122; 322; 422), the sixth wafer (124; 324; 424), the seventh wafer (126; 326; 426), and Neither of the eighth wafers (128; 328; 428) are adjacent and the ninth wafer (132; 332; 432), the tenth wafer (134; 334; 434), the eleventh wafer (136; 336; 436), and the twelfth wafer (138; 338) ; 438) are respectively located in the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant of the integrated circuit product, and the ninth chip (132; 332; 432), the tenth chip ( 134; 334; 434), the eleventh wafer (136; 336; 436), and the twelfth wafer (138; 338; 438) are not adjacent; wherein, the first wafer (112; 312) ; 412), the second chip (114; 314; 414), the third chip (116; 316; 416), and the fourth chip (118; 318; 418) are logic chips, and the the areas and components are substantially the same; and the fifth wafer (122; 322; 422), the sixth wafer (124; 324; 424), the seventh wafer (126; 326; 426), and the eighth wafer (128; 328; 428) are memory chips, and the areas and components of these memory chips are substantially the same. The integrated circuit product (100; 200; 300; 400; 500; 600) according to claim 1, wherein the first wafer (112; 312; 412), the second wafer (114; 314; 414) , the third wafer (116; 316; 416), the fourth wafer (118; 318; 418), the fifth wafer (122; 322; 422), the sixth wafer (124; 324; 424), the The seventh wafer (126; 326; 426), the eighth wafer (128; 328; 428), the ninth wafer (132; 332; 432), the tenth wafer (134; 334; 434), the tenth wafer (134; 334; 434) A wafer (136; 336; 436), and the twelfth wafer (138; 338; 438) are substantially in the same plane, the first wafer (112; 312; 412) and the third wafer (116; 316; 416) Shows point symmetry with respect to one center (101; 301; 401) of the integrated circuit product (100; 200; 300; 400; 500; 600), the second wafer (114; 314; 414) and the first The four wafers (118; 318; 418) exhibit point symmetry with respect to the center (101; 301; 401), the fifth The wafer (122; 322; 422) and the seventh wafer (126; 326; 426) exhibit point symmetry with respect to the center (101; 301; 401), the sixth wafer (124; 324; 424) and the eighth wafer (124; 324; 424) The wafer (128; 328; 428) exhibits point symmetry with respect to the center (101; 301; 401), the ninth wafer (132; 332; 432) and the eleventh wafer (136; 336; 436) are relative to the The center (101; 301; 401) exhibits point symmetry, and the tenth wafer (134; 334; 434) and the twelfth wafer (138; 338; 438) exhibit points relative to the center (101; 301; 401) symmetry. The integrated circuit product (100; 200; 300; 400; 500; 600) according to claim 1, wherein the first wafer (112; 312; 412), the second wafer (114; 314; 414) , the third chip (116; 316; 416), and the fourth chip (118; 318; 418) and a second side of the integrated circuit product (100; 200; 300; 400; 500; 600) respectively (104), a third side (106), a fourth side (108), and a first side (102) are adjacent. The integrated circuit product (100; 200; 300; 400; 500; 600) according to claim 3, wherein the fifth wafer (122; 322; 422), the sixth wafer (124; 324; 424) , the seventh chip (126; 326; 426), and the eighth chip (128; 328; 428) and the first side of the integrated circuit product (100; 200; 300; 400; 500; 600) respectively (102), the second side (104), the third side (106), and the fourth side (108) are adjacent. The integrated circuit product (100) of claim 4, wherein the fifth chip (122), the sixth chip (124), the seventh chip (126), and the eighth chip (128) are more respectively adjacent to the second side (104), the third side (106), the fourth side (108), and the first side (102) of the integrated circuit product (100). The integrated circuit product (100; 200; 300; 400; 500; 600) according to claim 3, wherein the ninth wafer (132; 332; 432), the tenth wafer (134; 334; 434) , the eleventh chip (136; 336; 436), and the twelfth chip (138; 338; 438) and the integrated circuit product (100; 200; 300; 400; 500; 600) of the first side (102), the second side (104), the third side (106), and the fourth side (108) are adjacent. The integrated circuit product (200; 300; 400; 600) according to claim 6, wherein the ninth wafer (132; 332; 432), the tenth wafer (134; 334; 434), the tenth wafer (132; 332; 432), the A chip (136; 336; 436), and the twelfth chip (138; 338; 438) and the second side (104), the second side (104) of the integrated circuit product (200; 300; 400; 600), respectively The third side (106), the fourth side (108), and the first side (102) are adjacent. The integrated circuit product (300; 400; 500; 600) according to claim 1, wherein the ninth wafer (332; 432), the tenth wafer (334; 434), the eleventh wafer (336) ; 436), and the twelfth chip (338; 438) is a memory chip. The integrated circuit product (400; 500; 600) of claim 8, further comprising: a thirteenth chip (442); a fourteenth chip (444); a fifteenth chip (446); and A sixteenth wafer (448); wherein the thirteenth wafer (442), the fourteenth wafer (444), the fifteenth wafer (446), and the sixteenth wafer (448) are respectively located in the the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant; and the fifth wafer (422), the sixth wafer (424), the seventh wafer (426), and the eighth wafer (428), the ninth wafer (432), the tenth wafer (434), the eleventh wafer (436), the twelfth wafer (438), the thirteenth wafer (442), the tenth wafer (442) The fourth wafer (444), the fifteenth wafer (446), and the sixteenth wafer (448) have the same width (W1). The integrated circuit product (400; 500) of claim 9, wherein the fifth wafer (422) is located between the ninth wafer (432) and the thirteenth wafer (442), the sixth wafer (442) (424) at the tenth wafer (434) and the fourteenth wafer (444) between the seventh wafer (426) and the eleventh wafer (436) and the fifteenth wafer (446), and the eighth wafer (428) between the twelfth wafer (438) and the fifteenth wafer (446) Between sixteenth wafers (448). The integrated circuit product (400) of claim 10, wherein the ninth wafer (432), the tenth wafer (434), the eleventh wafer (436), and the twelfth wafer (438) ) are respectively located at the four corners of the integrated circuit product (400). The integrated circuit product (500) of claim 10, wherein the thirteenth wafer (442), the fourteenth wafer (444), the fifteenth wafer (446), and the sixteenth wafer (448) are respectively located at the four corners of the integrated circuit product (500). The integrated circuit product (600) of claim 9, wherein the thirteenth wafer (442) is located between the fifth wafer (422) and the ninth wafer (432), the fourteenth wafer (432) 444) between the sixth wafer (424) and the tenth wafer (434), the fifteenth wafer (446) between the seventh wafer (426) and the eleventh wafer (436), and The sixteenth wafer (448) is located between the eighth wafer (428) and the twelfth wafer (438). An integrated circuit product (100; 200; 300; 400; 500; 600), comprising: a first chip (112; 312; 412); a second chip (114; 314; 414); a third chip (116; 316; 416); a fourth wafer (118; 318; 418); a fifth wafer (122; 322; 422); a sixth wafer (124; 324; 424); a seventh wafer (126 ; 326; 426); an eighth wafer (128; 328; 428); a ninth wafer (132; 332; 432); a tenth wafer (134; 334; 434); an eleventh wafer (136; 336; 436); and a twelfth wafer (138; 338; 438); wherein, the first wafer (112; 312; 412), the second wafer (114; 314; 414), the third wafer (116; 316; 416) , the fourth wafer (118; 318; 418), the fifth wafer (122; 322; 422), the sixth wafer (124; 324; 424), the seventh wafer (126; 326; 426), and the eighth wafer (128; 328; 428), the ninth wafer (132; 332; 432), the tenth wafer (134; 334; 434), the eleventh wafer (136; 336; 436), and The twelfth chip (138; 338; 438) is substantially located on a plane (PL); if the first chip (112; 312; 412) is on the plane relative to the integrated circuit product (100; 200; 300; 400; 500; 600) one of the centers (101; 301; 401) rotates ninety degrees, then the first wafer (112; 312; 412) and the second wafer (114; 314; 414) or the first wafer (112; 312; 412) Four wafers (118; 318; 418) substantially overlap, and if the first wafer (112; 312; 412) is rotated one hundred and eighty degrees on the plane relative to the center (101; 301; 401), then The first wafer (112; 312; 412) and the third wafer (116; 316; 416) substantially overlap; if the fifth wafer (122; 322; 422) is on the plane relative to the center (101 301; 401) is rotated ninety degrees, then the fifth wafer (122; 322; 422) and the sixth wafer (124; 324; 424) or the eighth wafer (128; 328; 428) are substantially overlapped, And if the fifth wafer (122; 322; 422) is rotated by one hundred and eighty degrees relative to the center (101; 301; 401) on the plane, the fifth wafer (122; 322; 422) and the the seventh wafer (126; 326; 426) substantially overlaps; and if the ninth wafer (132; 332; 432) is rotated ninety degrees on the plane relative to the center (101; 301; 401), the The ninth wafer (132; 332; 432) and the tenth wafer (134; 334; 434) or the twelfth wafer (138; 338; 438) substantially overlap, and if the ninth wafer (132; 332; 432) is rotated one hundred and eighty degrees on the plane relative to the center (101; 301; 401), the ninth wafer ( 132; 332; 432) and the eleventh wafer (136; 336; 436) substantially overlap; wherein the first wafer (112; 312; 412), the second wafer (114; 314; 414), the The third chip (116; 316; 416) and the fourth chip (118; 318; 418) are logic chips, and the areas and components of these logic chips are substantially the same; and the fifth chip (122; 322 ; 422), the sixth chip (124; 324; 424), the seventh chip (126; 326; 426), and the eighth chip (128; 328; 428) are memory chips, and the memory The area and constituent elements of the wafers are substantially the same. The integrated circuit product (100; 200; 300; 400; 500; 600) of claim 14, wherein the first wafer (112; 312; 412) and the second wafer and the fourth wafer (118) ; 318; 418) adjoining, and the second wafer (114; 314; 414) adjoins the first wafer and the third wafer (116; 316; 416). The integrated circuit product (100; 200; 300; 400; 500; 600) according to claim 14, wherein the fifth wafer (122; 322; 422), the sixth wafer (124; 324; 424) , the seventh wafer (126; 326; 426), and the eighth wafer (128; 328; 428) are not adjacent, and the ninth wafer (132; 332; 432), the tenth wafer ( 134; 334; 434), the eleventh wafer (136; 336; 436), and the twelfth wafer (138; 338; 438) are not adjacent. The integrated circuit product (100; 200; 300; 400; 500; 600) according to claim 14, wherein the first wafer (112; 312; 412), the second wafer (114; 314; 414) , the third chip (116; 316; 416), and the fourth chip (118; 318; 418) and a second side of the integrated circuit product (100; 200; 300; 400; 500; 600) respectively (104), a third side (106), a fourth side (108), and a first side (102) are adjacent. The integrated circuit product (100; 200; 300; 400; 500; 600) according to claim 17, wherein the fifth wafer (122; 322; 422), the sixth wafer (124; 324; 424) , the seventh chip (126; 326; 426), and the eighth chip (128; 328; 428) and the first side of the integrated circuit product (100; 200; 300; 400; 500; 600) respectively (102), the second side (104), the third side (106), and the fourth side (108) are adjacent. The integrated circuit product (100) of claim 18, wherein the fifth chip (122), the sixth chip (124), the seventh chip (126), and the eighth chip (128) are more respectively adjacent to the second side (104), the third side (106), the fourth side (108), and the first side (102) of the integrated circuit product (100). The integrated circuit product (100; 200; 300; 400; 500; 600) according to claim 17, wherein the ninth wafer (132; 332; 432), the tenth wafer (134; 334; 434) , the eleventh chip (136; 336; 436), and the twelfth chip (138; 338; 438) and the first chip of the integrated circuit product (100; 200; 300; 400; 500; 600) respectively One side (102), the second side (104), the third side (106), and the fourth side (108) are adjacent. The integrated circuit product (200; 300; 400; 600) according to claim 20, wherein the ninth wafer (132; 332; 432), the tenth wafer (134; 334; 434), the tenth wafer (134; 334; 434), the A chip (136; 336; 436), and the twelfth chip (138; 338; 438) and the second side (104), the second side (104) of the integrated circuit product (200; 300; 400; 600), respectively The third side (106), the fourth side (108), and the first side (102) are adjacent. The integrated circuit product (300; 400; 500; 600) of claim 14, wherein the ninth wafer (332; 432), the tenth wafer (334; 434), the eleventh wafer (336) ; 436), and the twelfth chip (338; 438) is a memory chip. The integrated circuit product (400; 500; 600) according to claim 22, further comprising: a thirteenth chip (442); A fourteenth wafer (444); a fifteenth wafer (446); and a sixteenth wafer (448); wherein the thirteenth wafer (442), the fourteenth wafer (444), the The fifteenth wafer (446), and the sixteenth wafer (448) are substantially located in the plane (PL); and the fifth wafer (422), the sixth wafer (424), the seventh wafer (426), and the eighth wafer (428), the ninth wafer (432), the tenth wafer (434), the eleventh wafer (436), the twelfth wafer (438), the thirteenth wafer (442) ), the fourteenth wafer (444), the fifteenth wafer (446), and the sixteenth wafer (448) have the same width (W1). The integrated circuit product (400; 500) of claim 23, wherein the fifth wafer (422) is located between the ninth wafer (432) and the thirteenth wafer (442), the sixth wafer (442) (424) is located between the tenth wafer (434) and the fourteenth wafer (444), and the seventh wafer (426) is located between the eleventh wafer (436) and the fifteenth wafer (446) , and the eighth wafer (428) is located between the twelfth wafer (438) and the sixteenth wafer (448). The integrated circuit product (400) of claim 24, wherein the ninth wafer (432), the tenth wafer (434), the eleventh wafer (436), and the twelfth wafer (438) ) are respectively located at the four corners of the integrated circuit product (400). The integrated circuit product (500) of claim 24, wherein the thirteenth wafer (442), the fourteenth wafer (444), the fifteenth wafer (446), and the sixteenth wafer (448) are respectively located at the four corners of the integrated circuit product (500). The integrated circuit product (600) of claim 23, wherein the thirteenth wafer (442) is located between the fifth wafer (422) and the ninth wafer (432), the fourteenth wafer (432) 444) is located between the sixth wafer (424) and the tenth wafer (434), and the fifteenth wafer (446) is located between the seventh wafer (426) and the eleventh wafer (436), and the sixteenth wafer (448) is located between the eighth wafer (428) and the twelfth wafer (438).

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