TWI767267B - Memory controller - Google Patents

Abstract

A memory controller is provided. The memory controller is suitable for a pseudo static random access memory. The memory controller includes a mode register, a mode register write controller and a latency controller. The mode register is configured to generate a latency control signal according to a write instruction signal. The mode register write controller is configured to generate the write instruction signal during a mode register write operation and generate a write mask signal according to a chip selection signal. The latency controller generates a latency type control signal according to the latency control signal and the write mask signal.

Description

memory controller

The present invention relates to a memory technology, and more particularly, to a memory controller.

Pseudo Static Random Access Memory (Pseudo Static Random Access Memory, hereinafter referred to as pSRAM) uses DRAM as a memory cell array to store data, and redesigns the access interface of DRAM to make it compatible with the access interface of SRAM , and the characteristics of access timing are similar to SRAM.

In the conventional memory technology, the memory controller is usually used to determine whether a self refresh collision occurs in the pSRAM, and the memory controller is used to control the delay control signals LTCX2_t generated by the mode register and The state of the delay type control signal LTNCY2_t generated by the delay controller is used to set the delay type of the access delay (latency) of the pSRAM.

1A and FIG. 1B are signal timing diagrams of a conventional pseudo-static random access memory. Please refer to FIG. 1A and FIG. 1B , the pSRAM performs a Mode Register Write (MRW) operation and operates in the write mode. When the memory controller determines that the self-refresh collision has not occurred, and When the access delay of the pSRAM is adjusted to different delay types, the signal timing diagrams corresponding to the pSRAM respectively.

In the scenario of FIG. 1A, when the memory controller wants to adjust the access delay of the pSRAM from 2 times the delay time to 1 times the delay time (ie, switching the delay type from the fixed delay type to the variable delay type When changing the delay type), the inverting chip select signal (Chip Select Signal) CS# of the pSRAM is set to a low voltage level, and the delay control signal LTCX2_t and the delay type control signal LTNCY2_t at this time will be set to high first voltage level.

However, in the prior art, because the response time of the time interval (ie, tCSH and tCSHI) in which the inverting chip selection signal CS# transitions from the low voltage level to the high voltage level is too short, the delay control signal LTCX2_t and the delay The type control signal LTNCY2_t cannot immediately transition to the low voltage level in the time interval.

In this case, the read/write data capture signal RWDS output by the Read/Write Data Strobe pin (hereinafter referred to as the RWDS pin) may be written in the memory cell array. , a malfunction occurs.

In contrast, in the situation of FIG. 1B , when the memory controller wants to adjust the access delay of the pSRAM from 1 times the delay time to 2 times the delay time (that is, changing the delay type from the variable delay type When the state is converted to the fixed delay type), the inverting chip select signal CS# of the pSRAM is set to a low voltage level, and the delay control signal LTCX2_t and the delay type control signal LTNCY2_t at this time will be first Set to low voltage level.

However, the delay control signal LTCX2_t and the delay type control signal LTNCY2_t cannot be used because the response time of the time interval (ie, tCSH and tCSHI) during which the inverting chip select signal CS# transitions from the low voltage level to the high voltage level is too short. Immediately transition to the high voltage level during the time interval.

In this case, the read/write data capture signal RWDS output by the RWDS pin may also malfunction when the memory cell array performs the write operation.

In other words, in the case of FIG. 1A and FIG. 1B , the read/write data capture signal RWDS output by the RWDS pin will be affected by the short time interval (ie, tCSH and tCSHI), so that the read/write data capture signal RWDS is too short. The fetching of the signal RWDS will cause a malfunction during the writing operation of the memory cell array, which will cause the pSRAM to fail to write valid data under correct timing control, and cause the overall memory system to fail to operate normally.

The present invention provides a memory controller, which can effectively reduce the malfunction of the memory controller when setting the delay pattern of the access delay of the pSRAM, so as to improve the operation quality of the memory system.

The memory controller of the present invention is suitable for pseudo-static random access memory. The memory controller includes a mode register, a mode register write controller, and a delay controller. The mode register is used for generating the delay control signal according to the write instruction signal. The mode register write controller is used for generating a write instruction signal during the mode register write operation, and generates a write mask signal according to the chip selection signal. The delay controller is coupled to the mode register and the mode register write controller, and generates a delay type control signal according to the delay control signal and the write mask signal.

Based on the above, the memory controller according to the embodiments of the present invention can perform a write operation on the memory cell array, and when the inverting chip select signal is in a disabled state, the delay controller can be based on a high voltage level The write mask signal of the control delay type control signal is maintained in the enabled state, so that the read and write data capture signal output by the RWDS pin can not malfunction during the write operation of the memory cell array, and then Effectively improve the operating quality of the memory system.

FIG. 2 is a schematic diagram illustrating a pseudo-static random access memory according to an embodiment of the present invention. 2, the pSRAM 200 includes a memory controller 300, an input/output interface, an X decoder circuit, a Y decoder circuit, a memory cell array, a data latch circuit, and a data transmission path. The pSRAM 200 of this embodiment may be, for example, an xSPI pSRAM or a HyperRAM pSRAM with an Expanded Serial Peripheral Interface (Expanded Serial Peripheral Interface, hereinafter referred to as xSPI) or a HyperBus™ interface as its access interface, but the invention is not limited thereto.

In this embodiment, the I/O interface of the pSRAM 200 can provide the chip select signal CS_t to the memory controller 300 according to the inverted chip select signal CS#. Wherein, when the chip selection signal CS_t is enabled (eg, at a high voltage level), the pSRAM 200 can perform a data access operation. When the chip selection signal CS_t is disabled (eg, at a low voltage level), the pSRAM 200 cannot perform data access operations. Wherein, in this embodiment, the states of the chip selection signal CS_t and the inverted chip selection signal CS# may be complementary.

It should be noted that the detailed functions of the memory controller 300, the I/O interface, the X decoder circuit, the Y decoder circuit, the memory cell array, the data latch circuit and the data transmission path shown in FIG. In the implementation, sufficient teachings, suggestions and implementation descriptions can be obtained from ordinary knowledge in the technical field.

FIG. 3 is a schematic circuit diagram illustrating the memory controller shown in FIG. 2 according to an embodiment of the present invention. Referring to FIG. 3 , the memory controller 300 can be applied to the memory controller of the pSRAM 200 shown in FIG. 2 . In this embodiment, the memory controller 300 includes a mode register 310 , a mode register write controller 320 , a delay controller 330 and a self-refresh controller 340 .

In this embodiment, the mode register 310 receives the write instruction signal MRW_t and the mode register write data DATA, and generates the delay control signal LTCX2_t according to the write instruction signal MRW_t and the mode register write data DATA. Wherein, when the delay control signal LTCX2_t is in an enabled state (eg, a high voltage level), the delay control signal LTCX2_t can instruct the delay controller 330 to generate a delay type for controlling the access delay of the pSRAM 200 to be the first type Control signal LTNCY2_t. On the other hand, when the delay control signal LTCX2_t is in a disabled state (eg, a low voltage level), the delay control signal LTCX2_t can instruct the delay controller 330 to generate a delay type for controlling the access delay of the pSRAM 200 to be the second type state control signal LTNCY2_t.

The self-refresh controller 340 receives the self-refresh request RE and the chip selection signal CS_t, and generates the self-refresh wait signal WAITSR_t according to the self-refresh request RE and the chip selection signal CS_t.

In this embodiment, the mode register write controller 320 includes a first-stage circuit 321 and a second-stage circuit 322 . The mode register write controller 320 can receive the command COM through the first stage circuit 321, and according to the command COM, generate the write instruction signal MRW_t in the mode register write (MRW) operation. In this way, the mode register write controller 320 can determine whether the pSRAM 200 performs the MRW operation through the write instruction signal MRW_t.

On the other hand, the second stage circuit 322 is coupled to the first stage circuit 321 . The second stage circuit 322 can generate the write mask signal WAITMRW_t according to the write instruction signal MRW_t, the chip selection signal CS_t and the initialization control signal CHRDY_t.

Specifically, the second-stage circuit 322 includes a latch 323, a pulse width adjustment circuit 325, a logic gate AND, and an inverter INV7. Wherein, the logic gate AND of this embodiment may be, for example, an AND gate (AND Gate), but the present invention is not limited thereto.

In this embodiment, the pulse width adjustment circuit 325 can receive the chip selection signal CS_t, and adjust the pulse width of the chip selection signal CS_t to generate the complementary control signal CSD_t and the inverted control signal CSD_c. In addition, the latch 323 is coupled to the pulse width adjustment circuit 325 and the first stage circuit 321 . The latch 323 can generate the output signal n01 according to the control signal CSD_t, the inverted control signal CSD_c and the write instruction signal MRW_t.

On the other hand, the first input terminal of the logic gate AND is coupled to the pulse width adjustment circuit 325 to receive the control signal CSD_t, and the second input terminal of the logic gate AND is coupled to the latch 323 to receive the output signal n01. In addition, the logic gate AND can perform AND operation on the control signal CSD_t and the output signal n01 to generate the write mask signal WAITMRW_t at the output end of the logic gate AND. In addition, the input terminal of the inverter INV7 receives the initialization control signal CHRDY_t, and the output terminal of the inverter INV7 is coupled to the latch 323 .

Regarding the detailed circuit structure of the pulse width adjustment circuit 325 , the pulse width adjustment circuit 325 includes inverters INV1 , INV4 , a plurality of inverters connected in series (eg, INV2 and INV3 ), and a NAND gate (NAND gate) NAND. In detail, the input terminal of the inverter INV1 receives the chip selection signal CS_t. The input terminals of the plurality of inverters connected in series are coupled to the output terminal of the inverter INV1. The first input terminal of the inversion gate NAND is coupled to the output terminal of the inverter INV1, and the second input terminal of the inversion gate NAND is coupled to the output terminals of the plurality of inverters connected in series. In addition, the inversion gate NAND can perform inversion and operation on the signal generated by the inverter INV1 and the signals generated by the plurality of inverters connected in series, so as to generate a control signal at the output end of the inversion gate NAND CSD_t.

In addition, the input terminal of the inverter INV4 is coupled to the output terminal of the inversion gate NAND to receive the control signal CSD_t. In addition, the inverter INV4 can perform an inversion operation on the control signal CSD_t, so as to generate an inversion control signal CSD_c at the output end of the inverter INV4.

Regarding the detailed circuit structure of the latch 323 , the latch 323 includes a tri-state inverter 324 , an inverter INV5 and a NOR gate NOR. Wherein, the tri-state inverter 324 in this embodiment may be composed of an inverter INV6, a P-type transistor M1 and an N-type transistor M2.

In detail, in the tri-state inverter 324, the input terminal of the inverter INV6 can receive the write indication signal MRW_t. The P-type transistor M1 can be controlled by the control signal CSD_t, and the N-type transistor M2 can be controlled by the inverted control signal CSD_c. In addition, the latch 323 can enable the tri-state inverter 324 according to the state of the control signal CSD_t and the inversion control signal CSD_c, so that the P-type transistor M1 and the N-type transistor M2 can be respectively in accordance with the control signal CSD_t and inversion The phase control signal CSD_c is turned on, so that the inverter INV6 can generate an inverted write instruction signal MRW_t at the output end.

In addition, the first input terminal of the inverting-OR gate NOR is coupled to the output terminal of the inverter INV7, and the second input terminal of the inverting-OR gate NOR is coupled to the output terminal of the inverter INV6. In addition, the inversion-OR gate NOR can perform an inverse-OR operation on the signal generated by the inverter INV7 and the inverted write-instructing signal MRW_t, so as to generate an output signal n01 at the output end of the inversion-OR gate NOR. In addition, the inverter INV5 is coupled between the output terminal of the inverting-OR gate NOR and the second input terminal of the inverting-ORing gate NOR. Therefore, the latch 323 can feed back the output signal n01 to the second input terminal of the inverting OR gate NOR through the inverter INV5.

It should be noted that the latch 323 , the tri-state inverter 324 and the pulse width adjustment circuit 325 in this embodiment can be a latch and a tri-state inverter known to those skilled in the art. And the pulse width adjustment circuit is implemented, the present invention is not limited to the above proposed circuit structure.

On the other hand, the delay controller 330 is coupled to the mode register 310 , the mode register write controller 320 and the self-refresh controller 340 . In this embodiment, the delay controller 330 can generate the delay type control signal LTNCY2_t according to the self-refresh wait signal WAITSR_t, the delay control signal LTCX2_t and the write mask signal WAITMRW_t.

It is worth mentioning that the delay controller 330 of this embodiment can control the access delay of the pSRAM 200 to be the first type or the second type through the delay type control signal LTNCY2_t. For example, when the delay type control signal LTNCY2_t is in an enabled state (eg, a high voltage level), the delay type of the access delay can be defined as a fixed delay type (corresponding to the first type) . When the delay type control signal LTNCY2_t is in a disabled state (eg, a low voltage level), the delay type of the access delay can be defined as a variable delay type (corresponding to the second type).

Further, in this embodiment, the first type may correspond to a first delay time, and the second type may correspond to a second delay time, and the first delay time is the first delay time 2 is an integer multiple of the delay time (for example, 2 times, but the present invention is not limited to this).

Regarding the detailed circuit structure of the delay controller 330 , the delay controller 330 includes a logic gate OR1 and a logic gate OR2 , wherein the logic gates OR1 and OR2 can be, for example, OR gates, but the invention is not limited thereto. Specifically, the first input terminal of the logic gate OR1 is coupled to the mode register 310 to receive the delay control signal LTCX2_t, and the second input terminal of the logic gate OR1 is coupled to the mode register write controller 320 to receive the delay control signal LTCX2_t. The write mask signal WAITMRW_t is received.

In addition, the first input terminal of the logic gate OR2 is coupled to the self-refresh controller 340 to receive the self-refresh wait signal WAITSR_t, and the second input terminal of the logic gate OR2 is coupled to the output terminal of the logic gate OR1. In addition, the logic gate OR2 can perform OR operation on the self-refresh waiting signal WAITSR_t and the signal output by the logic gate OR1, so as to generate the delay type control signal LTNCY2_t at the output end.

That is to say, in this embodiment, when any one of the self-refresh wait signal WAITSR_t, the delay control signal LTCX2_t and the write mask signal WAITMRW_t is set to be enabled (eg, a high voltage level), the delay controller 330 The access delay of the pSRAM 200 can be controlled to be the first type (ie, the fixed delay type) by the delay type control signal LTNCY2_t.

4 is a signal timing diagram illustrating when the memory controller controls the access delay of the pseudo-static random access memory to switch from a fixed delay type to a variable delay type according to an embodiment of the present invention. The embodiment of FIG. 4 assumes that the pSRAM 200 operates in the write mode and no self-refresh collision occurs.

Please refer to FIG. 2 to FIG. 4 at the same time. In this embodiment, when the pSRAM 200 operates at an initial time before startup (eg, power-on), the memory controller 300 does not perform the MRW operation, and the initialization control signal CHRDY_t can be is set to a disabled (eg, low voltage level) state. In this case, the latch 323 of the mode register write controller 320 can initialize the output signal n01 according to the disabled initialization control signal CHRDY_t, so that the output signal n01 is set to a low voltage at the initial time Alignment status.

Next, after the power-on operation of the pSRAM 200 is completed, the initialization control signal CHRDY_t can be set to an enabled state (eg, a high voltage level), and the state of the initialization output signal n01 is completed.

Next, when the pSRAM 200 operates in the time interval T11, the inverted chip selection signal CS# and the write instruction signal MRW_t are both set to a disabled (eg, low voltage level) state. At this time, the pulse width adjustment circuit 325 can generate a control signal CSD_t with a high voltage level and an inverted control signal CSD_c with a low voltage level according to the chip selection signal CS_t which is enabled (eg, a high voltage level).

In this case, the transistors M1 and M2 of the tri-state inverter 324 are respectively turned off according to the control signal CSD_t and the inverted control signal CSD_c, so that the latch 323 can latch the state of the output signal n01 ( That is, the state of the output signal n01 is maintained at the low voltage level). At the same time, the mode register write controller 320 can generate write disabled (eg, low voltage level) according to the control signal CSD_t with a high voltage level and the output signal n01 with a low voltage level Mask the signal WAITMRW_t.

It is worth mentioning that when the pSRAM 200 operates at the initial time of the time interval T11, the mode register write controller 320 can determine that the memory controller 300 is not performing the MRW operation according to the write instruction signal MRW_t.

Next, when the pSRAM 200 operates in the time interval T21 after the time interval T11 , the inverted chip selection signal CS# and the write instruction signal MRW_t are both set to the enabled (eg, high voltage level) state. At this time, the pulse width adjustment circuit 325 can generate a control signal CSD_t with a low voltage level and an inverted control signal CSD_c with a high voltage level according to the chip selection signal CS_t which is disabled (eg, a low voltage level).

In this case, the transistors M1 and M2 of the tri-state inverter 324 are turned on according to the control signal CSD_t and the inversion control signal CSD_c, respectively, so that the latch 323 can respond to the write instruction signal with a high voltage level The MRW_t and the initialization control signal CHRDY_t with a high voltage level generate an output signal n01 with a high voltage level. In addition, the mode register write controller 320 can generate the write mask signal WAITMRW_t which is disabled (eg, a low voltage level) according to the output signal n01 and the control signal CSD_t.

On the other hand, when the pSRAM 200 operates in the time interval T31 after the time interval T21, the memory cell array representing the pSRAM 200 can start to perform a write operation. At this time, the inverting chip selection signal CS# is set to a disabled state (eg, a low voltage level), and the write instruction signal MRW_t can be maintained at an enable (eg, a high voltage level) at the initial time of the time interval T31 )state. Therefore, the pulse width adjustment circuit 325 can generate the control signal CSD_t with a high voltage level and the inverted control signal CSD_c with a low voltage level according to the chip selection signal CS_t which is enabled (eg, a high voltage level).

In this case, the transistors M1 and M2 of the tri-state inverter 324 are respectively turned off according to the control signal CSD_t and the inverted control signal CSD_c, so that the latch 323 can latch the state of the output signal n01 ( That is, the state of the output signal n01 is maintained at the high voltage level).

At the same time, the mode register write controller 320 can generate a write that is enabled (eg, a high voltage level) according to the control signal CSD_t with a high voltage level and the output signal n01 with a high voltage level Mask the signal WAITMRW_t.

In other words, when the memory cell array of the pSRAM 200 performs the write operation (ie, the time interval T31 ), the delay controller 330 can generate an enabled delay type according to the write mask signal WAITMRW_t with a high voltage level The state control signal LTNCY2_t is used, so that the read and write data capture signal RWDS output by the RWDS pin does not malfunction when the memory cell array performs the write operation.

Besides, in this embodiment, the mode register write controller 320 may determine that the pSRAM 200 is performing the MRW operation at the initial time of the write operation in the memory cell array of the pSRAM 200 . In addition, since the mode register 310 will generate the disabled delay control signal LTCX2_t according to the write instruction signal MRW_t at this time, the memory controller 300 can perform the write operation when the memory cell array of the pSRAM 200 is written. , the access delay of the pSRAM 200 is set to a variable delay mode, and the delay mode control signal LTNCY2_t can still be maintained at a high voltage level.

Next, when the pSRAM 200 operates in the time interval T41 after the time interval T31, it indicates that the memory cell array of the pSRAM 200 has completed the writing operation. At this time, the inverting chip selection signal CS# is set to an enabled state (eg, a high voltage level), and the write instruction signal MRW_t is set to a disabled (eg, a low voltage level) state. Therefore, the pulse width adjustment circuit 325 can generate the control signal CSD_t with a low voltage level and the inverted control signal CSD_c with a high voltage level according to the chip selection signal CS_t which is disabled (eg, a low voltage level).

In this case, the transistors M1 and M2 of the tri-state inverter 324 are turned on according to the control signal CSD_t and the inversion control signal CSD_c, respectively, so that the latch 323 can respond to the write instruction signal with a low voltage level The MRW_t and the initialization control signal CHRDY_t with a high voltage level generate an output signal n01 with a low voltage level. In addition, the mode register write controller 320 can generate the write mask signal WAITMRW_t which is disabled (eg, a low voltage level) according to the output signal n01 and the control signal CSD_t.

5 is a signal timing diagram illustrating when the memory controller controls the access delay of the pseudo-static random access memory to switch from a variable delay type to a fixed delay type according to an embodiment of the present invention. The embodiment of FIG. 5 assumes that the pSRAM 200 operates in the write mode and no self-refresh collision occurs.

It should be noted that, in the embodiment shown in FIG. 5, the operation details of the pSRAM 200 operating in the time interval T12-T22 can be deduced by referring to the relevant description of the time interval T11-T21 in the embodiment shown in FIG. No longer.

2 , 3 and 5 , when the pSRAM 200 operates in a time interval T32 after the time interval T22 , the memory cell array of the pSRAM 200 can start to perform a write operation. At this time, the inverting chip selection signal CS# is set to a disabled state (eg, a low voltage level), and the write instruction signal MRW_t can be maintained at an enable (eg, a high voltage level) at the initial time of the time interval T32 )state. Therefore, the pulse width adjustment circuit 325 can generate the control signal CSD_t with a high voltage level and the inverted control signal CSD_c with a low voltage level according to the chip selection signal CS_t which is enabled (eg, a high voltage level).

In this case, the transistors M1 and M2 of the tri-state inverter 324 are respectively turned off according to the control signal CSD_t and the inverted control signal CSD_c, so that the latch 323 can latch the state of the output signal n01 ( That is, the state of the output signal n01 is maintained at the high voltage level).

At the same time, the mode register write controller 320 can generate a write that is enabled (eg, a high voltage level) according to the control signal CSD_t with a high voltage level and the output signal n01 with a high voltage level Mask the signal WAITMRW_t.

In other words, when the memory cell array of the pSRAM 200 performs the write operation (ie, the time interval T32 ), the delay controller 330 can generate an enabled delay type according to the write mask signal WAITMRW_t with a high voltage level The state control signal LTNCY2_t is used, so that the read and write data capture signal RWDS output by the RWDS pin does not malfunction when the memory cell array performs the write operation.

Besides, in this embodiment, the mode register write controller 320 may determine that the pSRAM 200 is performing the MRW operation at the initial time of the write operation in the memory cell array of the pSRAM 200 . In addition, since the mode register 310 will generate the enabled delay control signal LTCX2_t according to the write instruction signal MRW_t at this time, the memory controller 300 can perform the write operation when the memory cell array of the pSRAM 200 is written. , the access delay of the pSRAM 200 is set to a fixed delay type, and the delay type control signal LTNCY2_t can still be maintained at a high voltage level.

Next, when the pSRAM 200 operates in the time interval T42 after the time interval T32, it indicates that the memory cell array of the pSRAM 200 has completed the writing operation. At this time, the inverting chip selection signal CS# is set to an enabled state (eg, a high voltage level), and the write instruction signal MRW_t is set to a disabled (eg, a low voltage level) state. Therefore, the pulse width adjustment circuit 325 can generate the control signal CSD_t with a low voltage level and the inverted control signal CSD_c with a high voltage level according to the chip selection signal CS_t which is disabled (eg, a low voltage level).

In this case, the transistors M1 and M2 of the tri-state inverter 324 are turned on according to the control signal CSD_t and the inversion control signal CSD_c, respectively, so that the latch 323 can respond to the write instruction signal with a low voltage level The MRW_t and the initialization control signal CHRDY_t with a high voltage level generate an output signal n01 with a low voltage level. In addition, the mode register write controller 320 can generate the write mask signal WAITMRW_t which is disabled (eg, a low voltage level) according to the output signal n01 and the control signal CSD_t.

According to the descriptions of the above-mentioned embodiments in FIGS. 4 and 5 , it can be known that whether the memory controller 300 wants to convert the access delay of the pSRAM 200 from the variable delay type to the fixed delay type, or whether the memory controller 300 wants to The fetch delay is converted from a fixed delay type to a variable delay type, and even if the pSRAM 200 operates in the time interval tCSH and tCSHI with a short response time, the read and write data capture signal output by the RWDS pin of this embodiment When the RWDS performs the write operation in the memory cell array, it can not be misunderstood by the delay type and malfunction.

To sum up, the memory controller of the present invention can perform writing operations in the memory cell array, and when the inverting chip select signal is in a disabled state, the delay controller can Write the mask signal to control the delay type control signal to maintain the enabled state, so that the read and write data capture signal output by the RWDS pin can not malfunction during the write operation of the memory cell array, and thus effectively to improve the operating quality of the memory system.

200: Pseudo-Static Random Access Memory 300: Memory Controller 310: Mode Scratchpad 320: Mode register write controller 321: First stage circuit 322: Second stage circuit 323: Latch 324: Tri-state inverter 325: Pulse width adjustment circuit 330: Delay Controller 340: Self-refresh controller AND, OR1, OR2: logic gate COM:command CS_t: Chip select signal CSD_t: control signal CSD_c: Inverted control signal CHRDY_t: Initialization control signal DATA: mode register write data INV1～INV7: Inverter LTCX2_t: Delay control signal LTNCY2_t: Delay type control signal NOR: reverse or gate NAND: Invert and Gate n01: output signal MRW_t: write indication signal M1, M2: Transistor RE: Self-refresh request RWDS: read and write data capture signal T11～T41, T12～T42, tCSH, tCSHI: time interval WAITSR_t: Self-refresh wait signal WAITMRW_t: write mask signal

1A and FIG. 1B are signal timing diagrams of a conventional pseudo-static random access memory. FIG. 2 is a schematic diagram illustrating a pseudo-static random access memory according to an embodiment of the present invention. FIG. 3 is a schematic circuit diagram illustrating the memory controller shown in FIG. 2 according to an embodiment of the present invention. 4 is a signal timing diagram illustrating when the memory controller controls the access delay of the pseudo-static random access memory to switch from a fixed delay type to a variable delay type according to an embodiment of the present invention. 5 is a signal timing diagram illustrating when the memory controller controls the access delay of the pseudo-static random access memory to switch from a variable delay type to a fixed delay type according to an embodiment of the present invention.

300: Memory Controller

310: Mode Scratchpad

320: Mode register write controller

321: First stage circuit

322: Second stage circuit

323: Latch

324: Tri-state inverter

325: Pulse width adjustment circuit

330: Delay Controller

340: Self-refresh controller

AND, OR1, OR2: logic gate

COM:command

CS_t: Chip select signal

CSD_t: control signal

CSD_c: Inverted control signal

CHRDY_t: Initialization control signal

DATA: mode register write data

INV1~INV7: Inverter

LTCX2_t: Delay control signal

LTNCY2_t: Delay type control signal

NOR: reverse or gate

NAND: Invert and Gate

n01: output signal

MRW_t: write indication signal

M1, M2: Transistor

RE: Self-refresh request

WAITSR_t: Self-refresh wait signal

WAITMRW_t: write mask signal

Claims (10)

A memory controller suitable for pseudo-static random access memory, comprising: a mode register for generating a delay control signal according to the write instruction signal; a mode register write controller, used for generating the write instruction signal during the mode register write operation, and generating the write mask signal according to the chip selection signal; and The delay controller is coupled to the mode register and the mode register write controller, and generates a delay type control signal according to the delay control signal and the write mask signal. The memory controller of claim 1, wherein when the chip selection signal is enabled, the mode register write controller determines the mode register write according to the write instruction signal whether the action is executed, and the mode register write controller generates the write mask signal according to the judgment result, so that the delay controller controls the pseudo static random by the delay type control signal The access delay for accessing the memory is either the first type or the second type. The memory controller of claim 2, wherein when the write instruction signal indicates that the mode register write action is performed, the mode register write controller generates all enabled The write mask signal is used to make the delay controller control the access delay of the pseudo-static random access memory to the first type through the delay type control signal. The memory controller of claim 3, wherein the first type corresponds to a first delay time, and the second type corresponds to a second delay time, wherein the first delay time is the first delay time Two integer multiples of the delay time. The memory controller of claim 1, further comprising: The self-refresh controller is used for generating the self-refresh waiting signal according to the self-refresh request and the chip selection signal, The delay controller is further coupled to the self-refresh controller, and the delay controller also generates the delay-type control signal according to the self-refresh wait signal. The memory controller of claim 5, wherein the delay controller comprises: a first logic gate, the first input terminal of which receives the delay control signal and the second input terminal of which receives the write mask signal; and The second logic gate has a first input terminal for receiving the self-refresh waiting signal, a second input terminal of which is coupled to an output terminal of the first logic gate, and an output terminal of which generates the delay type control signal. The memory controller of claim 5, wherein when any one of the self-refresh wait signal, the delay control signal, and the write mask signal is enabled, the delay controller passes the A delay type control signal controls the access delay of the pseudo-static random access memory to the first type. The memory controller of claim 1, wherein the mode register write controller comprises: a first-stage circuit for generating the write instruction signal according to a command; and The second stage circuit is coupled to the first stage circuit and generates the write mask signal according to the write instruction signal, the chip selection signal and the initialization control signal. The memory controller of claim 8, wherein the second stage circuit comprises: a pulse width adjustment circuit, receiving the chip selection signal, and generating a control signal and an inversion control signal according to the chip selection signal; a latch, coupled to the pulse width adjustment circuit and the first-stage circuit, and generating an output signal according to the control signal, the inversion control signal and the write instruction signal; and The logic gate has a first input terminal for receiving the control signal, a second input terminal for receiving the output signal, and an output terminal for generating the write mask signal. The memory controller of claim 9, wherein the pulse width adjustment circuit adjusts the pulse width of the die select signal to generate the control signal and the inverted control signal that are complementary.

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