CN113936718B

CN113936718B - Memory Controller

Info

Publication number: CN113936718B
Application number: CN202010673537.XA
Authority: CN
Inventors: 森郁
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2020-07-14
Filing date: 2020-07-14
Publication date: 2025-05-27
Anticipated expiration: 2040-07-14
Also published as: CN113936718A

Abstract

The present invention provides a memory controller. The memory controller is suitable for a pseudo-static random access memory. The memory controller includes a mode register, a mode register write controller and a delay controller. The mode register is used to generate a delay control signal according to a write indication signal. The mode register write controller is used to generate a write indication signal in a mode register write operation and to generate a write mask signal according to a chip selection signal. The delay controller generates a delay type control signal according to the delay control signal and the write mask signal.

Description

Memory controller

Technical Field

The present disclosure relates to memory technologies, and in particular, to a memory controller.

Background

Pseudo-static random access memory (Pseudo Static Random Access Memory, abbreviated as pSRAM hereinafter) stores data using DRAM as a memory cell array, and the access interface of DRAM is redesigned to be compatible with that of SRAM, and the characteristics of access timing are also similar to that of SRAM.

In the conventional memory technology, a memory controller is generally used to determine whether a self-refresh collision (SELF REFRESH collision) occurs in the pSRAM, and the memory controller is used to control states of a delay control signal LTCX2_t generated by a mode register and a delay control signal LTNCY2_t generated by a delay controller, so as to set a delay type of an access delay (latency) of the pSRAM.

Fig. 1A and 1B show signal timing diagrams of a conventional pseudo-static random access memory. Referring to fig. 1A and 1B, the signal timing diagrams corresponding to the pSRAM respectively are shown when the memory controller determines that the self-refresh collision does not occur and adjusts the access delay of the pSRAM to different delay types when the pSRAM performs a Mode register write (Mode REGISTER WRITE, MRW) operation and operates in a write Mode.

In the scenario of fig. 1A, when the memory controller wants to adjust the access delay of the pSRAM from 2 times of the delay time to 1 times of the delay time (i.e., switch the delay type from the fixed delay type to the variable delay type), the inverted chip select signal (CHIP SELECT SIGNAL) cs# of the pSRAM is set to a low voltage level, and the delay control signal LTCX2_t and the delay type control signal LTNCY2_t are set to a high voltage level first.

However, in the prior art, since the reaction time of the inverted chip select signal cs# is too short for the time interval (i.e., tCSH and tCSHI) for switching from the low voltage level to the high voltage level, the delay control signal LTCX2_t and the delay type control signal LTNCY2_t cannot be immediately switched to the low voltage level in the time interval.

In this case, the Read/write data acquisition signal RWDS outputted from the Read/WRITE DATA Strobe pin (RWDS pin) may malfunction when the memory cell array performs a write operation.

In contrast, in the context of fig. 1B, when the memory controller wants to adjust the access delay of the pSRAM from 1 time to 2 times (i.e., switch the delay type from the variable delay type to the fixed delay type), the inverted chip select signal (CHIP SELECT SIGNAL) cs# of the pSRAM is set to a low voltage level, and the delay control signal LTCX2_t and the delay type control signal LTNCY2_t are set to the low voltage level first.

However, since the reaction time of the inverted chip select signal cs# from the low voltage level to the high voltage level (i.e., tCSH and tCSHI) is too short, the delay control signal LTCX2_t and the delay type control signal LTNCY2_t cannot be immediately converted to the high voltage level in the time interval.

In this case, the read/write data acquisition signal RWDS outputted from the RWDS pin may malfunction during the write operation of the memory cell array.

In other words, in the case of fig. 1A and 1B, the read/write data acquisition signal RWDS outputted by the RWDS pin is affected by the too short time interval (i.e., tCSH and tCSHI), so that the read/write data acquisition signal RWDS may malfunction when the memory cell array performs the write operation, and thus the pSRAM cannot write valid data under the correct timing control, and the overall memory system cannot operate normally.

Disclosure of Invention

The invention provides a memory controller, which can effectively reduce the situation of misoperation when the memory controller sets the delay type of the access delay of a pSRAM, thereby improving the operation quality of a memory system.

The memory controller of the present invention is applicable to pseudo-static random access memories. The memory controller includes a mode register, a mode register write controller, and a delay controller. The mode register is used for generating a delay control signal according to the write indication signal. The mode register write controller is used for generating a write indication signal in a mode register write operation and generating a write shielding signal according to a chip selection signal. The delay controller is coupled to the mode register and the mode register write controller, and generates a delay type control signal according to the delay control signal and the write mask signal.

Based on the above, the memory controller according to the embodiments of the present invention can perform a write operation on the memory cell array, and when the inverted chip selection signal is in the disabled state, the delay controller can control the delay control signal to maintain in the enabled state according to the write mask signal having the high voltage level, so that the read/write data acquisition signal output by the RWDS pin can not malfunction when the memory cell array performs the write operation, and further effectively improve the operation quality of the memory system.

Drawings

FIGS. 1A and 1B are signal timing diagrams of conventional pseudo-static random access memories;

FIG. 2 is a schematic diagram illustrating a pseudo-static random access memory according to an embodiment of the invention;

FIG. 3 is a circuit schematic illustrating the memory controller shown in FIG. 2 in accordance with one embodiment of the present invention;

FIG. 4 is a signal timing diagram illustrating a memory controller controlling the transition of the access delay of a pseudo-static random access memory from a fixed delay mode to a variable delay mode according to one embodiment of the present invention;

FIG. 5 is a signal timing diagram illustrating a memory controller controlling the transition of the access delay of a pseudo-static random access memory from a variable delay type to a fixed delay type according to one embodiment of the present invention.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Fig. 2 is a schematic diagram illustrating a pseudo-static random access memory according to an embodiment of the invention. Referring to fig. 2, psram 200 includes a memory controller 300, an input/output interface, an X decoder circuit, a Y decoder circuit, a memory cell array, a data latch circuit, and a data transmission path. The pSRAM 200 of the present embodiment may use, for example, an Expanded SERIAL PERIPHERAL INTERFACE (xSPI) or HyperBus ^TM interface as the xSPI pSRAM or HYPERRAM PSRAM access interface, but the present invention is not limited thereto.

In this embodiment, the input/output interface of the pSRAM 200 can provide the chip select signal cs_t to the memory controller 300 according to the inverted chip select signal cs#. When the chip select signal cs_t is enabled (e.g., at a high voltage level), the pSRAM 200 may perform a data access operation. When the chip select signal CS_t is disabled (e.g., low voltage level), the pSRAM 200 cannot perform the data access operation. In this embodiment, the states of the chip select signal cs_t and the inverted chip select signal cs# may be complementary.

It should be noted that the detailed functions and implementations of the memory controller 300, the input/output interface, the X decoder circuit, the Y decoder circuit, the memory cell array, the data latch circuit, and the data transmission path shown in fig. 2 may be sufficiently taught, suggested, and implemented by those of ordinary skill in the art.

FIG. 3 is a circuit schematic illustrating the memory controller shown in FIG. 2 according to one embodiment of the present invention. Referring to FIG. 3, a memory controller 300 may be suitable for the memory controller of pSRAM 200 shown in FIG. 2. In the present embodiment, the memory controller 300 includes a mode register 310, a mode register write controller 320, a delay controller 330, and a self-refresh controller 340.

In the present embodiment, the mode register 310 receives the write indication signal mrw_t and the mode register write DATA, and generates the delay control signal LTCX2_t according to the write indication signal mrw_t and the mode register write DATA. When the delay control signal LTCX2_t is in an enable (e.g., high voltage) state, the delay control signal LTCX2_t can instruct the delay controller 330 to generate the delay type control signal LTNCY2_t for controlling the access delay of the pSRAM 200 to be the first type. In contrast, when the delay control signal LTCX2_t is in a disabled (e.g., low voltage) state, the delay control signal LTCX2_t may instruct the delay controller 330 to generate the delay type control signal LTNCY2_t for controlling the access delay of the pSRAM 200 to the second type.

The self-refresh controller 340 receives the self-refresh request RE and the chip select signal CS_t and generates a self-refresh wait signal WAITSR _t according to the self-refresh request RE and the chip select signal CS_t.

In the present embodiment, the mode register write controller 320 includes a first stage 321 and a second stage 322. The mode register write controller 320 may receive a command COM through the first stage 321 and generate a write indication signal mrw_t in a Mode Register Write (MRW) action according to the command COM. Thus, the mode register write controller 320 can determine whether the pSRAM 200 performs the MRW operation by writing the indication signal mrw_t.

On the other hand, the second stage circuit 322 is coupled to the first stage circuit 321. The second stage circuit 322 can generate the write mask signal WAITMRW _t according to the write indication signal MRW_t, the chip select signal CS_t and the initialization control signal CHRDY _t.

Specifically, the second stage circuit 322 includes a latch 323, a pulse width adjustment circuit 325, a logic gate AND, AND an inverter INV7. The logic Gate AND of the present embodiment may be, for example, an AND Gate (AND Gate), but the present invention is not limited thereto.

In the present embodiment, the pulse width adjustment circuit 325 can receive the chip select signal cs_t and adjust the pulse width of the chip select signal cs_t to generate the complementary control signal csd_t and the complementary inverted control signal csd_c. In addition, the latch 323 is coupled to the pulse width modulation circuit 325 and the first stage 321. The latch 323 can generate an output signal n01 according to the control signal csd_t, the inverted control signal csd_c and the write indication signal mrw_t.

On the other hand, a first input terminal of the logic gate AND is coupled to the pulse width adjustment circuit 325 to receive the control signal CSD_t, AND a second input terminal of the logic gate AND is coupled to the latch 323 to receive the output signal n01. The logic gate AND performs an AND operation on the control signal CSD_t AND the output signal n01 to generate the write mask signal WAITMRW _t at the output of the logic gate AND. In addition, an input end of the inverter INV7 receives the initialization control signal CHRDY _t, and an output end of the inverter INV7 is coupled to the latch 323.

Regarding the detailed circuit architecture of the pulse width adjustment circuit 325, the pulse width adjustment circuit 325 includes inverters INV1, INV4, a plurality of inverters (e.g., INV2 and INV 3) connected in series with each other, and a NAND Gate (NAND Gate) NAND. In detail, the input end of the inverter INV1 receives the chip select signal cs_t. The input ends of the inverters connected in series are coupled to the output end of the inverter INV 1. The first input end of the NAND gate NAND is coupled to the output end of the inverter INV1, and the second input end of the NAND gate NAND is coupled to the output ends of the plurality of inverters which are connected in series. And, the NAND gate NAND can perform an inverse and operation on the signal generated by the inverter INV1 and the signals generated by the plurality of inverters connected in series, so as to generate the control signal csd_t at the output end of the NAND gate NAND.

In addition, an input end of the inverter INV4 is coupled to an output end of the NAND gate NAND to receive the control signal csd_t. The inverter INV4 may invert the control signal csd_t to generate an inverted control signal csd_c at the output end of the inverter INV 4.

Regarding the detailed circuit architecture of the latch 323, the latch 323 includes a tristate inverter 324, an inverter INV5, and a NOR Gate (NOR Gate) NOR. The tri-state inverter 324 of the present embodiment may be composed of an inverter INV6, a P-type transistor M1 and an N-type transistor M2.

In detail, in the tri-state inverter 324, an input end of the inverter INV6 may receive the write indication signal mrw_t. The P-type transistor M1 may be controlled by the control signal csd_t, and the N-type transistor M2 may be controlled by the inverted control signal csd_c. In addition, the latch 323 can enable the tri-state inverter 324 according to the states of the control signal csd_t and the inversion control signal csd_c, so that the P-type transistor M1 and the N-type transistor M2 can be turned on according to the control signal csd_t and the inversion control signal csd_c, respectively, and the inverter INV6 can generate the inverted write indication signal mrw_t at the output end.

In addition, a first input terminal of the NOR gate NOR is coupled to an output terminal of the inverter INV7, and a second input terminal of the NOR gate NOR is coupled to an output terminal of the inverter INV 6. The NOR gate NOR performs an inverse or operation on the signal generated by the inverter INV7 and the inverted write command signal mrw_t to generate an output signal n01 at the output terminal of the NOR gate NOR. In addition, the inverter INV5 is coupled between the output terminal of the NOR gate NOR and the second input terminal of the NOR gate NOR. Accordingly, the latch 323 may feedback the output signal n01 to the second input terminal of the NOR gate NOR through the inverter INV 5.

It should be noted that the latch 323, the tri-state inverter 324 and the pulse width adjusting circuit 325 of the present embodiment can be implemented by a latch, a tri-state inverter (tri-STATE INVERTER) and a pulse width adjusting circuit, which are well known to those skilled in the art, and the present invention is not limited to the above proposed circuit architecture.

On the other hand, the delay controller 330 is coupled to the mode register 310, the mode register write controller 320, and the self-refresh controller 340. In the present embodiment, the delay controller 330 can generate the delay type control signal LTNCY2 _2_t according to the self-refresh wait signal WAITSR _t, the delay control signal LTCX2 _2_t, and the write mask signal WAITMRW _t.

It is noted that the delay controller 330 of the present embodiment can control the access delay of the pSRAM 200 to be the first type or the second type by the delay type control signal LTNCY2 _t. For example, when the delay type control signal LTNCY2_t is in an enabled state (e.g., a high voltage level), the delay type of the access delay can be defined as a fixed delay type (corresponding to the first type). When the delay type control signal LTNCY2_t is in a disabled state (e.g., a low voltage level), the delay type of the access delay can be defined as a variable delay type (corresponding to the second type).

Further, in the present embodiment, the first type may correspond to a first delay time, and the second type may correspond to a second delay time, and the first delay time is an integer multiple (e.g. 2 times) of the second delay time (but the present invention is not limited thereto).

Regarding the detailed circuit architecture of the delay controller 330, the delay controller 330 includes a logic Gate OR1 and a logic Gate OR2, wherein the logic gates OR1 and OR2 may be, for example, OR gates (OR gates), but the invention is not limited thereto. Specifically, a first input terminal of the logic gate OR1 is coupled to the mode register 310 to receive the delay control signal LTCX2_t, and a second input terminal of the logic gate OR1 is coupled to the mode register write controller 320 to receive the write mask signal WAITMRW _t.

In addition, a first input terminal of the logic gate OR2 is coupled to the self-refresh controller 340 to receive the self-refresh wait signal WAITSR _t, and a second input terminal of the logic gate OR2 is coupled to an output terminal of the logic gate OR 1. The logic gate OR2 performs an OR operation on the self-refresh wait signal WAITSR _t and the signal output by the logic gate OR1 to generate the delay control signal LTNCY2_t at the output terminal.

That is, in the present embodiment, when any one of the self-refresh wait signal WAITSR _t, the delay control signal LTCX2 _2_t, and the write mask signal WAITMRW _t is set to be enabled (e.g., high voltage level), the delay controller 330 can control the access delay of the pSRAM 200 to the first mode (i.e., fixed delay mode) by the delay mode control signal LTNCY2 _2_t.

FIG. 4 is a signal timing diagram illustrating a memory controller controlling the transition of the access delay of a pseudo-static random access memory from a fixed delay mode to a variable delay mode according to one embodiment of the present invention. The embodiment of FIG. 4 assumes that pSRAM 200 is operating in write mode and no self-refresh collision occurs.

Referring to fig. 2 to 4, in the present embodiment, when pSRAM 200 is operated at an initial time before startup (e.g., power-on), memory controller 300 does not perform MRW operation, and initialization control signal CHRDY _t may be set to a disabled (e.g., low voltage level) state. In this case, the latch 323 of the mode register write controller 320 may initialize the output signal n01 according to the initialization control signal CHRDY _t that is disabled, so that the output signal n01 is set to a low voltage level state at the initial time.

Next, after the pSRAM 200 completes the power-up operation, the initialization control signal CHRDY _t may be set to an enabled (e.g., high voltage level) state again, and the state of the initialization output signal n01 is completed.

Then, when the pSRAM 200 is operated in the time interval T11, the inverted chip select signal CS# and the write indication signal MRW_t are both set to a disabled (e.g., low voltage level) state. At this time, the pulse width adjustment circuit 325 may generate the control signal csd_t with a high voltage level and the inverted control signal csd_c with a low voltage level according to the chip select signal cs_t being enabled (e.g., with a high voltage level).

In this case, the transistors M1 and M2 of the tri-state inverter 324 are turned off according to the control signal csd_t and the inversion control signal csd_c, respectively, so that the latch 323 can latch the state of the output signal n01 (i.e. the state of the output signal n01 is maintained at the low voltage level). At the same time, the mode register write controller 320 may generate the write mask signal WAITMRW _t disabled (e.g., at a low voltage level) according to the control signal csd_t at a high voltage level and the output signal n01 at a low voltage level.

It should be noted that, when the pSRAM 200 is operating at the initial time of the time interval T11, the mode register write controller 320 can determine that the memory controller 300 is not performing the MRW operation according to the write indication signal mrw_t.

Next, when pSRAM 200 is operated in a time period T21 after time period T11, both the inverted chip select signal cs# and the write indication signal mrw_t are set to an enabled (e.g., high voltage level) state. At this time, the pulse width adjustment circuit 325 can generate the control signal csd_t with a low voltage level and the inverted control signal csd_c with a high voltage level according to the chip select signal cs_t being disabled (e.g., at a low voltage level).

In this case, the transistors M1 and M2 of the tri-state inverter 324 are turned on according to the control signal csd_t and the inversion control signal csd_c, respectively, so that the latch 323 can generate the output signal n01 with a high voltage level according to the write indication signal mrw_t with a high voltage level and the initialization control signal CHRDY _t with a high voltage level. Furthermore, the mode register write controller 320 may generate the write mask signal WAITMRW _t that is disabled (e.g., at a low voltage level) according to the output signal n01 and the control signal csd_t.

On the other hand, when the pSRAM 200 operates in the time interval T31 after the time interval T21, it means that the memory cell array of the pSRAM 200 can start writing operation. At this time, the inverted chip select signal cs# is set to a disabled (e.g., low voltage level) state, and the write indication signal mrw_t can be maintained at an enabled (e.g., high voltage level) state at an initial time of the time interval T31. Therefore, the pulse width adjustment circuit 325 can generate the control signal csd_t with a high voltage level and the inverted control signal csd_c with a low voltage level according to the chip select signal cs_t being enabled (e.g., with a high voltage level).

In this case, the transistors M1 and M2 of the tri-state inverter 324 are turned off according to the control signal csd_t and the inversion control signal csd_c, respectively, so that the latch 323 can latch the state of the output signal n01 (i.e. the state of the output signal n01 is maintained at the high voltage level).

At the same time, the mode register write controller 320 may generate the write mask signal WAITMRW _t enabled (e.g., at a high voltage level) according to the control signal csd_t at the high voltage level and the output signal n01 at the high voltage level.

In other words, in the write operation (i.e., the time interval T31) of the memory cell array of the pSRAM 200, the delay controller 330 can generate the enabled delay control signal LTNCY2_t according to the write mask signal WAITMRW _t with a high voltage level, so that the read/write data acquisition signal RWDS outputted by the RWDS pin does not malfunction when the memory cell array performs the write operation.

In addition, in the present embodiment, the mode register write controller 320 may determine that the pSRAM 200 is performing the MRW operation at the initial time of the write operation of the memory cell array of the pSRAM 200. Moreover, since the mode register 310 generates the delay control signal LTCX2_t that is disabled according to the write indication signal MRW_t at this time, the memory controller 300 can set the access delay of the pSRAM 200 to a variable delay type when the memory cell array of the pSRAM 200 performs the write operation, and the delay type control signal LTNCY2_t can still be maintained at the high voltage level.

Next, when pSRAM 200 operates in a time interval T41 after time interval T31, it indicates that the memory cell array of pSRAM 200 has completed the write operation. At this time, the inverted chip select signal cs# is set to an enabled (e.g., high voltage level) state, and the write indication signal mrw_t is set to a disabled (e.g., low voltage level) state. Therefore, the pulse width adjustment circuit 325 can generate the control signal csd_t with a low voltage level and the inverted control signal csd_c with a high voltage level according to the chip select signal cs_t being disabled (e.g., at a low voltage level).

In this case, the transistors M1 and M2 of the tri-state inverter 324 are turned on according to the control signal csd_t and the inversion control signal csd_c, respectively, so that the latch 323 can generate the output signal n01 with a low voltage level according to the write indication signal mrw_t with a low voltage level and the initialization control signal CHRDY _t with a high voltage level. Furthermore, the mode register write controller 320 may generate the write mask signal WAITMRW _t that is disabled (e.g., at a low voltage level) according to the output signal n01 and the control signal csd_t.

FIG. 5 is a signal timing diagram illustrating a memory controller controlling the transition of the access delay of a pseudo-static random access memory from a variable delay type to a fixed delay type according to one embodiment of the present invention. The embodiment of FIG. 5 assumes that pSRAM 200 is operating in write mode and no self-refresh collision occurs.

It should be noted that, in the embodiment shown in fig. 5, details of the operation of the pSRAM 200 in the time intervals T12 to T22 can be analogized with reference to the related descriptions of the time intervals T11 to T21 in the embodiment shown in fig. 4, so that the description is omitted.

Referring to fig. 2, 3 and 5, when pSRAM 200 is operated in a time interval T32 after time interval T22, it means that the memory cell array of pSRAM 200 can start writing. At this time, the inverted chip select signal cs# is set to a disabled (e.g., low voltage level) state, and the write indication signal mrw_t can be maintained at an enabled (e.g., high voltage level) state at an initial time of the time interval T32. Therefore, the pulse width adjustment circuit 325 can generate the control signal csd_t with a high voltage level and the inverted control signal csd_c with a low voltage level according to the chip select signal cs_t being enabled (e.g., with a high voltage level).

In other words, in the write operation (i.e., the time interval T32) of the memory cell array of the pSRAM 200, the delay controller 330 can generate the enabled delay control signal LTNCY2_t according to the write mask signal WAITMRW _t with a high voltage level, so that the read/write data acquisition signal RWDS outputted by the RWDS pin does not malfunction when the memory cell array performs the write operation.

In addition, in the present embodiment, the mode register write controller 320 may determine that the pSRAM200 is performing the MRW operation at the initial time of the write operation of the memory cell array of the pSRAM 200. Moreover, since the mode register 310 generates the delay control signal LTCX2_t enabled according to the write indication signal MRW_t at this time, the memory controller 300 can set the access delay of the pSRAM200 to a fixed delay type when the memory cell array of the pSRAM200 performs the write operation, and the delay type control signal LTNCY2_t can still be maintained at the high voltage level.

Next, when pSRAM 200 operates for a time interval T42 after time interval T32, it indicates that the memory cell array of pSRAM 200 has completed the write operation. At this time, the inverted chip select signal cs# is set to an enabled (e.g., high voltage level) state, and the write indication signal mrw_t is set to a disabled (e.g., low voltage level) state. Therefore, the pulse width adjustment circuit 325 can generate the control signal csd_t with a low voltage level and the inverted control signal csd_c with a high voltage level according to the chip select signal cs_t being disabled (e.g., at a low voltage level).

As can be seen from the above description of the embodiments of fig. 4 and 5, no matter whether the memory controller 300 wants to switch the access delay of the pSRAM 200 from the variable delay type to the fixed delay type or switch the access delay of the pSRAM 200 from the fixed delay type to the variable delay type, even if the pSRAM 200 operates in the time interval tCSH, tCSHI with a short response time, the read/write data acquisition signal RWDS outputted by the RWDS pin of the embodiment can not be misinterpreted by the delay type to generate a malfunction when writing in the memory cell array.

In summary, the memory controller of the present invention can perform a write operation on the memory cell array, and when the inverted chip selection signal is in a disabled state, the delay controller can control the delay control signal to maintain in an enabled state according to the write shielding signal having a high voltage level, so that the read/write data acquisition signal output by the RWDS pin can perform a write operation on the memory cell array without malfunction, thereby effectively improving the operation quality of the memory system.

It should be noted that the above embodiments are merely for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the above embodiments, it should be understood by those skilled in the art that the technical solution described in the above embodiments may be modified or some or all of the technical features may be equivalently replaced, and these modifications or substitutions do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the present invention.

Claims

1. A memory controller, applicable to a pseudo-static random access memory, comprising:

A mode register, used to generate a delay control signal according to a write indication signal;

A mode register write controller, used to generate the write indication signal in the mode register write operation, and to generate a write mask signal according to a chip select signal; and

The delay controller is coupled to the mode register and the mode register write controller, and generates a delay type control signal according to the delay control signal and the write mask signal.

2. The memory controller according to claim 1, wherein when the chip select signal is enabled, the mode register write controller determines whether the mode register write action is executed based on the write indication signal, and the mode register write controller generates the write mask signal based on the determination result, so that the delay controller controls the access delay of the pseudo-static random access memory to the first type or the second type through the delay type control signal.

3. The memory controller according to claim 2, wherein when the write indication signal indicates that the mode register write action is executed, the mode register write controller generates the write mask signal to be enabled, and enables the delay controller to control the access delay of the pseudo-static random access memory to the first type through the delay type control signal.

4 . The memory controller according to claim 3 , wherein the first type corresponds to a first delay time, the second type corresponds to a second delay time, and the first delay time is an integer multiple of the second delay time.

5. The memory controller according to claim 1 , further comprising:

A self-refresh controller is used to generate a self-refresh wait signal according to a self-refresh request and the chip selection signal.

The delay controller is further coupled to the self-refresh controller, and the delay controller generates the delay type control signal according to the self-refresh wait signal.

6. The memory controller of claim 5, wherein the delay controller comprises:

A first logic gate, a first input terminal of which receives the delay control signal, and a second input terminal of which receives the write mask signal; and

The second logic gate has a first input terminal receiving the self-refresh wait signal, a second input terminal coupled to the output terminal of the first logic gate, and an output terminal generating the delay type control signal.

7. The memory controller according to claim 5, wherein when any one of the self-refresh wait signal, the delay control signal and the write mask signal is enabled, the delay controller controls the access delay of the pseudo-static random access memory to a first type through the delay type control signal.

8. The memory controller according to claim 1, wherein the mode register write controller comprises:

A first-stage circuit is used to generate the write indication signal according to a command; and

The second stage circuit is coupled to the first stage circuit and generates the write mask signal according to the write indication signal, the chip selection signal and the initialization control signal.

9. The memory controller of claim 8, wherein the second stage circuit comprises:

A pulse width adjustment circuit receives the chip selection signal and generates a control signal and an inverted control signal according to the chip selection signal;

a latch coupled to the pulse width adjustment circuit and the first stage circuit, and generating an output signal according to the control signal, the inverted control signal and the write indication signal; and

A logic gate has a first input terminal receiving the control signal, a second input terminal receiving the output signal, and an output terminal generating the write mask signal.

10 . The memory controller according to claim 9 , wherein the pulse width adjustment circuit adjusts a pulse width of the chip selection signal to generate the control signal and an inverted control signal which are complementary.