TWI756040B - Display device - Google Patents

Abstract

A display device has a peripheral area and a display area, and includes data lines, scan lines, transfer lines, pixels and shielding wires. The data lines extend from the peripheral area into the display area in a first direction. The scan lines located in the display area extend in a second direction intersected with the first direction. The transfer lines extend from the peripheral area into the display area and are electrically connected to the scan lines respectively. The pixels are electrically connected to the scan lines and the data lines respectively, in which a first data line and at least two transfer lines are located between the adjacent two of the pixels. A first shielding wire of the shielding wires is located between the first data line and the at least two transfer lines, and a second shielding wire of the shielding wires is located between the adjacent two of the at least two transfer lines.

Description

display device

The present invention relates to a display device, and more particularly, to a display device with stable data line potential.

In the display produced by the special-shaped cutting method, the signal source of the gate electrode and the source electrode need to be placed on the same side to facilitate cutting. Therefore, in the display area of the display, there are vertical gate transition lines disposed between adjacent pixels, and the gate transition lines are usually parallel to the data lines. However, there will be a fixed capacitance between the parallel and adjacent data lines and the gate transfer line, which will cause capacitive coupling of the signal, and affect the potential of the data line when the gate signal is turned on or off, making the data line The potential of the device fluctuates and becomes unstable, resulting in abnormal display brightness.

The present invention provides a display device with stable data line potential.

An embodiment of the present invention provides a display device, which has a peripheral area and a display area, and includes: a plurality of data lines extending from the peripheral area into the display area, wherein the data lines extend along a first direction; and a plurality of scan lines located at The display area extends along a second direction interlaced with the first direction; a plurality of transfer lines extend from the peripheral area into the display area and are respectively electrically connected to the scan lines; a plurality of pixels are electrically connected to the A scan line and a data line, wherein the first data line and at least two transfer lines are located between two adjacent ones of the pixels; and a plurality of shielded wires, wherein the first shielded wire is located between the first data line and the above at least two Between the transfer wires, the second shielded wire is located between two adjacent ones of the above at least two transfer wires.

In an embodiment of the present invention, the above-mentioned shielded wires are electrically connected to each other.

In an embodiment of the present invention, the above-mentioned second shielded wire has an opening.

In an embodiment of the present invention, four transfer wires and five shielded wires are arranged between two adjacent ones of the above-mentioned pixels.

In an embodiment of the present invention, the above-mentioned pixel includes a plurality of sub-pixels, each sub-pixel includes a switching element and a pixel electrode, the pixel electrode is electrically connected to the switching element, and the shielding wire and the pixel electrode belong to the same film layer.

In an embodiment of the present invention, the above-mentioned display device further includes a common electrode, wherein the shielding wire is electrically connected to the common electrode.

In an embodiment of the present invention, the above-mentioned display device further includes a dummy data line, wherein at least two transfer lines are located between the first data line and the dummy data line.

In an embodiment of the present invention, the third shielded wire among the above-mentioned shielded wires is located between the dummy data wire and the patch wire.

In an embodiment of the present invention, the dummy data line and the first data line are connected through a conductive layer, and the conductive layer and the scan line belong to the same film layer.

In an embodiment of the present invention, the above-mentioned data lines, transition lines and dummy data lines belong to the same film layer.

In an embodiment of the present invention, the above-mentioned data lines, transition lines and dummy data lines belong to different layers.

In an embodiment of the present invention, the above-mentioned at least two patch cables belong to different layers.

An embodiment of the present invention provides a display device having a peripheral area and a display area, the display area has a patch cord area, the patch cord area has a side area and a center area, and the side area is located between the peripheral area and the center area , wherein the display device includes: a plurality of data lines extending from the peripheral area into the display area, wherein the data lines extend along a first direction; a plurality of scan lines, located in the display area, and along a second direction staggered in the first direction extension; a plurality of transfer lines, extending from the peripheral area into the transfer line area, and electrically connected to the scan lines respectively; a plurality of pixels, respectively electrically connected to the scan lines and the data lines, wherein the first data line and at least Two transfer wires are located between two adjacent ones of the pixels; a plurality of shielded wires are located in the central area; and a plurality of shielding patterns are located in the central area; wherein the first shielded wire is located between the first data line and the at least two transfer wires Between lines, the second shielded wire is located between two adjacent ones of the at least two transfer lines, each shielding pattern is located at the connection between each transfer line and the corresponding scan line, and each shielding pattern overlaps at least two transfer lines at the same time. line and the corresponding scan line.

In an embodiment of the present invention, each of the above-mentioned shielding patterns is connected to the first shielded wire and the second shielded wire.

In an embodiment of the present invention, the above-mentioned display device further includes a dummy data line, wherein at least two transfer lines are located between the first data line and the dummy data line.

In an embodiment of the present invention, the above-mentioned first data line and the dummy data line are connected in the side region.

In an embodiment of the present invention, the above-mentioned display area further has a non-patch line area, the non-patch line area is located between the transition line area and the peripheral area, and in the non-patch line area, the dummy data line and the second The data line is located between two adjacent ones in the pixel.

In an embodiment of the present invention, the above-mentioned second data line is electrically connected to the dummy data line.

In an embodiment of the present invention, the above-mentioned display device further includes a plurality of common electrode lines, wherein at least two common electrode lines are located between the second data line and the dummy data line.

In an embodiment of the present invention, the number of the above-mentioned at least two common electrode lines and at least two transition lines is the same.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

FIG. 1 is a schematic top view of a display device 10 according to an embodiment of the present invention. FIG. 2 is an enlarged view of area I in FIG. 1 . The display device 10 has a peripheral area NA and a display area AA. The display device 10 includes a plurality of data lines DL, a plurality of scan lines GL, a plurality of transition lines Gn, a plurality of pixels PX, and a plurality of shielding wires Sn. A plurality of data lines DL extend from the peripheral area NA into the display area AA, wherein the data lines DL extend along the first direction D1. The plurality of scan lines GL are located in the display area AA and extend along the second direction D2, wherein the second direction D2 is intersected with the first direction D1. A plurality of transition lines Gn extend from the peripheral area NA into the display area AA, and are respectively electrically connected to the scan lines GL. The plurality of pixels PX are respectively electrically connected to the scan line GL and the data line DL, wherein the data line DL1 and at least two transition lines Gn are located between two adjacent pixels PX among the plurality of pixels PX. Among the plurality of shielded conductors Sn, the shielded conductor S1 is located between the data line DL1 and the patch cord Gn, and the shielded conductor S2 is located between two adjacent patch cords Gn.

In this embodiment, the shielded wire S1 is used to separate the patch cord Gn and the data line DL1, so as to reduce the capacitive coupling between the patch cord Gn and the data line DL1, thereby preventing the potential of the data line DL1 from changing, and enabling The data line DL1 has a stable potential. In addition, the shielded wires S2 between adjacent patch wires Gn can make the loads of the patch wires Gn relatively similar, so as to avoid uneven brightness of the display device 10 .

Hereinafter, the embodiments of each element and film layer of the display device 10 will be continuously described with reference to the drawings, but the present invention is not limited thereto.

Referring to FIG. 1 , in this embodiment, the shape of the display device 10 is a circle, but the present invention is not limited thereto. In some embodiments, the display device 10 may have a rectangular, oval, polygonal, or irregular shape, and the shape of the display device 10 may be selected as desired.

The display device 10 may have a peripheral area NA and a display area AA, and the peripheral area NA surrounds the display area AA. In this embodiment, the display device 10 further includes a driving circuit DC located in the peripheral area NA. In this embodiment, the display device 10 is unilateral, and the driving circuit DC is located on the upper side of the display area AA, but the invention is not limited to this. In some embodiments, the display device 10 may be bilaterally driven, and the driving circuits DC may be located on the upper and lower sides or the left and right sides of the display area AA.

In this embodiment, the display area AA may have a patch cord area TA and a non-transit cord area NTA, wherein the patch cord area TA is an area provided with patch cords Gn, and the patch cord Gn is not set in the non-transition cord area. Connection area NTA. In this embodiment, the patch cord area TA is located in the central area of the display area AA, and the non patch cord area NTA is located on both sides of the patch cord area TA, but the present invention is not limited to this, the patch cord area TA And the configuration of the non-patch line area NTA can be changed as needed. In this embodiment, the patch cord area TA may have a side area EA1 and a central area CA1, wherein the side area EA1 is located between the peripheral area NA and the central area CA1. In addition, the non-patch line area NTA may also have a side area EA2 and a center area CA2, and the side area EA2 is located between the peripheral area NA and the center area CA2.

1 and 2 at the same time, the display device 10 includes a plurality of data lines DL, a plurality of scan lines GL, a plurality of transition lines Gn, a plurality of pixels PX and a plurality of shielding wires Sn on the substrate SB. The data line DL is electrically connected to the driving circuit DC. For example, the data line DL is electrically connected to a source driving element (not shown) in the driving circuit DC. The data lines DL extend from the peripheral area NA into the display area AA, the data lines DL in the display area AA extend along the first direction D1, and the data lines DL in the peripheral area NA may not be parallel to each other.

The scan line GL is located in the display area AA and extends along the second direction D2 which is intersected with the first direction D1. The patch cord Gn extends from the peripheral area NA into the patch cord area TA of the display area AA, and one end of the patch cord Gn is electrically connected to the scan line GL respectively, and the other end of the patch cord Gn is electrically connected to the driving circuit DC For example, the switching wire Gn can be electrically connected to a gate driving element (not shown) in the driving circuit DC. In this way, the switching wires Gn can respectively transmit the gate driving signals from the driving circuit DC to the corresponding scanning lines GL.

Referring to FIG. 2 , in this embodiment, the display device 10 includes a plurality of sub-pixels SP, and each sub-pixel SP is electrically connected to the corresponding scan line GL and data line DL. For example, each sub-pixel SP includes a switch element SW and a pixel electrode PE electrically connected to the switch element SW, wherein the switch element SW is electrically connected to a corresponding scan line and a corresponding data line. In this embodiment, the sub-pixels SP include red sub-pixels, green sub-pixels and blue sub-pixels. For example, the sub-pixel SP overlapping the red filter element (not shown) is a red sub-pixel, the sub-pixel SP overlapping the green filter element (not shown) is a green sub-pixel, and the sub-pixel SP overlapping the green filter element (not shown) is a green sub-pixel. The sub-pixel SP of the blue filter element (not shown) is a blue sub-pixel. In this embodiment, the sub-pixels SP are arrayed into a plurality of pixels PX. For example, each pixel PX includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel. In some embodiments, each pixel PX may also include sub-pixels of other colors. In this embodiment, each pixel PX includes three sub-pixels SP, and each pixel PX is electrically connected to one scan line and three data lines.

In the patch cord area TA, one data line DL and at least two patch cords Gn may be set between two adjacent pixels PX. For example, in this embodiment, one data line DL1 and four transition lines G1 to G4 are set between two adjacent pixels PX1 and PX2 . In some embodiments, one data line DL1 and three transition lines Gn may be set between adjacent pixels PX1 and PX2. In some embodiments, one data line DL and five transition lines Gn may be set between adjacent pixels PX1 and PX2.

In this embodiment, the data line DL1 is located between the pixel PX1 and the transition line G1. The display device 10 may further include a dummy data line DDL, and the transition lines G1 to G4 are located between the data line DL1 and the dummy data line DDL, and the dummy data line DDL is located between the transition line G4 and the pixel PX2. In this embodiment, the data line DL1 , the transition lines G1 - G4 and the dummy data line DDL may belong to the same film layer, but the invention is not limited to this. By arranging the dummy data line DDL, the capacitive coupling between the data line DL1 and the pixel PX1 can be canceled by the capacitive coupling between the dummy data line DDL and the pixel PX2.

In the central area CA1 of the patch cord area TA, a plurality of shielded wires Sn of the display device 10 can be respectively disposed between the data line DL1, the patch cords G1-G4 and the dummy data line DDL. For example, in this embodiment, the display device 10 includes three shielded wires S1-S3, wherein the shielded wire S1 is located between the data line DL1 and the patch wire G1; the shielded wire S2 is located between the patch wire G2 and the patch wire G3 and the shielded wire S3 is located between the transfer wire G4 and the dummy data wire DDL, but the present invention is not limited to this. In this way, the shielded wire S1 can separate the data wire DL1 from the patch wire G1 to reduce the capacitive coupling between the data wire DL1 and the patch wire G1, and the shielded wire S2 and the shielded wire S3 can make the patch wire The load of G2~G4 is similar to that of the patch cord G1, so as to avoid uneven brightness.

FIG. 3 is a schematic top view of the display device 20 according to an embodiment of the present invention. Compared with the display device 10 shown in FIGS. 1 to 2 , the display device 20 shown in FIG. 3 is different in that the display device 20 includes five shielded wires S1 to S5 , wherein the shielded wire S1 is located between the data line DL1 and the switch. Between the wiring G1; the shielded wire S2 is between the transfer wire G1 and the transfer wire G2; the shielded wire S3 is between the transfer wire G2 and the transfer wire G3; the shielded wire S4 is between the transfer wire G3 and the transfer wire between G4; and the shielded wire S5 is located between the transfer line G4 and the dummy data line DDL. Setting shielded wires Sn between any two of the data line DL1, the patch cables G1~G4 and the dummy data line DDL can fully uniformize the load of the patch cables G1~G4 and avoid slight misalignment in the process. The situation that leads to the uneven load is more serious.

FIG. 4A is a schematic top view of a display device 30 according to an embodiment of the present invention. FIG. 4B is an enlarged schematic view of a region V of the display device 30 of FIG. 4A . Fig. 4C is a schematic cross-sectional view taken along the section line A-A' of Fig. 4B. Compared with the display device 20 of FIG. 3 , the display device 30 shown in FIGS. 4A to 4C is different in that the shielded wire S2 has an opening O2 , and the shielded wire S4 has an opening O4 , wherein the shielded wire S2 includes a sub-conductor S21 and the sub-conductor S22, and the opening O2 is located between the sub-conductor S21 and the sub-conductor S22; meanwhile, the shielded lead S4 includes the sub-conductor S41 and the sub-conductor S42, and the opening O4 is located between the sub-conductor S41 and the sub-conductor S42. In this embodiment, the openings O2 and O4 can reduce the capacitance between the shielded wire S2 and the shielded wire S4 and the nearby conductive layer, and avoid short circuit between the shielded wire S2 and the shielded wire S4 and the adjacent conductive layer.

4B and 4C at the same time, in this embodiment, the switching element SW includes a gate electrode GE, a semiconductor layer CH, a source electrode SE and a drain electrode DE. The gate electrode GE overlaps the semiconductor layer CH, and the region where the semiconductor layer CH overlaps the gate electrode GE can be regarded as a channel region of the switching element SW. The source SE and the drain DE of the switching element SW are separated from each other, and the source SE and the drain DE respectively contact the semiconductor layer CH. The pixel electrode PE is electrically connected to the drain electrode DE. The switching element SW can be turned on or off through the signal transmitted by the scan line GL, and when the switching element SW is turned on, the signal transmitted on the data line DL can be transmitted to the pixel electrode PE.

The source electrode SE and the drain electrode DE of the switching element SW may belong to the same film layer, and the material of the source electrode SE, the drain electrode DE and the gate electrode GE of the switching element SW may include metals with good conductivity, such as aluminum, molybdenum, titanium, etc. metal, but the present invention is not limited to this. In order to avoid unnecessary short circuits between components, a gate insulating layer GI is provided between the gate electrode GE and the semiconductor layer CH, and between the film layer forming the source electrode SE and the drain electrode DE and the pixel electrode PE Passivation layer PV. Although the gate GE in this embodiment is located under the semiconductor layer CH, the switching element SW is a bottom gate transistor. However, in other embodiments, the gate GE may also be located above the semiconductor layer CH, so that the switching element SW is a top gate transistor.

In this embodiment, the shielding wires S1-S5 and the pixel electrodes PE belong to the same film layer, and the materials of the shielding wires S1-S5 include transparent conductive materials. In some embodiments, the shielding wires S1-S5 can be made of alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials or other suitable materials, or stacked layers of the above conductive materials, such as indium Tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide, or other suitable oxides or a stacked layer of at least two of the above, but the invention is not limited thereto.

The display device 30 further includes a common electrode CL, and the shielded wires S1 ˜ S5 are electrically connected to the common electrode CL, respectively. Therefore, the shielded wires S1 ˜ S5 have the same potential as the common electrode CL. For example, in this embodiment, the common electrode CL includes a common electrode CL1 and a common electrode CL2, and the common electrode CL1 and the common electrode CL2 are located on two sides of the scan line GL, respectively. The shielded wires S1 ˜ S5 can be electrically connected to each other through the wire ML1 , and the wire ML1 can be connected to the common electrode CL1 through the through hole V1 . In addition, the wire ML1 can also be connected to the wire ML2 through the through hole V2, and the wire ML2 can be connected to the common electrode CL2 through the through hole V3, the wire ML3 and the through hole V4, so that the common electrode CL1 and the common electrode CL2 can be connected to form a mesh electrode. In this way, even after the display device 30 is cut in a special shape, the common electrode CL1 and the common electrode CL2 can still be electrically connected.

FIG. 5 is an enlarged view of the display device 30 of FIG. 4A in the region II shown in FIG. 1 . In the side area EA1 of the patch line area TA of the display device 30, the dummy data line DDL and the data line DL1 are connected through the conductive layer M1, so that the dummy data line DDL and the data line DL1 have the same potential. In some embodiments, the conductive layer M1 and the scan line GL may belong to the same film layer, but the invention is not limited thereto. In some embodiments, the data line DL1 may be connected to the conductive layer M1 by the conductive pattern P1, and the dummy data line DDL may be connected to the conductive layer M1 by the conductive pattern P2. The conductive pattern P1 and the conductive pattern P2 may belong to the same film layer as the shielded wires S1 to S5 of the display device 30 of FIG. 4A , and the shielded wires S1 to S5 do not extend to the side area EA1 to avoid the conductive pattern P1 and the conductive pattern P2 short circuit.

FIG. 6 is an enlarged view of the display device 30 of FIG. 4A in the region III shown in FIG. 1 . In the present embodiment, in the central area CA1 of the patch cord area TA, the patch cables G1 to G4 can be connected to four scan lines GL, wherein each of the patch cables G1 to G4 is respectively connected to a corresponding scan line GL. The four scan lines GL connected by the transition lines G1 to G4 may be sequentially arranged along the first direction D1, but the present invention is not limited thereto. In addition, a shield pattern SM may be provided where the transition lines G1 to G4 connect the scan lines GL.

For example, in this embodiment, the shielding pattern SM is located between the data line DL1 and the dummy data line DDL, and the shielding pattern SM may include a shielding block SM1 and a shielding block SM2.

In some embodiments, the shielding block SM1 is connected to the shielding wires S1 - S5 , and the shielding block SM1 overlaps the common electrode CL1 , the common electrode CL2 , the transition lines G1 - G4 and the scan line GL1 at the same time. Using the shielding block SM1 to cover the patch cords G1 to G4 can prevent the electric field of the patch cords G1 to G4 from affecting the adjacent pixel electrodes PE. In some embodiments, the patch line G1 can be connected to the shield block SM2 through the through hole V5, and the shield block SM2 can be connected to the scan line GL1 through the through hole V6. Since the through hole V5 and the through hole V6 can be formed by the existing process, the process steps and mask of forming the through hole in the overlapping region VI of the transition line G1 and the scan line GL1 can be omitted.

FIG. 7 is an enlarged view of the display device 30 of FIG. 4A in the region IV shown in FIG. 1 . In this embodiment, the non-patch line area NTA is located between the transition line area TA and the peripheral area NA. In the non-patch line area NTA, a data line DL2 and a dummy data line DDL can be disposed between adjacent pixels, and the data line DL2 and the dummy data line DDL are electrically connected in the side area EA2.

Since the non-transfer line area NTA is not provided with the transfer line Gn, in the non-transfer line area NTA, a plurality of common electrode lines can be set between the data line DL2 and the dummy data line DDL, and the number of common electrode lines It may be the same as the number of patch lines between adjacent pixels in the patch line area TA, so that the capacitive load of the non- patch line area NTA is similar to that of the patch line area TA. For example, in this embodiment, four common electrode lines CM1 , CM2 , CM3 , and CM4 are disposed between the data line DL2 and the dummy data line DDL.

In addition, a shielded wire S6 can be arranged between the data line DL2 and the common electrode line CM1, and a shielded wire S7 can be arranged between the dummy data line DDL and the common electrode line CM4, so as to reduce the reduction of the common electrode lines CM1, CM4 and the data line DL2 , Capacitive coupling between the dummy data lines DDL, so as to avoid the potential variation of the data line DL2 and the dummy data line DDL, so that the data line DL2 can have a stable potential.

FIG. 8A is a schematic top view of a display device 40 according to an embodiment of the present invention. Fig. 8B is a schematic cross-sectional view taken along the section line B-B' of Fig. 8A. Fig. 8C is a schematic cross-sectional view taken along the section line C-C' of Fig. 8A. Compared with the display device 20 shown in FIG. 3 , the display device 40 shown in FIGS. 8A to 8C is different in that: in the central area CA1 of the patch cord area TA, the data line DL1 , the patch cord G1 ~ G4 and the dummy data line DDL belong to different layers.

For example, in this embodiment, the patch line G1, the patch wire G3, and the dummy data line DDL belong to the conductive layer M0, and the data line DL1, the patch wire G2, and the patch wire G4 belong to the conductive layer M2. Therefore, the patch cords G1~G4 also belong to different film layers. The conductive layer M0 is located on the substrate SB, the buffer layer BF and the gate insulating layer GI are disposed between the conductive layer M0 and the conductive layer M2, and the passivation layer PV is located on the conductive layer M2. Since any adjacent traces in the data line DL1, the transition lines G1~G4, and the dummy data line DDL belong to different layers, the possibility of short-circuiting of adjacent traces due to process errors can be eliminated, thereby minimizing the phase difference. Spacing between adjacent traces.

8C, in the side area EA1 of the patch line area TA of the display device 40, the dummy data line DDL and the data line DL1 are connected through the conductive layer M4, so that the dummy data line DDL and the data line DL1 have the same potential.

FIG. 9 is a schematic cross-sectional view of a display device 50 according to an embodiment of the present invention. Compared with the display device 40 shown in FIG. 8B , the display device 50 shown in FIG. 9 is different in that the patch line G1 , the patch line G3 and the dummy data line DDL belong to the conductive layer M3 , and the data line DL1 , the transfer line G2 and the transfer line G4 belong to the conductive layer M2.

In this embodiment, the gate insulating layer GI is located on the substrate SB, the conductive layer M2 is disposed on the gate insulating layer GI, the passivation layer PV is located between the conductive layer M2 and the conductive layer M3, and the insulating layer BP is located on the conductive layer M3 superior. Since any adjacent traces in the data line DL1, the transition lines G1~G4, and the dummy data line DDL belong to different layers, the possibility of short-circuiting of adjacent traces due to process errors can be eliminated, thereby minimizing the phase difference. The distance between adjacent traces.

To sum up, the present invention utilizes shielded wires to separate the patch cables and the data cables, which can reduce the capacitive coupling between the patch cables and the data cables, and avoid the potential variation of the data cables, so that the potential of the data cables can be maintained. Stablize. In addition, by arranging shielded wires between adjacent patch cables, the load of the patch cables can be similar, and the uneven brightness of the display device can be avoided.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

10, 20, 30, 40, 50: Display device A-A', B-B', C-C': hatching AA: display area BF: buffer layer BP: insulating layer CA1, CA2: Central District CH: semiconductor layer CL, CL1, CL2: Common electrodes CM1, CM2, CM3, CM4: Common electrode lines D1: first direction D2: second direction DC: drive circuit DDL: dummy data line DE: drain DL, DL1, DL2: data lines EA1, EA2: side area G1, G2, G3, G4, Gn: Adapter cable GE: gate GI: gate insulating layer GL, GL1: scan line I, II, III, IV, V, VI: Regions M0, M1, M2, M3, M4: Conductive layer ML1, ML2, ML3: Wires NA: Surrounding area NTA: Non-patch line area O2, O4: Opening P1: Conductive Pattern P2: Conductive Pattern PE: pixel electrode PV: Passivation layer PX, PX1, PX2: Pixels S1, S2, S3, S4, S5, S6, S7, Sn: Shielded conductors S21, S22, S41, S42: Sub-conductors SB: Substrate SE: source SM: Shield Pattern SM1, SM2: Blocking blocks SP: Subpixel SW: switching element TA: patch cord area V1, V2, V3, V4, V5, V6: Through holes

FIG. 1 is a schematic top view of a display device 10 according to an embodiment of the present invention. FIG. 2 is an enlarged view of area I in FIG. 1 . FIG. 3 is a schematic top view of the display device 20 according to an embodiment of the present invention. FIG. 4A is a schematic top view of a display device 30 according to an embodiment of the present invention. FIG. 4B is an enlarged schematic view of a region V of the display device 30 of FIG. 4A . Fig. 4C is a schematic cross-sectional view taken along the section line A-A' of Fig. 4B. FIG. 5 is an enlarged view of the display device 30 of FIG. 4A in the region II shown in FIG. 1 . FIG. 6 is an enlarged view of the display device 30 of FIG. 4A in the region III shown in FIG. 1 . FIG. 7 is an enlarged view of the display device 30 of FIG. 4A in the region IV shown in FIG. 1 . FIG. 8A is a schematic top view of a display device 40 according to an embodiment of the present invention. Fig. 8B is a schematic cross-sectional view taken along the section line B-B' of Fig. 8A. Fig. 8C is a schematic cross-sectional view taken along the section line C-C' of Fig. 8A. FIG. 9 is a schematic cross-sectional view of a display device 50 according to an embodiment of the present invention.

A-A': hatch line CH: semiconductor layer CL1: Common electrode DE: drain DDL: dummy data line DL1: Data Line G1, G2, G3, G4: Adapter cable GE: gate GI: gate insulating layer GL: scan line ML1, ML2: Wire PE: pixel electrode PV: Passivation layer S1, S2, S3, S4, S5: Shielded conductors S21, S22, S41, S42: Sub-conductors SB: Substrate SE: source SW: switching element 30: Display device

Claims (20)

A display device has a peripheral area and a display area, and includes: a plurality of data lines extending from the peripheral area into the display area, wherein the data lines extend along a first direction; a plurality of scan lines located in the display area and extending along a second direction interlaced with the first direction; a plurality of transfer lines extending from the peripheral area into the display area and electrically connected to the scan lines respectively; a plurality of pixels, respectively electrically connected to the scan lines and the data lines, wherein a first data line and at least two transfer lines are located between two adjacent ones of the pixels; and A plurality of shielded wires, wherein a first shielded wire is positioned between the first data wire and the at least two transfer wires, and a second shielded wire is positioned between two adjacent ones of the at least two transfer wires. The display device of claim 1, wherein the shielded wires are electrically connected to each other. The display device of claim 1, wherein the second shielded wire has an opening. The display device as claimed in claim 1, wherein four transfer wires and five shielded wires are arranged between two adjacent ones of the pixels. The display device of claim 1, wherein each pixel includes a plurality of sub-pixels, each of the sub-pixels includes a switch element and a pixel electrode, the pixel electrode is electrically connected to the switch element, and the Some shielded wires belong to the same film layer as the pixel electrode. The display device of claim 1, further comprising a common electrode, wherein the shielding wires are electrically connected to the common electrode. The display device of claim 1, further comprising a dummy data line, wherein the at least two transfer lines are located between the first data line and the dummy data line. The display device of claim 7, wherein a third shielded wire among the shielded wires is located between the dummy data wire and the at least two transition wires. The display device of claim 7, wherein the dummy data line and the first data line are connected through a conductive layer, and the conductive layer and the scan lines belong to the same film layer. The display device of claim 7, wherein the data lines, the transition lines and the dummy data lines belong to the same film layer. The display device of claim 7, wherein the data lines, the transition lines and the dummy data lines belong to different layers. The display device of claim 11, wherein the at least two patch cables belong to different film layers. A display device has a peripheral area and a display area, and the display area has a patch cord area, the patch cord area has a side area and a central area, the side area is located in the peripheral area and the central area between, wherein the display device includes: a plurality of data lines extending from the peripheral area into the display area, wherein the data lines extend along a first direction; a plurality of scan lines located in the display area and extending along a second direction interlaced with the first direction; a plurality of patch cords extending from the peripheral area into the patch cord area and electrically connected to the scan lines respectively; a plurality of pixels, respectively electrically connected to the scan lines and the data lines, wherein a first data line and at least two transfer lines are located between two adjacent ones of the pixels; a plurality of shielded conductors, located in the central region; and a plurality of shielding patterns, located in the central area; One of the first shielded conductors is located between the first data line and the at least two patch cables, a second shielded conductor is located between two adjacent ones of the at least two patch cables, and each of the shield patterns is located between each of the at least two patch cables. Where the patch wire is connected to the corresponding scan line, and each of the shielding patterns overlaps the at least two patch cables and the corresponding scan line at the same time. The display device of claim 13, wherein each of the shielding patterns is connected to the first shielded wire and the second shielded wire. The display device of claim 13, further comprising a dummy data line, wherein the at least two transfer lines are located between the first data line and the dummy data line. The display device of claim 15, wherein the first data line and the dummy data line are connected in the side area. The display device according to claim 15, wherein the display area further has a non-patch line area, the non-patch line area is located between the patch line area and the peripheral area, and in the non-patch line area, the dummy The data line and a second data line are located between two adjacent ones of the pixels. The display device of claim 17, wherein the second data line is electrically connected to the dummy data line. The display device of claim 17, further comprising a plurality of common electrode lines, wherein at least two common electrode lines are located between the second data line and the dummy data line. The display device of claim 19, wherein the at least two common electrode lines and the at least two transition lines have the same number.

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