CN105372891A - Array substrate and display device - Google Patents

Abstract

The present invention describes an array substrate and a display device. The array substrate includes a pixel array, which is composed of a plurality of pixel units arranged in a matrix of m rows×n columns; a plurality of gate lines extending along the row direction, and a plurality of A data line and a scan line extending along the column direction, the scan line is connected to one of the gate lines and is insulated from the rest of the gate lines; between two adjacent columns of pixel units is the first wiring area Or the second routing area, the first routing area and the second routing area are arranged alternately along the row direction; two data lines are arranged in each first routing area, and each second routing area There is at most one scan line in a region. The array substrate provided by the invention can increase the distance between the scanning line and the data line, reduce the voltage coupling on the data line, and solve the problem that some pixels of the display device are too bright when the gray scale is low or medium.

Description

A kind of array substrate, display device

technical field

The present invention relates to the field of thin film transistor (ThinFilm Transistor, TFT) display technology, in particular to an array substrate and a display device including the array substrate.

Background technique

Array substrates, also known as TFT substrates, have the characteristics of small size and low power consumption, and occupy a dominant position in the current display field.

A current TFT substrate includes a pixel array, and the pixel array includes a plurality of pixel units arranged in an array, and a TFT switch and a pixel electrode are arranged in each pixel unit. The function of the TFT switch is a three-terminal switch tube, one end is the gate, which corresponds to the gate line; one end is the source, which corresponds to the data line; the other end is the drain, which corresponds to the pixel electrode. The array substrate also includes a gate drive circuit and a data drive circuit, the gate drive circuit inputs scan signals to the gate lines, and the data drive circuit inputs data signals to the data lines. The gate driving circuit and the data driving circuit are arranged outside the pixel array.

FIG. 1 is a top view of an array substrate in the prior art. As shown in FIG. 1 , an array substrate 1 includes a pixel array 2 , a plurality of gate lines 4 and a plurality of data lines 3 . The gate lines 4 and the data lines 3 need to be connected to the driving chip 6 , and the driving chip 6 provides driving signals for the gate lines 4 and the data lines 3 . The gate line 4 is connected to the drive chip 6 through the gate line connection part 4-1, and the gate line connection part 4-1 is arranged on both sides of the pixel array 2, so the gate line connection part 4-1 is on the array substrate 1 Part of the area is occupied, resulting in a wider frame of the array substrate 1 .

Contents of the invention

In view of this, the present invention provides an array substrate and a display device including the array substrate.

The present invention provides an array substrate, comprising: a pixel array, the pixel array includes a plurality of pixel units, the pixel units are arranged in a matrix of m rows×n columns, and m and n are both positive integers;

The array substrate further includes a plurality of gate lines extending along the row direction, a plurality of data lines and scanning lines extending along the column direction, and the scanning line is connected to one of the gate lines and is insulated from the rest of the gate lines;

The first routing area and the second routing area, between two adjacent columns of pixel units is the first routing area or the second routing area, and the first routing area and the second routing area are arranged alternately along the row direction two data lines are arranged in each first routing area, and at most one scanning line is arranged in each second routing area.

The present invention also provides a display device, including: the array substrate provided by the present invention.

Compared with the prior art, the present invention has at least one of the following outstanding advantages: not only the narrow frame; but also the scanning line and the data line are arranged in parallel and the pixel unit is arranged between the scanning line and the data line, which reduces the distance between the two. Interference, that is, reduces the voltage coupling on the data line, and solves the problem that some pixels of the display device are too bright when the display device is in a low-middle gray scale.

Description of drawings

FIG. 1 is a top view of an array substrate in the prior art;

Fig. 2 is a top view of an array substrate in the present invention;

Fig. 3 is a top view of another array substrate in the present invention;

Fig. 4 is a top view of another array substrate in the present invention;

Fig. 5 is a top view of a pixel unit;

Fig. 6 is a sectional view along AA' line and BB' line among Fig. 5;

Fig. 7 is a top view of another pixel unit;

Fig. 8 is a sectional view along CC' line and DD' line among Fig. 7;

Fig. 9 is a top view of another pixel unit;

Fig. 10 is a sectional view along EE' line and FF' line among Fig. 9;

Fig. 11 is a top view of another array substrate in the present invention;

Fig. 12 is a sectional view along GG' line among Fig. 11;

Fig. 13 is a top view of another array substrate in the present invention;

Fig. 14 is a sectional view along HH' line among Fig. 13;

Fig. 15 is another kind of sectional view along EE ' line and FF ' line among Fig. 9;

Fig. 16 is a top view of another pixel unit;

Fig. 17 is a sectional view along II' line and JJ' line among Fig. 16;

detailed description

In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described below in conjunction with the accompanying drawings and embodiments.

It should be noted that in the following description, specific details are set forth in order to fully understand the present invention. However, the present invention can be implemented in many other ways than those described here, and those skilled in the art can make similar extensions without departing from the connotation of the present invention. Accordingly, the present invention is not limited to the specific embodiments disclosed below.

FIG. 2 is a schematic diagram of an array substrate in the present invention. Please refer to FIG. 2 , the array substrate 100 includes a pixel array 110 , and the pixel array 110 includes a plurality of pixel units 111 . It should be noted that the pixel unit 111 includes a thin film transistor composed of a gate, a source, and a drain, and a pixel electrode. Structures such as thin film transistors and pixel electrodes in each pixel unit. A plurality of pixel units 111 are arranged in a matrix of m rows×n columns, and both m and n are positive integers.

The array substrate 100 further includes a plurality of gate lines 10 extending along the row direction X and a plurality of data lines 20 extending along the column direction Y. The gate lines 10 and the data lines 20 are used to drive the pixel units 111 . The array substrate 100 also includes a plurality of scan lines 30 extending along the column direction Y. The scan line 30 is connected to one of the gate lines 10 and is insulated from the other gate lines 10 . It should be noted that, in the present invention, the row direction X and the column direction Y are perpendicular to each other, but the present invention is not limited thereto.

The array substrate 100 also includes a first wiring area 120 and a second wiring area 130, between two adjacent columns of pixel units 111 is the first wiring area 120 or the second wiring area 130, the first wiring area 120 and the second wiring area 130 are arranged alternately along the row direction X, and each first wiring area 120 is provided with two data lines 20, and each data line 20 is adjacent to it, that is, the nearest column The pixel units 111 are connected. One scan line 30 is disposed in each second wiring area 130 .

In the present invention, when the number of the second routing area 130 is greater than the number of scanning lines 30, please refer to FIG. 3. The difference between FIG. 3 and FIG. 2 is that when the number of the second routing area 130 is large Due to the number of scanning lines 30 , there are no scanning lines in part of the second routing area 130 - 1 , so in the present invention, there is at most one scanning line 30 in the second routing area 130 .

In the present invention, the array substrate 100 further includes dummy lines. As shown in Figure 4, taking m=5, n=14 as an example, the pixel array 100 includes 5 gate lines 10, 5 scan lines 30, 6 second wiring areas 130, and 5 second wiring areas One scan line 30 is set in 130, so there is one more second wiring area 130-2 without a scan line. When the second wiring area 130-2 does not have a scanning line, there is an unbalanced influence of the data line 20 on the pixel unit 111. In order to avoid this influence, a dummy line 50 can be set in the second wiring area 130-2. , to balance the capacitive coupling effect on the pixel electrodes and improve the display quality. The setting method of the virtual line 50 is the same as that of the scanning line 30 , both of which extend along the column direction Y, but the virtual line 50 is not connected to the gate line 10 in essence, and can be suspended or connected to a voltage of 1/2V. The second wiring area 130 for setting the scan line 30 and the second wiring area 130 - 2 for setting the dummy line 50 can be distributed in any combination.

In the present invention, when the number of the second wiring area 130 is less than the number of the scan lines 30 , the redundant scan lines 30 can be arranged on one side or both sides of the pixel array 110 .

In the present invention, preferably, the first wiring area is between the pixel units in the first column and the pixel units in the second column. If n is an odd number, a single data line 20 is provided for the pixel units in the nth column. When there is a second wiring area between the pixel units in the first column and the pixel units in the second column, one data line 20 needs to be separately provided for the pixel units in the first column and/or the nth column.

Please continue to refer to FIG. 4 , in the present invention, a data drive circuit 140 and a scan drive circuit 150 are also provided on the first substrate 100 , each data line 20 is connected to the data drive circuit 140 , and the data drive circuit 140 provides data lines 20 Data signal; each gate line 10 is connected to the scan driving circuit 150 through a scan line 30 , and the scan drive circuit 150 provides scan signals for the gate lines 10 . Both the data driving circuit 140 and the scanning driving circuit 150 are disposed on the same side of the pixel array 110 .

In the present invention, there are two ways to connect the scan lines 30 and the gate lines 10:

In the first connection method, in the preparation process of the array substrate 100, the same photolithography or mask can be used to make part of the wiring of the gate line 10 and the scanning line 30 on the same film with the same material. Layer, in the connection part, the scan line 30 intersects with one of the gate lines 10 to realize connection; in the insulation part, the scan line 30 uses a bridge to insulate from the rest of the gate lines 10, or the gate line 10 uses a bridge to insulate from the rest of the scan lines. Wire 30 is insulated.

In order to clearly illustrate the relationship between the film layers on the array substrate 100 in the present invention, the structure of a specific pixel unit is shown in FIG. The connected data line 20 , the pixel electrode 13 connected to the drain electrode 11 , and the scanning line 30 . The scan line 30 includes a multi-segment scan line portion 31 and a plurality of scan jumper portions 32 , and the scan jumper portion 32 includes a scan connection hole 33 and a scan connection portion 34 . The pixel unit 111 also includes a common electrode, which is not shown because it is not directly related to the invention of this embodiment.

Please refer to Figure 6. It should be noted that, in order to clearly illustrate the positional relationship of different film layers at different positions, Figure 6 is divided into two parts, wherein the first part is a cross-sectional view along the line AA' in Figure 5; the second part is Sectional view along line BB' in Fig. 5.

Please continue to refer to FIG. 6 , the array substrate 100 includes a source 11 , a drain 12 , a gate 15 , a pixel electrode 13 , a gate line 10 and a gate insulating layer 50 . The scan line 30 includes a multi-segment scan line part 31 and a plurality of scan jumper parts 32, the scan line part 31 and the scan jumper part 32 are in different layers, the scan jumper part 32 includes a scan connection hole 33 and a scan connection part 34, and the scan line part 31 and the scan jumper part 32 are in different layers. The wiring part 31 is on the same layer as the gate line 10 , and the scanning connection part 34 is on the same layer as the data line 20 . At the position where the scanning line 30 needs to be insulated from the gate line 10, two adjacent sections of the scanning line 31 are connected through the scanning connection part 34 and the two scanning connection holes 33, so as to avoid intersecting with the gate line 10 to achieve insulation . At the same time, since the multi-segment scanning line part 31 and the multiple scanning jumper parts 32 of the scanning line 30 can be formed by using existing film layer etching, this technical solution can be realized without increasing the mask.

In the first connection mode between the scan line 30 and the gate line 10, please refer to FIG. 7. FIG. 7 is a top view of another pixel unit. The difference between FIG. 7 and FIG. 5 is that the gate line 10 is set A plurality of gate wiring parts 11 and a plurality of gate jumper parts 12 , the gate jumper parts 12 include a gate connection hole 13 and a gate connection part 14 .

Please refer to Figure 8, Figure 8 is divided into two parts, wherein the first part is a cross-sectional view along line CC' in Figure 7; the second part is a cross-sectional view along line DD' in Figure 7. The gate wiring part 11 and the gate jumper part 12 are in different layers, the gate jumper part 12 includes a gate connection hole 13 and a gate connection part 14, the gate wiring part 11 and the scanning line 30 are in the same layer, and the gate The connecting portion 14 is on the same layer as the data line 20 . Where the scan line 30 needs to be insulated from the gate line 10 , the gate line 10 is isolated from the scan line 30 through the gate jumper 12 .

The second connection mode between the scanning line 30 and the gate line 10 is: the scanning line 30 is in a different layer from the gate line 10 and a via hole is set on the film layer between the two, and the scanning line 30 passes through the via hole One of the gate lines 10 is connected. The specific implementation is as follows:

FIG. 9 is a top view of another pixel unit. Referring to FIG. 9, the pixel unit 111 has a gate line 10 connected to the gate 15, a data line 20 connected to the source 12, and a pixel electrode 13 connected to the drain 11. and scanline 30. Wherein, the scan line 30 is connected to a gate line 10 through a via hole 40 .

Please refer to Fig. 10, Fig. 10 is divided into two parts, wherein the first part is a sectional view along EE' line in Fig. 9; the second part is a sectional view along FF' line in Fig. 9 . The scanning line 30 and the data line 20 are arranged in the same film layer, and the gate insulating layer 50 has a via hole 40, and the scanning line 30 is connected to one of the gate lines 10 through the via hole 40, and is insulated from the other gate lines.

11 is a top view of another array substrate in the present invention. When the scanning lines 30 and the data lines 20 are arranged in the same film layer, the scanning lines 30 and the data lines 20 both extend along the column direction Y in the region where the pixel array 110 is located. There is no intersection problem, but the scan line 30 and the data line 20 need to be connected to the data drive circuit 140 and the scan drive circuit 150 respectively, in the area A between the pixel array 110 and the data drive circuit 140 and the scan drive circuit 150, there is The problem that the data driving circuit 140 and the scanning driving circuit 150 intersect. In order to solve this technical problem, it is necessary to arrange the scan lines 30 and the data lines 20 in different film layers in the region A. The data line 20 includes a first data line part 20-1, a second data line part 20-2 and a data line changing hole 21, and the data line changing hole 21 connects a data line part 20-1 and the second data line part 20 -2. The first data line portion 20 - 1 extends along the column direction Y in the region where the pixel array 110 is located, and the first data line portion 20 - 1 and the scan line 30 are arranged in the same film layer.

Please refer to FIG. 12. FIG. 12 is a cross-sectional view along line GG' in FIG. , the data line changing hole 21 connects the first data line part 20-1 and the second data line part 20-2. In the region A, the scan lines 30 and the data lines 20 are in different layers, avoiding intersection.

In this embodiment, the data line 20 can also be kept on the same film layer, and the scanning line 30 can be switched to the film layer where the gate line 10 is located in the area A to avoid intersecting with the data line 20 . Please refer to FIG. 13 . The difference between FIG. 13 and FIG. 11 is that the scan line 30 includes a first scan line portion 30 - 1 , a second scan line portion 30 - 2 and a scan line replacement hole 31 . The first scan line portion 30 - 1 extends along the column direction Y in the region where the pixel array 110 is located, and the data lines 20 of the first scan line portion 30 - 1 are disposed on the same film layer.

Please refer to FIG. 14. FIG. 14 is a cross-sectional view along line HH' in FIG. , the first scan line part 30 - 1 is connected to the second scan line part 30 - 2 through the scan line changing hole 31 . In the region A, the scan lines 30 and the data lines 20 are in different layers, avoiding intersection.

In the second connection mode between the scanning lines 30 and the gate lines 10, the array substrate 100 can also include touch electrodes and touch electrode leads, and the touch function can be integrated into the array substrate 100, which can reduce the overall thickness of the module. .

Referring to Fig. 15, Fig. 15 is divided into two parts, wherein the first part is a sectional view along EE' line in Fig. 9; the second part is a sectional view along FF' line in Fig. 9 . In FIG. 15 , the array substrate 100 further includes touch electrodes 14 and touch electrode leads 16 , and the touch electrodes 14 are connected to the driving unit disposed on the array substrate through the touch electrode leads 16 . In this case, the scan line 30 and the touch electrode lead 16 can be fabricated on the same layer using the same photolithography or mask, and the scan line 30 is connected to one of the gate lines 10 through the via hole 40 .

The array substrate 100 in the above embodiments can use amorphous silicon (a-Si), oxide (IndiumGalliumZincOxide, IGZO) or low temperature polysilicon (LowTemperaturePoly-Silicon, LTPS) to make thin film transistor switches (TFT switches). When low temperature polysilicon (LTPS) is used to make the TFT switch, the structure of the pixel unit 111 is shown in FIG. Fig. 17 is a cross-sectional view along line II' and line JJ' in Fig. 16, the array substrate 100 also includes a light-shielding layer 17, a gate 15, a source 12, and a drain 11, because other film layers or structures are not directly related to the present invention. relationship and is therefore not shown. The material of the light-shielding layer 17 is, for example, molybdenum-aluminum alloy, chromium metal, molybdenum metal, or other materials with both light-shielding function and conductive properties. Formed by etching with the same mask. The scan line 30 is connected to one of the gate lines 10 through a via hole 40 .

The present invention also provides a display device comprising the above-mentioned array substrate 100 . The display device may include: a liquid crystal panel, a liquid crystal TV, a mobile phone, a computer, and the like.

The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be assumed that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deduction or replacement can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (11)

1. An array substrate, characterized in that, comprising: A pixel array, the pixel array includes a plurality of pixel units, the pixel units are arranged in a matrix of m rows×n columns, and both m and n are positive integers; a plurality of gate lines extending along the row direction, A plurality of data lines and scan lines extending along the column direction, The scan line is connected to one of the gate lines and is insulated from the other gate lines, The first wiring area and the second wiring area, the first wiring area or the second wiring area between two adjacent columns of pixel units, The first routing area and the second routing area are arranged alternately along the row direction; Two data lines are arranged in each first wiring area, and at most one scanning line is arranged in each second wiring area. 2. The array substrate according to claim 1, wherein the array substrate further comprises a dummy line, the second wiring area includes at most one scanning line or at most one dummy line, and the dummy line wires are insulated from the gate wires. 3. The array substrate according to claim 1, wherein the array substrate further comprises a data driving circuit and a scanning driving circuit, the data driving circuit provides data signals for the data lines, and the scanning driving circuit passes The scanning lines provide scanning signals for the gate lines, and the data driving circuit and the scanning driving circuit are arranged on the same side of the pixel array. 4. The array substrate according to claim 1, wherein the scan lines comprise: a multi-segment scan line part and a plurality of scan bridge parts on different layers from the scan line part, The scanning jumper connects two adjacent sections of the scanning line, The scan wiring part and the gate line are in the same layer. 5. The array substrate according to claim 1, wherein the gate lines comprise: a multi-segment gate wiring part and a plurality of gate jumper parts in different layers from the gate wiring part, The gate jumper connects two adjacent sections of the gate wiring, The gate wiring part is in the same layer as the scan line. 6 . The array substrate according to claim 1 , further comprising a via hole, and the scan line is connected to one of the gate lines through the via hole. 7. The array substrate according to claim 6, characterized in that, Each of the scanning lines includes a first scanning line part, a second scanning line part and a scanning line changing hole, The first scan line part is in a different layer from the second scan line part and is connected through the scan line replacement hole, The first scan line part is on the same layer as the data line. 8. The array substrate according to claim 6, characterized in that, Each of the data lines includes a first data line part, a second data line part and a data line changing hole, The first data line part and the second data line part are in different layers and connected through the data line changing hole, The first data line part is on the same layer as the scan line. 9 . The array substrate according to claim 6 , further comprising a light-shielding layer, and the scan lines are in the same layer as the light-shielding layer. 10 . The array substrate according to claim 6 , wherein the array substrate further comprises touch electrodes and touch electrode leads, and the scan lines are on the same layer as the touch electrode leads. 11 . 11. A display device, comprising: the array substrate according to any one of claims 1-10.