TWI746331B - Control method for flash memory, flash memory die and flash memory - Google Patents

Abstract

A control method for flash memory is provided. The control method comprises: in a setup stage, under an operation mode of command input, issuing by a host a setup command to map each port of an external data bus of each flash memory die respectively to a status index of each flash memory die; and in a request stage, under the operation mode of command input, issuing by the host a request command to each flash memory dies, and under the operation mode of data output, transmits status of the status index of each flash memory die to the host through the ports of the external data bus respectively.

Description

Flash memory control method, flash memory die and flash memory

The present invention relates to a flash memory, and more particularly to a control method of the flash memory and the flash memory die.

At present, NAND flash memory controllers are facing a large increase in the number of NAND flash memory dies to be controlled, which results in an increase in the number of controller pads and the size of the dies. In addition, the ready/busy (R/B) signals of all logic units are also connected to the shared R/B signal line. Therefore, if you want to know which logical unit is busy when the shared R/B signal line is busy, you need to issue a "read status command" to inquire whether the specified logical unit is ready or busy.

Generally speaking, the implementation of the R/B state of the NAND flash memory uses an open drain design. FIG. 1 shows a schematic diagram of an open drain circuit of a NAND flash memory. As shown in Figure 1, there are multiple NAND flash memories in one channel Bulk dies 0, 1, 2,... and their R/B state outputs are respectively connected to a common open-drain output. Figures 2A and 2B show that there are currently two design methods for multi-channel NAND flash memory.

As shown in Figure 2A, in this architecture, the R/B signal lines of each NAND flash die in each channel are independent, that is, each flash die 10_0~ 10_m-1 are each set up with a R/B signal line to connect to the multi-channel flash memory controller 20, so in each channel, the multi-channel flash memory controller 20 should also be set to be the same as the R/B signal line. The number of corresponding pads.

Figure 2B shows another architecture of multi-channel NAND flash memory. As shown in Figure 2B, in this design, each flash memory die 10_0~10_m-1 in each channel shares one R/B The signal lines are short-circuited together. However, under this architecture, the multi-channel flash memory controller 20 will not be able to know which NAND flash memory die 10_0~10_m-1 is busy, and extra time must be spent to confirm each flash memory. The ready/busy state of the body crystal grains 10_0~10_m-1. In other words, under this architecture, although the number of pads can be saved, additional time is needed to confirm the ready/busy status of each flash memory die 10_0~10_m-1.

Therefore, there is a need in the technical field for a technical method that can reduce the number of pads on the one hand, and on the other hand, it does not require extra time to confirm whether each flash memory is in a busy state.

According to an embodiment, the present invention provides a flash memory controller Method, wherein the flash memory has an external data bus connected to a plurality of flash memory dies. The control method includes: in the setting stage, in the operation mode of command input, the main controller sends a setting command to map each port of the external data bus to the state indicator of each flash memory die; And in the request phase, in the operation mode of command input, the main controller sends a request command to each of the plurality of flash memory dies, and in the operation mode of data output, each flash The state of the state indicator of the memory die is transmitted to the main controller through each port of the corresponding external data bus.

In the above-mentioned multi-channel flash memory control method, in the setting stage, sending a setting command from the main controller further includes: in the command input operation mode, the main controller sends a preparation command to notify each of the multiple The flash memory die is ready to assign each port of the external data bus to the status indicator of each of the plurality of flash memory die; and in the operation mode of address input, the The host controller sends out an address signal, thereby mapping each port of the external data bus to the state indicator of each of the plurality of flash memory dies.

In the above flash memory control method, each of the flash memory die has a plurality of output ports respectively coupled to each port of the external data bus; in the setting stage, the plurality of flash memory The first output port of one of the first flash memory dies of one of the flash memory dies is selected to transmit the status indicator. Wherein, the output port corresponding to the first output port of each flash memory die other than the first flash memory die among the plurality of flash memory die is an output High-impedance state; output ports other than the first output port of the first flash memory output a high-impedance state.

In the above flash memory control method, the status indicator can be a ready/busy status for the master controller. In the above flash memory control method, the setting command and the request command can be defined by manufacturer-specific commands. In the above flash memory control method, the main controller may be a multi-channel flash memory controller. According to another embodiment, the present invention provides a flash memory die, which at least includes: a plurality of ports, the plurality of ports are coupled to an external data bus; a control logic unit that provides the flash memory A state indicator of the die; a mapping state register for storing data for selecting one of the multiple ports corresponding to the state indicator of the flash memory die; and input / Output control unit. The input/output control unit further includes a first multiplexer and a demultiplexer. The first multiplexer has multiple inputs and outputs, the multiple inputs respectively receive data from multiple sets of internal buses, the output is coupled to the multiple ports, and the first multiplexer is based on The selection signal provided by the control logic unit selects one of the multiple inputs and outputs it to the external data bus. The multiple sets of internal buses include at least an internal data bus, a state indicator bus, and a mapping state bus Row. The demultiplexer has an input, a plurality of outputs, and a selection line, wherein the input receives the state indicator, the selection line receives the data stored in the mapping state register, and the demultiplexer The output of is connected to the input of the first multiplexer via the mapping state bus, wherein the demultiplexer selects based on the data received by the select line Selecting one of the multiple outputs of the demultiplexer to transmit the state indicator, and the unselected output of the demultiplexer is output with a high impedance.

In the above flash memory die, when the flash memory die receives a setting command sent by the main controller, the status indicator of the flash memory die is mapped to the multiple ports one.

In the above flash memory die, when the flash memory die receives a request command from the main controller, the demultiplexer of the input/output control unit temporarily stores according to the mapping state Select the port corresponding to the state indicator of the flash memory die, and transmit the state of the state indicator to the host through the selected port.

In the above-mentioned flash memory die, when the request command is received, the unselected port among the plurality of ports is in a high impedance state.

In the above-mentioned flash memory die, the setting command and the request command can be defined by manufacturer-specific commands. In the above flash memory die, the main controller can be a multi-channel flash memory controller. In the above-mentioned flash memory die, the status indicator is the ready/busy status for the master controller.

In the above flash memory die, the input/output control unit further includes a second multiplexer, the output of the second multiplexer is coupled to the input of the demultiplexer for switching from a plurality of states The register selects one and outputs it to the demultiplexer.

In the above flash memory die, the input/output control unit further includes: a multiplexer unit coupled to the demultiplexer, wherein the multiplexer unit includes a plurality of multiplexers. Each of the multiple multiplexers receives multiple status registers. The stored state is selected from the plurality of state registers and output to the demultiplexer. The outputs of the multiple multiplexers are provided to the demultiplexer and input to the first multiplexer via the mapping state bus.

According to another embodiment, the present invention provides a method for controlling a flash memory, wherein the flash memory has an external data bus connected to a plurality of flash memory dies. The control method includes: sending a setting command from a main controller to correspond each port of the external data bus with the state indicator of each flash memory die; and sending the main controller to each of the The flash memory die sends a request command; when each of the plurality of flash memory dies receives the request command, the state of the state indicator of each of the plurality of flash memory dies is correlated The corresponding ports of the external data bus are sent to the main controller.

In the above flash memory control method, sending a setting command from the main controller further includes: sending a preparation command to notify each of the plurality of flash memory dies to prepare for each port of the external data bus Respectively assigned to each of the plurality of flash memory dies; and sending an address signal, thereby connecting each port of the external data bus of each of the plurality of flash memory dies to each of the plurality of flash memory dies. The state indicators of each flash memory die correspond to each other.

In the above flash memory control method, each of the flash memory dies has a plurality of output ports respectively coupled to the ports of the external data bus; among the plurality of flash memory dies The first output port of one of the first flash memory dies is selected to transmit the status indicator. Wherein, each of the flash memory dies other than the first flash memory die in the plurality of flash memory dies The output port corresponding to the first output port of the chip is in the output high impedance state; the output ports other than the first output port of the first flash memory output the high impedance state.

In the above flash memory control method, the status indicator can be a ready/busy status for the master controller. In the above flash memory control method, the setting command and the request command can be defined by manufacturer-specific commands. In the above flash memory control method, the main controller may be a flash memory controller.

According to another embodiment, the present invention provides a flash memory, which includes: at least one external data bus having multiple ports; a plurality of flash memory dies, respectively coupled to the at least one external bus; And a main controller, coupled with the at least one external bus, for controlling the plurality of flash memory dies. Wherein, in the setting phase, the main controller sends a setting command to correspond each port of the external data bus with the state indicator of each flash memory die; in the request phase, the main controller The controller sends a request command to each of the flash memory dies, and receives the request command in each of the plurality of flash memory dies, and sends all the flash memory dies to each of the plurality of flash memory dies. The status of the status indicator is transmitted to the main controller through each port of the corresponding external data bus.

In the above flash memory, sending a setting command from the main controller further includes: sending a preparation command to notify each of the plurality of flash memory dies to prepare to assign each port of the external data bus to Each of the plurality of flash memory dies; and sending an address signal, whereby each port of the external data bus of each of the plurality of flash memory dies and each of the plurality of flashes The state of the memory die refers to Corresponding to the standards.

In the above flash memory control method, in the above flash memory control method, each of the flash memory dies has a plurality of output ports respectively coupled to each port of the external data bus; The first output port of one of the first flash memory dies of one of the plurality of flash memory dies is selected to transmit the status indicator. Wherein, the output port corresponding to the first output port of each flash memory die other than the first flash memory die in the plurality of flash memory die is in an output high impedance state ; Output ports other than the first output port of the first flash memory output a high impedance state.

In the above-mentioned flash memory, the status indicator can be used as a ready/busy status for the master controller. In the above flash memory control method, the setting command and the request command can be defined by manufacturer-specific commands.

In summary, under the architecture of this embodiment, the manufacturer-specific commands are used and the data bus is used to double as the R/B signal line of the flash memory die, so the original flash memory die can be saved. R/B signal lines and pads, so the flash memory controller does not need this R/B pad correspondingly, and the number of pads of the controller can be effectively reduced.

10_0~10_m-1: NAND flash memory die

20: Flash memory controller

100_0~100_m-1: NAND flash memory die

102: Logic Control Unit

104: Input and output unit

106, 106a: mapping status register

106b: State selection register

108: R/B signal status (internal)

110: high voltage circuit

112: Command register

114: Address register

116: Status register

118: data buffer

120: memory array

122: Y-decoder

124: X-decoder

126: page buffer

130, 132’: Demultiplexer

130a, 130’a: decoder

130b_0~130b_7, 130’b_0~130’b_7: Three-state gate

131, 132: Multiplexer

132’: Multiplexer unit

132a, 132’a: decoder

132’b_0~132’b_7: Multiplexer

200: Flash memory controller

FIG. 1 is a schematic diagram of an open-drain output of a conventional NAND flash memory die structure.

2A and FIG. 2B are schematic diagrams depicting the structure of a conventional NAND flash memory.

FIG. 3A shows a schematic diagram of a flash memory structure according to an embodiment of the present invention.

FIG. 3B shows a schematic diagram of the structure of a NAND flash memory die according to an embodiment of the present invention.

3C and 3D further show schematic diagrams of the circuit structure of the I/O control unit in the flash memory die shown in FIG. 3B.

FIG. 3E is a schematic diagram of the circuit structure of the demultiplexer in FIG. 3D.

FIG. 4A is a schematic diagram showing the structure of another NAND flash memory die according to an embodiment of the present invention.

FIG. 4B is a schematic diagram of the circuit structure of the I/O controller unit in FIG. 4A.

FIG. 5 is a schematic diagram of the circuit structure of the I/O control unit in the flash memory die of another embodiment.

FIG. 6A is a timing diagram of the operation flow of each flash memory die in the NAND flash memory control method according to an embodiment of the present invention.

FIG. 6B is a timing diagram of another embodiment of the operation flow of the setting stage of each flash memory die in the NAND flash memory control method of another embodiment of the present invention.

FIG. 7A is a schematic diagram showing the operation flow of the main controller for multiple NAND flash memory dies on a channel according to an embodiment of the present invention.

FIG. 7B is a schematic diagram of the operation flow of another embodiment in the setting stage of FIG. 7A.

FIG. 8 shows the operation sequence of the flash memory controller according to the embodiment of the present invention intention.

FIG. 3A shows a schematic diagram of a flash memory structure according to an embodiment of the present invention. FIG. 3B shows a schematic diagram of the structure of a NAND flash memory die according to an embodiment of the present invention, that is, a schematic diagram of the structure of each NAND flash memory die in each channel in FIG. 3A. Although FIG. 3A illustrates the architecture of a multi-channel flash memory, the description of this embodiment will take one of the channels as the object of description. The method and architecture of this embodiment are applicable to single-channel or multi-channel situations.

As shown in Figure 3A, the NAND flash memory controller 200 or the host 200 can be connected with n channels (0~n-1) of flash memory strings, and the flash memory of each channel Each string can contain multiple flash memory dies. For example, each NAND flash memory channel 0~n-1 has m NAND flash memory dies 100_0~100_m-1. In addition, the m NAND flash memory dies 100_0~100_m-1 of each channel have at least chip enable signals (CE_0~CE_m-1), which are respectively connected to the NAND flash memory controller 200. In addition, the input control unit of each NAND flash memory die 100_0~100_m-1 can send and receive data through the data bus (external data bus) DQ and the NAND flash memory controller 200.

Furthermore, as shown in Figure 3A, in this architecture, each NAND flash memory die 100_0~100_m-1 does not use R/B pads as in the prior art to communicate with each NAND flash memory. Corresponding equipment for body crystal grains 100_0~100_m-1 Transmission of proper and busy status (status indicator signal). According to the embodiment of the present invention, this embodiment will use each port of the data bus DQ (take 8 ports as an example, such as DQ[7:0]) for each NAND flash memory die 100_0~100_m- Transmission of 1 R/B signal. In other words, this embodiment maps the internal R/B # port to the designated DQ port to detect the R/B status of the NAND flash memory die 100_0~100_m-1.

The status indicators here can be the various internal states and parameters of the flash memory of each channel, such as the ready/busy state for the master (R/B# for host), the ready/busy state for the flash array (R/ B# for flash array) and so on. In this embodiment, the ready/busy status (R/B# for host) of the master is used as an example of the status indicator. In this way, this embodiment will not use external R/B pads and signal lines, so the number of pads of the controller can be reduced. The detailed operation method will be detailed later. The ready/busy state for the master controller refers to whether the data buffer in the flash memory die (data buffer 118 in Figure 3B) is empty, to indicate whether it can receive the next data from the master controller , But the data has not yet been written to the memory array. The ready/busy status of the flash array indicates whether the data is actually written into the memory array.

FIG. 3B shows a schematic diagram of the structure of a NAND flash memory die according to an embodiment of the present invention. As shown in Figure 3B, NAND flash memory die 100_0 (the structure of NAND flash memory die 100_1~100_m-1 is the same) is basically the same as the structure of general NAND flash memory die. The difference lies in Add a circuit block that maps the R/B signal line and the DQ port to each other.

As shown in FIG. 3B, the NAND flash memory die 100_0 of this embodiment also has a control logic unit 102, an input and output control unit 104, a memory array 120, an X-decoder 124, a Y-decoder 122, and a page The basic circuit blocks of the buffer 126, the high voltage circuit 110, the command register 112, the address register 114, the status register 116, the data buffer 118, the data bus DQ, and so on. The function and operation of the basic circuit block of the NAND flash memory die 100_0 are basically the same as or similar to the existing architecture, and the actual architecture does not affect the implementation of this embodiment, so the detailed description is omitted here.

According to this embodiment, the NAND flash memory die 100_0 has at least a mapping state register 106. In this embodiment, the mapping of R/B to the DQ port 106 is taken as an example. The mapping state register 106 is used to store the one-to-one correspondence between the ports DQ0~DQ7 of the data bus DQ and the internal R/B lines of the flash memory die 100_0~100_m-1, respectively. That is, the mapping status register 106 in the NAND flash memory die 100_0 will store information indicating which DQ port the NAND flash memory die 100_0 should use to output the R/B status of the master controller. material. For example, if the NAND flash memory die 100_0 needs to use DQ0 as the output, the data stored in the mapping status register 106 will record, for example, the value "0", and the other NAND flash memory die 100_1~100_m- 1 and so on. That is, each NAND flash memory die only stores the DQ port it wants to use in its mapping state register 106. In the main controller (flash memory controller 200), a correspondence table can be stored. This correspondence table can record which NAND flash memory each port (DQ[7:0]) in the channel is used to output State indicator of the die.

Thereby, when the NAND flash memory controller 200 sends a request signal (the request stage will be detailed later) to each flash memory die 100_0~100_m-1 to obtain the status of the R/B signal, each flash The input and output control unit 104 of the memory die 100_0~100_m-1 can send out R/B signals at the corresponding DQ port. In this way, the NAND flash memory controller 200 obtains the R/B signal status of each flash memory die 100_0~100_m-1 from each port DQ0~DQ7 in the data bus DQ at a time.

Through the above structure, the logic control unit 102 does not need to use internal R/B signals to transmit the R/B state through the R/B pads of the input and output control unit 104, so there is no need for external R/B signal lines and connections. pad. Therefore, the NAND flash memory controller 200 does not need to be provided with corresponding R/B pads, so the number of pads can be reduced. As shown by the dashed line in the lower left corner of FIG. 3B, this embodiment can completely omit this part of the hardware architecture.

3C and 3D further show schematic diagrams of the circuit structure of the I/O control unit 104 in the NAND flash memory die shown in FIG. 3B. The NAND flash memory die shown in FIG. 3C and FIG. 3D only depict the circuit blocks related to this embodiment, and the remaining parts are omitted. As shown in FIG. 3C, the I/O control unit 104 may further include a multiplexer 131 (first multiplexer), which may have multiple sets of internal busbars as input. Each group of bus bars is composed of 8 signal lines, for example. Through these internal buses, the multiplexer 131 can select one of multiple sets of inputs according to the selected signal line of the logic control unit 102, that is, the internal data bus (general data transmission), the status bus (flash memory) The state indicator) or one of the mapping state buses (such as RB to DQ port) to output to the port (DQ[7:0]) output. DQ bus can output a variety of output The output signal, such as data, flash memory status or RB status in this embodiment (i.e., RB to DQ port). In this embodiment, the status indicator is the R/B status for the main controller. In addition, the mapping status register 106 stores data indicating which port is to be used as the output R/B (status). As shown in FIG. 3D, the demultiplexer 130 has an input, multiple outputs, and selection lines. The output of the demultiplexer 130 and one of the inputs of the multiplexer 131 can be connected to a state bus ([7:0]). The input of the demultiplexer 130 receives the R/B state signal for the main controller. The select line of the demultiplexer 130 receives the data stored in the mapping state register 106, and accordingly transfers the master controller of the flash memory die from the corresponding port (mapping state bus ([ 7:0]) one of) output. Accordingly, the multiplexer 131 of FIG. 3C can output the R/B state for the master from the corresponding port.

In addition, FIG. 3E shows a schematic diagram of the circuit structure of the demultiplexer 130 in 3D. As shown in FIG. 3E, the demultiplexer 130 may further include a decoder 130a and a plurality of pass gates. In this example, a tri-state gate is used as an example of a strobe gate. Three-state gates 130b_0~130b_7 (in this example, there are eight, corresponding to DQ[7:0]). The output of each tri-state gate 130b_0~130b_7 is connected to its corresponding DQ port DQ[7:0]. The decoder 130a can receive and decode the data from the R/B to DQ port register 106, so that the R/B state of the main controller of the input demultiplexer 130 can pass through the tri-state gate 130b_0 corresponding to the data. One of ~130b_7, and output from the corresponding DQ port. For example, if the NAND flash memory die 100_1 is to use DQ1 as the output port of the R/B state for the main controller, the mapping state register 106 will record "1". For example, when the value stored in the mapping status register 106 is 1, It means that the demultiplexer 130 will be converted to 0000_0010 through the decoder 130a, and the tri-state gates 130b_0~130b_7 will turn on DQ1 according to the received signal 0000_0010, and the remaining ports will become high impedance states. In other words, DQ1 will output R/B (status). At this time, the decoder 130a will enable the tri-state gate 130b_1 accordingly, and the remaining tri-state gates 130b_0, 130b_2~130b_7 will be disabled and become a high impedance state. Based on this, port DQ1 will be selected to output the R/B status of the master controller.

In addition, in this embodiment, each NAND flash memory die selects only one DQ port as the output of the status indicator (in this example, the master controller uses the R/B status). At this time, the DQ port that is not selected will be in a high impedance state.

As described above, the state of the internal R/B signal line can be transmitted to the NAND flash memory controller 200 through the data bus DQ by using the corresponding DQ port by the method of this embodiment. For example, the R/B signal line of the flash memory die 100_0 is mapped to the DQ port DQ0, the R/B signal of the flash memory die 100_1 is mapped to the DQ port DQ1, and so on.

Therefore, in this way, for multiple flash memory dies 100_0~100_m-1 in each channel, the NAND flash memory controller 200 can obtain the data from each port DQ0~DQ7 on the data bus DQ at one time. The R/B state of the flash memory die 100_0~100_m-1. Therefore, the NAND flash memory controller 200 does not require external R/B signal lines and pads, thereby effectively reducing the number of pads of the controller.

FIG. 4A is a schematic diagram showing the structure of another NAND flash memory die of this implementation, and FIG. 4B is a schematic diagram showing the circuit structure of the I/O controller unit in FIG. 4A. As shown in FIG. 4A, in addition to the mapping state register 106a, the I/O controller unit 104 also includes a state selection register 106b. The data stored in the mapping status register 106a can prompt which of the multiple DQ ports of the NAND flash memory die 100_0 (...100_m-1) should be used as the output of the status indicator, and the status selection register The data stored in 106b can prompt which of the multiple status indicators of the NAND flash memory die 100_0 (...100_m-1) is to be output.

In the descriptions of FIGS. 3B to 3E, a single state indicator is taken as an example, that is, the R/B state of the main controller is used as an example. However, as mentioned above, the application of the present invention is not limited to the R/B state of the main controller, but can also be other state indicators or parameters of the NAND flash memory die 100_0 (...100_m-1). In other words, in this embodiment, one of the multiple status indicators of each flash memory die 100_0 (...100_m-1) can be selected to output from the corresponding DQ port.

As shown in FIG. 4B, in the architecture of this embodiment, in addition to the demultiplexer 130, a multiplexer 132 (second multiplexer) is further included. In addition, the control logic unit 102 may also include a plurality of state registers, and may select one of them to output to the demultiplexer 132. The multiplexer 132 can receive the states stored in a plurality of state registers, such as the R/B state for the main controller, the R/B state for the flash array, and other states. In addition, the multiplexer 132 is further coupled to the state selection register 106b. The multiplexer 132 can select one output from a plurality of state registers such as the R/B state for the main controller, the R/B state for the flash array, and other states based on the data from the state selection register 106b. Therefore, the demultiplexer 130 can output the state selected by the state selection register 106b from the corresponding port according to the data stored in the mapping state register 106a.

As shown in FIG. 4B, the multiplexer 132 is coupled to the demultiplexer 130. The state index selected by the multiplexer 132 is then input to the demultiplexer 130. The operation mode of the demultiplexer 130 is the same as that described in FIGS. 3D and 3E. That is, the demultiplexer 130 can receive and decode the data from the mapping state register 106a, and accordingly, the state index selected by the multiplexer 132 can be specified by the data stored in the mapping state register 106a. The corresponding DQ port (selected by the multiplexer 131 of FIG. 3C) is output. Therefore, the multiplexer 132 can select one of the multiple status indicators to use the data bus DQ for status transmission.

That is, as shown in FIG. 4B, the multiplexer 132 selects the signal of the register 106b as the selection line according to the state, and selects from multiple states such as the R/B state for the master and the R/B state for the flash array. One of them is used as output. For example, the multiplexer 132 selects the output state as the R/B state for the flash array according to the state selector 106b. At this time, the demultiplexer 130 will receive the signal output by the multiplexer 132 (ie, the R/B state for the flash array), and decode it according to the data in the mapping state register 106a to obtain the selected output port this time For the sixth root. In this example, in the 8-port output result of the demultiplexer 130, ports 0 to 5 and port 7 are all high impedance, and port 6 is used to output the R/B state of the flash array.

Then, according to the selection line of the control logic unit 102, the multiplexer 131 (refer to FIG. 3C) will output the eight ports of the demultiplexer 130 (port 6 is the R/B state for the output flash array, and the rest are High impedance) as a group of options for the multiplexer 131 to select and output. Suppose that when the host controller issues the request command of this embodiment, the group of ports output by the eight ports of the demultiplexer 130 will be selected as DQ[7:0] and output.

According to this variation, the DQ port of the data bus DQ is not limited to only being mapped to a single state indicator, but can be dynamically selected by the master, that is, the NAND flash memory controller 200, to select the required state indicator from The data bus DQ performs status signal transmission, so the control of the NAND flash memory die can be operated in a more free manner. Except for the second multiplexer 132 and the state selection register 106b, the operation mode of the demultiplexer 130 is the same as that of FIG. 3D to FIG. 3E, so it will not be repeated here.

FIG. 5 is a schematic diagram of the circuit structure of the I/O control unit in the flash memory die of another embodiment. The difference between the embodiment shown in FIG. 5 and FIG. 4B lies in the circuit structure of the demultiplexer and the multiplexer. As shown in FIG. 5, the demultiplexer 130' includes, for example, a decoder 130'a and a plurality of tri-state gates 130'b_0~130'b_7 (take 8 as an example), and the decoder 130'a is further coupled to each Three-state gate 130'b_0~130'b_7. The multiplexer unit 132' further includes a decoder 132'a and a plurality of multiplexers 132'b_0~132'b_7 (take 8 as an example), and the decoder 132'a is further coupled to each multiplexer 132'b_0 ~132'b_7. Each multiplexer 132'b_0~132'b_7 of the multiplexer unit 132' is respectively coupled to the tri-state gate 130'b_0~130'b_7 of the demultiplexer 130'. In addition, each multiplexer 132'b_0~132'b_7 receives the states stored in a plurality of state registers, such as the R/B state for the main controller, the R/B state for the flash array, and other states.

The decoder 132'a of the multiplexer unit 132' receives data from the state selection register 106b and decodes it, so that each multiplexer 132'b_0~132'b_7 can select one of the state registers. For example, the multiplexer 132’b_0 can use the R/B state for the main controller, the R/B state for the flash array, and other states, etc. Multiple status registers are selected and output to the corresponding tri-state gate 130'b_0. The multiplexer 132'b_1 can use R/B status from the main controller, R/B status for flash array, and other statuses. The state indicators are selected and output to the corresponding tri-state gate 130'b_1, and the rest can be deduced by analogy. In addition, the decoder 130'a of the demultiplexer 130' can receive and decode the data from the mapping state register 106a, thereby enabling the corresponding tri-state gate 130'b_0~130'b_7, and each state indicator It can be output from the corresponding DQ port [7:0].

For example, the demultiplexer 130' will select which ports will be the output state, and the remaining ports will be high impedance. For example, the decoding result of the decoder 130'a is 0000_1100, which means that the ports 2 and 3 are used as status outputs, and the other ports are in a high impedance state. In addition, the state selection register 106b stores the state to be output by each port. The multiplexer (second multiplexer) 132' will determine which state each of the eight ports should select as the output. For example, if the decoded result of the decoder 132'a is 1111_1211, assuming that 1 represents the R/B state for the main controller, and 2 represents the R/B state for the flash array, then port 2 of the eight ports of the multiplexer 132' It will output the R/B status for the flash array, and the remaining ports are used as the R/B status for the output master (ie, ports 0, 1, 3-7). In addition, the eight output ports of the demultiplexer 130 finally obtained by the multiplexer 131 (refer to FIG. 3C) are: port 2 is in the R/B state for the flash array, port 3 is in the R/B state for the master controller, and the rest All 6 ports are high impedance.

In this embodiment, compared to the embodiment shown in FIG. 3E for a flash memory die that only assigns one DQ port to output the status indicator, a flash memory die can also assign multiple DQ ports, each DQ port can represent a status indicator. Therefore, for a flash memory die, the data bus DQ can be used, and at the same time Output multiple status indicators. In this embodiment, the flash memory die will have multiple status indicators to output. At this time, which DQ port should be used to output which status indicator output, the corresponding relationship will be stored in a data format in the status selection temporary storage器106b中.

Next, the actual operation method of the above-mentioned circuit structure will be described, and with reference to FIGS. 6A to 6C, it will be described in detail how the ports of the data bus DQ are mapped to the R/B signal lines in the embodiment of the present invention. Here, FIGS. 6A to 6C are explanatory diagrams illustrating the action sequence of a flash memory die after receiving a command from the main controller.

FIG. 6A is a schematic diagram of the operation sequence sequence of each flash memory die in the NAND flash memory control method according to an embodiment of the present invention, which is an explanatory diagram of the operation sequence of the flash memory die level. As shown in FIG. 6A, the control method of this embodiment uses the operation mode of the data bus DQ to be divided into two stages, namely the setup stage and the request stage. This embodiment mainly uses the time period when the data bus DQ is in the idle state. In this example, the data bus DQ has 8 ports as an example DQ0~DQ7, but the actual situation can be adjusted appropriately depending on the NAND flash memory die. In addition, the operation of the main controller level will be illustrated in FIG. 7A.

As shown in Figure 6A, in the setting phase, in the CMD input operation mode (based on the data transmission specification of the data bus DQ), the cycle pattern at this time is to set the R/B command. That is, each NAND flash memory die 100_0 (...100_m-1) receives the setup command sent by the NAND flash memory controller 200, that is, the host 200 Then, connect each port DQ0~DQ7 of the data bus DQ with each flash memory die in a channel of the flash memory Corresponds to the R/B status (status index) of 100_0~100_m-1.

Here, the setting command can use a vendor-specific command to correspond to each port DQ0~DQ7 of the data bus DQ of each NAND flash memory die 100_0~100_m-1 of each channel. For example, a general NAND flash memory die 100_0~100_m-1 can have 8 different vendor-specific commands, and each vendor-specific command can correspond to a specific DQ port. For example, command 20h can be assigned to port DQ0, command 21h can be assigned to port DQ1, etc., and so on. In this way, different vendor-specific commands can be used to assign corresponding ports to each port. That is, as shown in FIG. 6A, when the cycle type of the R/B command is set, the internal chip enable signal CE# enables the chip and sends a command 20h on DQ[7:0] of the data bus DQ.

In this way, through the setting stage, the manufacturer-specific commands can be used to map each port DQ0~DQ7 with the internal R/B signal lines of each NAND flash memory die, and the data used to indicate the corresponding relationship (Value) is stored in the R/B to DQ port register 106 shown in FIGS. 3B to 3E.

At the main controller level, in the setting phase, the operation flow diagram is shown in step S100 in Figure 7A. In the command input operation mode, the main controller (such as a flash memory controller) sends out the setting command to Each port DQ0~DQ7 of the data bus of each of the plurality of flash memory dies 100_0~100_m-1 is respectively mapped to the state indicator (R/B) of each of the flash memory dies 100_0~100_m-1 state).

6A again, then in the request stage (request stage), each NAND flash memory die 100_0 (...100_m-1) received by the NAND flash memory The body controller 200 sends a request command, that is, another manufacturer-specific command is sent to each NAND flash memory die 100_0~100_m-1.

In this request stage, as shown in FIG. 6A, when the operation mode is command input, the cycle type is request R/B command, that is, the NAND flash memory controller 200 will respond to each NAND flash memory die. 100_0~100_m-1 sends request commands to obtain the status of the R/B signal line of each NAND flash memory die 100_0~100_m-1. Then, in the data output operation mode, each NAND flash memory die 100_0~100_m-1 will use the corresponding port DQ0~DQ7, and each NAND flash memory die will be transferred via the data bus DQ. The R/B status of the master controller of the grains 100_0~100_m-1 is transmitted to the NAND flash memory controller 200.

For the main controller level, at the request stage, the schematic diagram of the operation flow is shown in step S200 of FIG. Send a request order. Next, in step S300, in the data output operation mode, each flash memory die 100_0~100_m-1 in each channel passes the state of the state indicator (the R/B state for the main controller) through the corresponding all Each port DQ0~DQ7 of the data bus is sent to the main controller.

In this way, the multiple flash memory dies 100_1~100_m-1 on the channel of the NAND flash memory controller 200 can obtain multiple flash memories at one time through each port DQ0~DQ7 of the data bus DQ The main controller of the bulk die 100_1~100_m-1 uses the R/B state, without the need for external R/B signal lines and pads, thereby reducing the number of pads of the controller.

FIG. 6B shows the control of NAND flash memory according to another embodiment of the present invention The operation sequence diagram of another embodiment of the setting stage of each flash memory die in the manufacturing method. FIG. 7B shows a schematic diagram of the operation flow of the setting stage of the main controller level.

As shown in FIG. 6B, in this embodiment, the setting phase may further include two cycles. In this embodiment, only the setting phase is different from the setting phase of FIG. 6A, and the requirement phase is basically the same. Therefore, I would like to explain the operation of the setup phase here.

As shown in FIG. 6B, in the setting phase, the operation mode is divided into two cycles, the first cycle is a command input (CMD input) cycle, and the second cycle is an address input (ADDR input) cycle. Both constitute the cycle pattern of the R/B command.

When the enable signal CE# of the NAND flash memory chip enables the chip, in the operation mode of command input, the NAND flash memory chip is received and sent by the NAND flash memory controller (main controller) 200 The prepare command (prepare command). The preparation command can also be defined by a vendor-specific command, such as the command FEh shown in FIG. 6B. This preparation command mainly informs or hints that each NAND flash memory die 100_0~100_m-1 is ready to assign a corresponding DQ port to transmit R/B status.

Then, in the second cycle of the address input cycle, that is, in the address input operation mode shown in FIG. 6B, the NAND flash memory controller 200 will send a specific address value, which will correspond to one The specific DQ port corresponds to the R/B signal line of a NAND flash memory die. For example, at this stage, the value 00h corresponds to DQ0, the value 01h corresponds to DQ1, etc., and the rest can be deduced by analogy.

Therefore, in this embodiment, in the first cycle of the setting phase, the NAND flash memory controller 200 may first send, for example, a command FEh to notify each NAND flash memory die 100_0~100m-1, and their respective The R/B signal line is prepared to establish a corresponding relationship with each port DQ0~DQ7 of the data bus DQ, that is, to assign each port DQ0~DQ7 to the R/B of each NAND flash memory die 100_0~100m-1 Signal line. Then, in the second cycle of address input, by assigning addresses, the R/B signal status of each NAND flash memory die 100_0~100m-1 can be actually associated with each port DQ0~DQ7. In this way, through the two-cycle setting phase, the manufacturer-specific commands and addresses can also be used to map each port DQ0~DQ7 with the internal R/B signal of each NAND flash memory die one-to-one, and store it in The above-mentioned mapping status register 106 shown in FIG. 3B to FIG. 3E.

The schematic diagram of the operation flow of this setting stage at the main controller level is shown in Fig. 7B. In the setting stage, sending a setting command from the main controller may further include: in step S102, in the command input operation mode, sending a preparation command (such as the above command FEh) on the data bus DQ to notify each flash memory The die 100_0~100_m-1 is ready to assign each port DQ0~DQ7 of the data bus DQ to the R/B signal line (status indicator) of each flash memory die 100_0~100_m-1. Then, in step S104, in the operation mode of address input, the main controller sends an address signal ADDR (such as 00h, 01h, etc.) on the data bus DQ, thereby connecting the ports DQ0~ of the data bus DQ DQ7 corresponds to the R/B status signal line (status index) of each flash memory die 100_0~100_m-1 respectively.

FIG. 8 shows the operation sequence of the flash memory controller according to the embodiment of the present invention Schematic. First, when the flash memory starts to operate, data input and output have not been performed on the data bus DQ, that is, when the flash memory is in an idle state, you can set it as shown in Figure 6A or Figure 6B. The operation of the stage is to perform the R/B command operation of setting flash memory die 0~flash memory die 3. Then, the ports DQ0~DQ3 of the data bus DQ are respectively assigned as the R/B signal lines of flash memory die 0~ flash memory die 3. In other words, in the stage of setting the flash memory die, die 0 is set to the R/B state for the DQ0 output master, and the remaining DQ ports are in the high impedance state. Die 1 is set to the R/B state for the DQ1 output master controller, and the remaining DQ high-impedance states. The rest of the die settings can be deduced by analogy.

In addition, when the controller (master controller) sets one of the flash memory dies 0~3 in the setting stage, for example, if DQ0 is selected as the R/B state for the output master, the other flash memory The DQ0 of the die 1~3 corresponding to the DQ0, that is, the respective DQ0 of the flash memory die 1~3 will output a high impedance state. In the same way, make the same settings for other flash memory dies 1~3.

Thereby, the status of the R/B signal lines of each subsequent flash memory die 0~flash memory die 3 can be respectively transmitted from DQ0~DQ3 of the data bus DQ to the flash memory controller 200. At this time, the state of the internal R/B signal lines of each flash memory die 0~3 is in a ready state.

Then, the flash memory die enters the operation mode, that is, various operations such as writing to each flash memory die can be performed. At this time, the state of the internal R/B signal of each flash memory die 0~3 enters the busy state in sequence.

Then after a period of time, the flash memory controller Body die 0~3 send request RB command. When each flash memory die 0~3 receives this request RB command, it then sends the status of R/B signal to the flash memory controller through their corresponding ports DQ0~DQ3. In this way, the flash memory controller can obtain the R/B state of each flash memory die 0~3 during the period from RB to DQ in FIG. 6.

In the request phase, the main controller will issue a request command to all flash memory dies 0-3 at the same time, and each flash memory die 0-3 will be demultiplexed according to the configuration of the setting stage. The 8 outputs of the converter 130 are mapped to DQ[7:0], and finally assembled on a DQ data bus. In this way, the results of X1h, X3h,... can be output on the DQ bus as shown in Figure 8. Because the host controller will assign each flash memory die 0-3 to the corresponding port when setting it, so that multiple ports are not allowed to output at the same time to avoid inter-signal interference. In other words, two flash memory dies will not output to the same port at the same time. For example, taking the channel 0 shown in Figure 3A as an example, when the status is output, flash memory die 0 will output zzzz_zzz1 in its DQ[7:0], and flash memory die 1 will be in its DQ[7 :0] output zzzz_zz0z, flash memory die 2 will output zzzz_z0zz in its DQ[7:0], flash memory die 3 will output zzzz_0zzz in its DQ[7:0] (where z means high impedance state ). Finally, the master DQ bus will output zzzz_0001 to indicate the status of each flash memory die 0-3.

Therefore, under the structure of this embodiment, the R/B signal line of the flash memory die is replaced by the manufacturer-specific command and the data bus is used, so the original R/B signal line of each flash memory die can be saved. The signal line and the pad, so the flash memory controller does not need this R/B pad correspondingly, so the number of pads of the controller can be effectively reduced without increasing the flash memory die Size and circuit complexity. also, The operation mode of this embodiment is performed by using the existing data input and output operation mode, that is, the idle period of the data bus is used to set the R/B signal and DQ port, so no additional operation is required, and it can also be used. Easily achieve the assignment of R/B signal and DQ port and output the mapping status value to the data bus DQ (external data bus) at the same time, which can reduce the need to poll each flash memory die state in turn frequency. .

100_0~100_m-1: NAND flash memory die

102: Logic Control Unit

104: Input and output unit

106a: Mapping status register

106b: State selection register

108: R/B signal status (internal)

110: high voltage circuit

112: Command register

114: Address register

116: Status register

118: data buffer

120: memory array

122: Y-decoder

124: X-decoder

126: page buffer

Claims (26)

A method for controlling a flash memory, wherein the flash memory has an external data bus connected to a plurality of flash memory dies, and the control method includes: In the setting phase, in the command input operation mode, the main controller sends a setting command to map each port of the external data bus to the state indicator of each flash memory die; and In the request phase, in the operation mode of command input, the main controller sends a request command to each of the plurality of flash memory dies, and in the operation mode of data output, each of the flash memories The state of the state indicator of the bulk die is transmitted to the main controller through each port of the corresponding external data bus. The method for controlling flash memory according to claim 1, wherein in the setting phase, sending the setting command by the main controller further includes: In the operation mode of command input, the main controller sends a preparation command to notify each of the plurality of flash memory dies to prepare to assign each port of the external data bus to each of the plurality of flash memory dies. The state indicator of the flash memory die; and In the operation mode of address input, the main controller sends out an address signal, thereby mapping each port of the external data bus to the state indicator of each of the plurality of flash memory dies. The flash memory control method according to claim 1, wherein each flash memory die has a plurality of output ports respectively coupled to each port of the external data bus, and in the setting stage, the The first output port of one of the first flash memory dies of one of the plurality of flash memory dies is selected to transmit the status indicator, Wherein the output port corresponding to the first output port of each flash memory die other than the first flash memory die in the plurality of flash memory die is in an output high impedance state, Output ports other than the first output port of the first flash memory output a high impedance state. The method for controlling a flash memory according to claim 1, wherein the state indicator is ready/busy for the master controller The flash memory control method according to claim 1, wherein the setting command and the request command are defined by manufacturer-specific commands. The method for controlling a flash memory according to claim 1, wherein the main controller is a flash memory controller. A flash memory die, including at least: A plurality of output ports, the plurality of output ports are coupled to an external data bus; A control logic unit, which provides a state indicator of the flash memory die; A mapping state register for storing data, the data being used for selecting one of the plurality of output ports corresponding to the state indicator of the flash memory die; and Input/output control unit, The input/output control unit further includes: The first multiplexer has multiple inputs and outputs, the multiple inputs respectively receive data from multiple sets of internal buses, and the output is coupled to the multiple output ports, wherein the first multiplexer According to the selection signal provided by the control logic unit, one of the multiple inputs is selected and output to the external data bus. The multiple sets of internal buses include at least an internal data bus, a status indicator bus, and a mapping state Busbar; and The demultiplexer has an input, a plurality of outputs, and a selection line, wherein the input receives the state indicator, the selection line receives the data stored in the mapping state register, and the demultiplexer The output of the demultiplexer is connected to the input of the first multiplexer via the mapping state bus, wherein the demultiplexer selects the multiplexer of the demultiplexer based on the data received by the selection line. One of the two outputs is used to transmit the state indicator, and the unselected output of the demultiplexer is output with high impedance. The flash memory die according to claim 7, wherein when the flash memory die receives a setting command sent by the main controller, the state indicator of the flash memory die is mapped to One of the multiple output ports. The flash memory die according to claim 8, wherein when the flash memory die receives a request command from the main controller, the demultiplexer of the input/output control unit is based on the The data stored in the mapping status register is selected, the output port corresponding to the status indicator of the flash memory die is selected, and the status of the status indicator is passed through the selected output port Transfer to the main controller. The flash memory die according to claim 9, wherein when the request command is received, the unselected one of the plurality of output ports is in a high impedance state. The flash memory die according to claim 9, wherein the setting command and the required command are defined by manufacturer-specific commands. The flash memory die according to claim 8, wherein the main controller is a flash memory controller. The flash memory die according to claim 7, wherein the status indicator is a ready/busy status for the master. The flash memory die according to claim 7, wherein the input/output control unit further includes: The second multiplexer, the output of the second multiplexer is coupled to the input of the demultiplexer, and is used to select one from a plurality of state registers and output to the demultiplexer. The flash memory die according to claim 7, wherein the input/output control unit further includes: a multiplexer unit coupled to the demultiplexer, wherein the multiplexer unit includes a plurality of Multiplexer, Each of the plurality of multiplexers receives a plurality of state registers, and selects one from the plurality of state registers to output to the demultiplexer, The outputs of the multiple multiplexers are provided to the demultiplexer and input to the first multiplexer via the mapping state bus. A method for controlling a flash memory, wherein the flash memory has an external data bus connected to a plurality of flash memory dies, and the control method includes: The main controller sends a setting command to correspond each port of the external data bus with the state indicator of each flash memory die; and The main controller sends a request command to each of the flash memory dies; When each of the plurality of flash memory dies receives the request command, the state of the state indicator of each of the plurality of flash memory dies is passed through each of the corresponding external data bus Port, sent to the host controller. The method for controlling a flash memory according to claim 16, wherein the setting command sent by the main controller further includes: Sending a preparation command to notify each of the plurality of flash memory dies to prepare to assign each port of the external data bus to each of the plurality of flash memory dies; and An address signal is sent to thereby correspond each port of the external data bus of each of the plurality of flash memory dies to the state indicators of each of the plurality of flash memory dies. The method for controlling a flash memory according to claim 16, wherein each of the flash memory dies has a plurality of output ports respectively coupled to each port of the external data bus, and the plurality of flashes The first output port of one of the first flash memory dies of one of the memory dies is selected to transmit the status indicator, Wherein the output port corresponding to the first output port of each flash memory die other than the first flash memory die in the plurality of flash memory die is in the output high impedance state, Output ports other than the first output port of the first flash memory output a high impedance state. The method for controlling the flash memory according to claim 16, wherein the status indicator is a ready/busy status for the master controller. The method for controlling the flash memory according to claim 16, wherein the setting command and the request command are defined by manufacturer-specific commands. The method for controlling a flash memory according to claim 16, wherein the main controller is a flash memory controller. A type of flash memory, including: At least one external data bus with multiple ports; A plurality of flash memory dies are respectively coupled to the at least one external bus; and The main controller is coupled to the at least one external bus for controlling the plurality of flash memory dies, In the setting phase, the main controller sends a setting command to correspond each port of the external data bus with the state indicator of each flash memory die, In the request stage, the main controller sends a request command to each of the flash memory dies, and receives the request command in each of the plurality of flash memory dies, and sends each of the plurality of flash memory dies. The state of the state indicator of the flash memory die is transmitted to the main controller through each port of the corresponding external data bus. The flash memory according to claim 22, wherein the setting command sent by the main controller further includes: Sending a preparation command to notify each of the plurality of flash memory dies to prepare to assign each port of the external data bus to each of the plurality of flash memory dies; and An address signal is sent to thereby correspond each port of the external data bus of each of the plurality of flash memory dies to the state indicators of each of the plurality of flash memory dies. The flash memory according to claim 22, wherein each of the flash memory dies has a plurality of output ports respectively coupled to each port of the external data bus, and the plurality of flash memory dies The first output port of one of the first flash memory die is selected to transmit the status indicator, Wherein the output port corresponding to the first output port of each flash memory die other than the first flash memory die in the plurality of flash memory die is in the output high impedance state, Output ports other than the first output port of the first flash memory output a high impedance state. The flash memory according to claim 22, wherein the status indicator is a ready/busy status for the master. The flash memory according to claim 22, wherein the setting command and the request command are defined by manufacturer-specific commands.

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