TW202226250A - Control method for flash memory, flash memory die and flash memory - Google Patents

Abstract

A control method for flash memory is provided. The control method comprises: in a setup stage, under an operation mode of command input, issuing by a host a setup command to map each port of an external data bus of each flash memory die respectively to a status index of each flash memory die; and in a request stage, under the operation mode of command input, issuing by the host a request command to each flash memory dies, and under the operation mode of data output, transmits status of the status index of each flash memory die to the host through the ports of the external data bus respectively.

Description

Flash memory control method, flash memory die, and flash memory

The present invention relates to a flash memory, and more particularly, to a control method of the flash memory and a flash memory die thereof.

Currently, NAND flash memory controllers face a large increase in the number of NAND flash memory dies to be controlled, which results in an increase in the number of controller pads and an increase in die size. Also, the ready/busy (R/B) signals of all logic units are also connected to the shared R/B signal line. Therefore, if you want to know which logic unit is busy when the shared R/B signal line is busy, you need to issue a "read status command" to inquire whether the specified logic unit is ready or busy.

In general, the R/B state of NAND flash memory is implemented using an open drain design. FIG. 1 is a schematic circuit diagram of an open drain of a NAND flash memory. As shown in Figure 1, there are multiple NAND flash memory dies 0, 1, 2, . . . in a channel and their R/B state outputs are respectively connected to a common open-drain output. 2A and 2B illustrate that there are currently two design methods for multi-channel NAND flash memory.

As shown in FIG. 2A, in this structure, the R/B signal lines of each NAND flash die in each channel are independent, that is, each flash die 10_0~ Each of 10_m-1 is provided with an R/B signal line to connect with the multi-channel flash memory controller 20. Therefore, in each channel, the multi-channel flash memory controller 20 is also set to be connected to the R/B signal line. The corresponding number of pads.

FIG. 2B illustrates a multi-channel NAND flash memory of another architecture. As shown in FIG. 2B , in this design, each flash memory die 10_0 to 10_m-1 in each channel shares one R/B Signal lines, that is, shorted together. However, under this architecture, the multi-channel flash memory controller 20 will not be able to know which NAND flash memory die 10_0~10_m-1 is in a busy state, and additional time must be spent to confirm each flash memory Ready/busy status of bulk die 10_0~10_m-1. In other words, in this structure, although the number of pads can be saved, additional time is required to confirm the ready/busy status of each of the flash memory chips 10_0 to 10_m-1.

Therefore, there is a need in the technical field for a technical means, which can reduce the number of pads on the one hand, and on the other hand, does not require extra time to confirm whether each flash memory is in a busy state.

According to an embodiment, the present invention provides a control method of a flash memory, wherein the flash memory has an external data bus connecting a plurality of flash memory dies. The control method includes: in the setting stage, in the operation mode of command input, a setting command is sent from the host controller, and each port of the external data bus is respectively mapped to the state index of each of the flash memory chips; and in the request stage, in the operation mode of command input, the host controller sends a request command to each of the plurality of flash memory chips, and in the operation mode of data output, each of the flash The state of the state indicator of the memory die is transmitted to the host controller through the corresponding ports of the external data bus.

In the above control method of multi-channel flash memory, in the setting stage, sending a setting command from the master controller further comprises: in the operation mode of command input, the master controller sends a ready command to notify each of the plurality of The flash memory die is ready to perform the state indicator of assigning each port of the external data bus to each of the plurality of flash memory die; and in the address input mode of operation, the The host controller sends out an address signal, thereby mapping each port of the external data bus to the status indicators of each of the plurality of flash memory chips.

In the above control method of a flash memory, each of the flash memory chips has a plurality of output ports respectively coupled to the ports of the external data bus; in the setting stage, the plurality of flash memory A first output port of one of the first flash memory dies of one of the flash memory dies is selected to transmit the status indicator. Wherein, the output port corresponding to the first output port of each flash memory die other than the first flash memory die among the plurality of flash memory die is in an output high impedance state ; Output ports other than the first output port of the first flash memory output a high impedance state.

In the above control method of the flash memory, the state indicator can be a ready/busy state for the master. In the above control method of a flash memory, the setting command and the request command may be defined by manufacturer-specific commands. In the above method for controlling a flash memory, the main controller may be a multi-channel flash memory controller. According to another embodiment, the present invention provides a flash memory chip, which at least includes: a plurality of ports coupled to an external data bus; a control logic unit for providing the flash memory a state index of a die; a map state register for storing data used to select one of the plurality of ports corresponding to the state index of the flash memory die; and an input /output control unit. The input/output control unit further includes a first multiplexer and a demultiplexer. A first multiplexer has a plurality of inputs and outputs, the plurality of inputs respectively receive data from a plurality of sets of internal busbars, the outputs are coupled to the plurality of ports, wherein the first multiplexer is based on The selection signal provided by the control logic unit selects one of the multiple inputs and outputs it to the external data bus, and the multiple groups of internal bus at least include an internal data bus, a state indicator bus and a mapping state bus Row. A demultiplexer has an input, a plurality of outputs and select lines, wherein the input receives the state indicator, the select line receives the data stored from the map state register, the demultiplexer The output of the demultiplexer is connected via the map state bus to the input of the first multiplexer, wherein the demultiplexer selects one of the multiple outputs of the demultiplexer based on the data received by the select line Once the state indicator is communicated, the unselected outputs of the demultiplexer are output at high impedance.

In the above-mentioned flash memory die, when the flash memory die receives a setting command sent by a host controller, the state indicators of the flash memory die are mapped to the plurality of ports one.

In the above-mentioned flash memory die, when the flash memory die receives a request command from the host controller, the demultiplexer of the input/output control unit temporarily stores according to the mapping state selecting the port corresponding to the state indicator of the flash memory chip according to the data stored in the device, and transmitting the state of the state indicator to the host controller via the selected port.

In the above-mentioned flash memory die, when the request command is received, the unselected one of the plurality of ports is in a high impedance state.

In the above flash memory die, the set command and the request command may be defined by vendor specific commands. In the above flash memory die, the main controller may be a multi-channel flash memory controller. In the above flash memory die, the status indicator is ready/busy for the master.

In the above-mentioned flash memory die, the input/output control unit further includes a second multiplexer, the output of the second multiplexer is coupled to the input of the demultiplexer, and is used for switching from a plurality of states The register selects one output to the demultiplexer.

In the above flash memory die, the input/output control unit further includes: a multiplexer unit coupled to the demultiplexer, wherein the multiplexer unit includes a plurality of multiplexers. Each of the plurality of multiplexers receives states stored in a plurality of state registers, and outputs one selected from the plurality of state registers to the demultiplexer. The outputs of the multiplexers are provided to the demultiplexer and input to the first multiplexer via the map state bus.

According to another embodiment, the present invention provides a control method of a flash memory, wherein the flash memory has an external data bus connecting a plurality of flash memory dies. The control method includes: sending a setting command from a main controller to correspond each port of an external data bus with a state index of each of the flash memory chips; and sending from the main controller to each of the The flash memory die sends a request command; when each of the plurality of flash memory die receives the request command, the state of the state index of each of the plurality of flash memory die is passed through the phase The corresponding ports of the external data bus are sent to the host controller.

In the above method for controlling a flash memory, sending a setting command from the host controller further comprises: sending a prepare command to notify each of the plurality of flash memory chips to prepare for each port of the external data bus. respectively assigning each of the plurality of flash memory chips; and sending out address signals, thereby connecting the ports of the external data bus of each of the plurality of flash memory chips to each of the plurality of flash memory chips The state indicators of each flash memory die correspond respectively.

In the above-mentioned control method of a flash memory, each of the flash memory chips has a plurality of output ports respectively coupled to the ports of the external data bus; among the plurality of flash memory chips One of the first output ports of one of the first flash memory dies is selected to transmit the status indicator. Wherein, the output port corresponding to the first output port of each flash memory die other than the first flash memory die among the plurality of flash memory die is in an output high impedance state ; Output ports other than the first output port of the first flash memory output a high impedance state.

In the above control method of the flash memory, the state indicator can be a ready/busy state for the master. In the above control method of a flash memory, the setting command and the request command may be defined by manufacturer-specific commands. In the above method for controlling a flash memory, the main controller may be a flash memory controller.

According to another embodiment, the present invention provides a flash memory, comprising: at least one external data bus with multiple ports; a plurality of flash memory chips coupled to the at least one external bus, respectively; and a main controller, coupled to the at least one external bus, for controlling the plurality of flash memory chips. Wherein, in the setting stage, the host controller sends a setting command to correspond each port of the external data bus with the status indicators of the flash memory chips respectively; in the request stage, the host The controller sends a request command to each of the flash memory dies, and receives the request command in each of the plurality of flash memory dies, and sends all of the plurality of flash memory dies to the request command. The state of the state indicator is transmitted to the host controller through the corresponding ports of the external data bus.

In the above-mentioned flash memory, sending the setting command by the host controller further comprises: sending a prepare command to notify each of the plurality of flash memory chips to prepare for assigning the ports of the external data bus to the respective ports of the external data bus. each of the plurality of flash memory dies; and sending an address signal, thereby connecting each port of the external data bus of each of the plurality of flash memory dies with each of the plurality of flashes The state indicators of the memory die correspond respectively.

In the above control method of a flash memory, in the above control method of a flash memory, each of the flash memory chips has a plurality of output ports respectively coupled to the ports of the external data bus; A first output port of one of a first flash memory die of one of the plurality of flash memory dies is selected to transmit the status indicator. Wherein, the output port corresponding to the first output port of each flash memory die other than the first flash memory die among the plurality of flash memory die is in an output high impedance state ; Output ports other than the first output port of the first flash memory output a high impedance state.

In the above flash memory, the status indicator can be used as a ready/busy status for the master. In the above control method of a flash memory, the setting command and the request command may be defined by manufacturer-specific commands.

To sum up, under the structure of the present embodiment, the manufacturer-specific command and the data bus are used as the R/B signal lines of the flash memory chips, so the original flash memory chips can be saved. Therefore, the flash memory controller does not need this R/B pad correspondingly, and the number of the controller pads can be effectively reduced.

FIG. 3A is a schematic diagram illustrating a structure of a flash memory according to an embodiment of the present invention. FIG. 3B is a schematic structural diagram of a NAND flash memory die according to an embodiment of the present invention, that is, a schematic structural diagram of each NAND flash memory die in each channel in FIG. 3A . Although FIG. 3A shows the structure of a multi-channel flash memory, the description of this embodiment will take one of the channels as an object of description. Both the method and the architecture of this embodiment are applicable to single-channel or multi-channel situations.

As shown in FIG. 3A , the NAND flash memory controller 200 or host 200 can be connected to n channels (0˜n−1) of flash memory strings, and each channel of flash memory Each string may contain multiple flash memory dies. For example, each of the NAND flash memory channels 0 to n-1 has m NAND flash memory dies 100_0 to 100_m-1. In addition, the m NAND flash memory chips 100_0 to 100_m-1 of each channel have at least chip enable signals CE_0 to CE_m-1, which are respectively connected to the NAND flash memory controller 200 . In addition, the input and input control units of each of the NAND flash memory dies 100_0 to 100_m-1 can transmit and receive data with the NAND flash memory controller 200 through the data bus (external data bus) DQ.

Furthermore, as shown in FIG. 3A, in this structure, each NAND flash memory die 100_0~100_m-1 does not use the R/B pads in the prior art to communicate with each NAND flash memory. The corresponding ready and busy states (status indicator signals) of the bulk dies 100_0~100_m-1 are transmitted. According to the embodiment of the present invention, each port of the data bus DQ (take 8 ports as an example, such as DQ[7:0]) is used for each NAND flash memory die 100_0~100_m- 1 for the transmission of R/B signals. In other words, in this embodiment, the R/B state detection of the NAND flash memory chips 100_0 to 100_m-1 is performed by mapping the internal R/B # port to the designated DQ port.

The status indicators here can be various internal states and parameters of the flash memory of each channel, such as the ready/busy status for the master (R/B# for host), the ready/busy status for the flash array (R/ B# for flash array) etc. In this embodiment, the ready/busy state (R/B# for host) for the host is used as an example of the description of the state indicator. In this way, the present embodiment does not use external R/B pads and signal lines, so the number of pads of the controller can be reduced. The detailed operation method will be described in detail later. The ready/busy state used by the master refers to whether the data buffer in the flash memory die (such as the data buffer 118 in FIG. 3B ) is empty, indicating whether the next data from the master can be received. , but the data has not been written to the memory array. The flash array uses the ready/busy state to indicate whether data is actually written to the memory array.

FIG. 3B is a schematic structural diagram of a NAND flash memory die according to an embodiment of the present invention. As shown in FIG. 3B , the structure of the NAND flash memory die 100_0 (the structures of the NAND flash memory die 100_1 to 100_m-1 are all the same) is basically the same as that of the general NAND flash memory die, and the difference lies in Add a circuit block that maps R/B signal lines and DQ ports to each other.

As shown in FIG. 3B , the NAND flash memory die 100_0 of this embodiment also has a control logic unit 102 , an input/output control unit 104 , a memory array 120 , an X-decoder 124 , a Y-decoder 122 , a page Basic circuit blocks of buffer 126, high voltage circuit 110, command register 112, address register 114, status register 116, data buffer 118, data bus DQ, etc. The functions and operation modes of the basic circuit blocks of the NAND flash memory die 100_0 are basically the same as or similar to the existing structure, and the actual structure does not affect the implementation of this embodiment, so the detailed description thereof is omitted here.

According to this embodiment, the NAND flash memory die 100_0 has at least a mapping state register 106 , and in this embodiment, R/B is mapped to the DQ port 106 as an illustration example. The mapping state register 106 is used for storing the one-to-one correspondence between the ports DQ0 ˜ DQ7 of the data bus DQ and the internal R/B lines of the flash memory chips 100_0 ˜ 100_m-1 respectively. That is, the mapping state register 106 in the NAND flash memory die 100_0 stores the data used to indicate which DQ port the NAND flash memory die 100_0 uses to output the R/B state for the master. material. For example, if the NAND flash memory die 100_0 is to use DQ0 as the output, the data stored in the mapping state register 106 will record, for example, the value "0", and the other NAND flash memory die 100_1~100_m- 1 and so on. That is, each NAND flash memory die will only store the DQ port to be used in its own mapping state register 106 . In the main controller (flash memory controller 200 ), a correspondence table can be stored, and the correspondence table can record which NAND flash memory each port (DQ[7:0]) in the channel is used to output. The state indicator of the die.

Thereby, when the NAND flash memory controller 200 sends a request signal (request stage which will be described in detail later) to each of the flash memory chips 100_0 to 100_m-1 to obtain the state of the R/B signal, each flash The I/O control units 104 of the memory chips 100_0 to 100_m-1 can send R/B signals at the corresponding DQ ports. In this way, the NAND flash memory controller 200 obtains the R/B signal state of each flash memory die 100_0 to 100_m-1 from each port DQ0 to DQ7 in the data bus DQ at one time.

Through the above structure, the logic control unit 102 does not need to use the internal R/B signal to transmit the R/B state through the R/B pads of the I/O control unit 104, so no external R/B signal line and connection are required. pad. Therefore, the NAND flash memory controller 200 does not need to set corresponding R/B pads, so the number of pads can be reduced. As shown by the dotted line in the lower left corner of FIG. 3B , this embodiment can completely omit the hardware structure of this part.

3C and 3D further illustrate a schematic diagram of the circuit structure of the I/O control unit 104 in the NAND flash memory die shown in FIG. 3B. The NAND flash memory chips shown in FIG. 3C and FIG. 3D only depict circuit blocks related to this embodiment, and the rest are omitted. As shown in FIG. 3C, the I/O control unit 104 may further include a multiplexer 131 (first multiplexer), which may have multiple sets of internal busbars as inputs. Each group of bus bars is composed of, for example, 8 signal lines. Through these internal busbars, the multiplexer 131 can select one of the multiple sets of inputs according to the selection signal line of the logic control unit 102, that is, select the internal data busbar (general data transfer), status busbar (flash memory) status indicator) or map one of the status busses (such as RB to DQ port) to output to port (DQ[7:0]) output. The DQ bus can output various output signals, such as data, the status of the flash memory, or the RB status in this embodiment (ie, RB to DQ port). In this embodiment, the state indicator is to use the R/B state for the master. In addition, the mapping state register 106 stores data used to indicate which port is to be used as the output R/B (state). As shown in Figure 3D, the demultiplexer 130 has an input, multiple outputs and select lines. The output of demultiplexer 130 and one of the inputs of multiplexer 131 can be connected to the map state bus ([7:0]). The input of the demultiplexer 130 receives a signal in the R/B state of the master. The select line of the demultiplexer 130 receives the data stored from the map state register 106, and accordingly transfers the master of the flash memory die from the corresponding port (the map state bus ([ 7:0])) output. Accordingly, the multiplexer 131 of FIG. 3C can output the R/B state for the master from the corresponding port.

In addition, FIG. 3E is a schematic diagram of the circuit structure of the demultiplexer 130 in 3D. As shown in FIG. 3E, the demultiplexer 130 may further include a decoder 130a and a plurality of pass gates. In this example, a tri-state gate is used as an example of a gate gate. Tri-state gates 130b_0~130b_7 (8 in this example, corresponding to DQ[7:0] respectively). The output of each tri-state gate 130b_0~130b_7 is connected to its corresponding DQ port DQ[7:0]. The decoder 130a can receive and decode the data from the R/B to DQ port register 106, thereby enabling the master of the input demultiplexer 130 to use the R/B state to pass through the tri-state gate 130b_0 corresponding to the data One of ~130b_7, and output from the corresponding DQ port. For example, if the NAND flash memory die 100_1 uses DQ1 as the output port for the R/B state of the master, the mapping state register 106 will record “1”. For example, when the value stored in the mapping state register 106 is 1, it means that the demultiplexer 130 will convert the value into 0000_0010 through the decoder 130a, and the tri-state gates 130b_0~130b_7 will convert the DQ1 to DQ1 according to the received signal 0000_0010. On, the rest of the ports will be in a high-impedance state. That is, DQ1 outputs R/B (status). At this time, the decoder 130a will enable the tri-state gate 130b_1 accordingly, and the other tri-state gates 130b_0, 130b_2~130b_7 are disabled and become a high-impedance state. Accordingly, port DQ1 will be selected to output the R/B status for the master.

In addition, in this embodiment, each NAND flash memory die selects only one DQ port as the output of the state indicator (in this example, the master uses the R/B state). At this time, the DQ ports that are not selected will be in a high impedance state.

As described above, the state of the internal R/B signal line can be transmitted to the NAND flash memory controller 200 through the data bus DQ through the corresponding DQ port by the method of this embodiment. For example, the R/B signal line of the flash memory die 100_0 is mapped to the DQ port DQ0, the R/B signal of the flash memory die 100_1 is mapped to the DQ port DQ1 and so on.

Therefore, in this way, for the plurality of flash memory dies 100_0 to 100_m-1 of each channel, the NAND flash memory controller 200 can obtain the data from the ports DQ0 to DQ7 on the data bus DQ at one time. The R/B states of the flash memory die 100_0~100_m-1. Therefore, the NAND flash memory controller 200 does not need external R/B signal lines and pads, thereby effectively reducing the number of pads in the controller.

FIG. 4A is a schematic diagram of the structure of another NAND flash memory die of this implementation, and FIG. 4B is a schematic diagram of the circuit structure of the I/O controller unit in FIG. 4A . As shown in FIG. 4A, in addition to the mapping state register 106a, the I/O controller unit 104 also includes a state selection register 106b. The data stored in the mapping state register 106a can indicate which of the multiple DQ ports of the NAND flash memory die 100_0 (...100_m-1) is to be used as the output of the state indicator, and the state selection register 106b The stored data may indicate which of a plurality of status indicators of the NAND flash memory die 100_0 (...100_m-1) is to be output.

In the descriptions of FIGS. 3B to 3E , a single state indicator is used as an example, that is, the R/B state used by the master is used as an illustration. However, as mentioned above, the application of the present invention is not limited to the R/B state for the master controller, but may also be other state indicators or parameters of the NAND flash memory die 100_0 (...100_m-1). In other words, in this embodiment, one state indicator can be selected from a plurality of state indicators of each flash memory die 100_0 (...100_m-1) to be output from the corresponding DQ port.

As shown in FIG. 4B , in the architecture of this embodiment, in addition to the demultiplexer 130 , a multiplexer 132 (a second multiplexer) is further included. In addition, the control logic unit 102 may further include a plurality of state registers, and may optionally output one to the demultiplexer 132 . The multiplexer 132 can receive states stored in a plurality of state registers, such as the R/B state for the master, the R/B state for the flash array, and other states. In addition, the multiplexer 132 is further coupled to the state selection register 106b. The multiplexer 132 may select one output from a plurality of state registers, such as the R/B state for the master, the R/B state for the flash array, and other states, based on the data from the state selection register 106b. Therefore, the demultiplexer 130 can output the state selected by the state selection register 106b from the corresponding port according to the data stored in the mapping state register 106a.

As shown in FIG. 4B , the multiplexer 132 is coupled to the demultiplexer 130 . The state indicator selected by the multiplexer 132 is then input to the demultiplexer 130 . The operation of the demultiplexer 130 is the same as that described in FIGS. 3D and 3E . That is, the demultiplexer 130 may receive and decode data from the map state register 106a, whereby the state indicator selected by the multiplexer 132 may pass through the data stored in the map state register 106a specified by the data The corresponding DQ port (selected by the multiplexer 131 of FIG. 3C ) is output. Therefore, the multiplexer 132 can select one state indicator from the plurality of state indicators to use the data bus DQ to transmit the state.

That is, as shown in FIG. 4B, the multiplexer 132 selects the signal of the register 106b as the select line according to the state, and selects from a plurality of states such as the R/B state for the master and the R/B state for the flash array, etc. one of them as output. For example, the multiplexer 132 selects the output state according to the state selector 106b to be the R/B state for the flash array. At this time, the demultiplexer 130 will receive the signal output by the multiplexer 132 (ie, the R/B state for the flash array), and decode the data according to the mapping state register 106a to obtain the port selected for the output this time. for the 6th root. In this example, in the output result of the eight ports of the demultiplexer 130, ports 0-5 and port 7 are all high impedance, and port 6 is used to output the R/B state for the flash array.

Then, according to the selection line of the control logic unit 102, the multiplexer 131 (refer to FIG. 3C) will output the eight ports of the demultiplexer 130 (the port 6 is the R/B state for outputting the flash array, and the rest are high impedance) as one of the set of choices for the multiplexer 131 select outputs. It is assumed that when the master side issues the request command in this embodiment, the group of ports output by the eight ports of the demultiplexer 130 will be selected as DQ[7:0] for output.

According to this variation, the DQ port of the data bus DQ is not limited to be mapped to only a single state indicator, but can be dynamically selected by the master, that is, the NAND flash memory controller 200 to select the required state indicator from the The data bus DQ transmits the status signal, so the control of the NAND flash memory die can be operated in a more free manner. Except for the first multiplexer 132 and the state selection register 106b, the operation of the demultiplexer 130 is the same as that shown in FIG. 3D to FIG. 3E, so the description is omitted here.

FIG. 5 is a schematic diagram of a circuit structure of an I/O control unit in a flash memory die according to another embodiment. The difference between the embodiment shown in FIG. 5 and FIG. 4B lies in the circuit structure of the demultiplexer and the multiplexer. As shown in FIG. 5 , the demultiplexer 130 ′ includes, for example, a decoder 130 ′a and a plurality of tri-state gates 130 ′b_0 to 130 ′b_7 (8 for example), and the decoder 130 ′a is further coupled to each Tri-state gates 130'b_0~130'b_7. The multiplexer unit 132' further includes a decoder 132'a and a plurality of multiplexers 132'b_0 to 132'b_7 (8 for example), and the decoder 132'a is further coupled to each multiplexer 132'b_0 ~132'b_7. Each multiplexer 132'b_0~132'b_7 of the multiplexer unit 132' is respectively coupled to the tri-state gates 130'b_0~130'b_7 of the demultiplexer 130'. In addition, each of the multiplexers 132'b_0~132'b_7 receives states stored in a plurality of state registers, such as the R/B state for the master, the R/B state for the flash array, and other states.

The decoder 132'a of the multiplexer unit 132' receives and decodes the data from the state selection register 106b, thereby enabling each of the multiplexers 132'b_0~132'b_7 to select one of the state registers. For example, the multiplexer 132'b_0 can select and output to the corresponding tri-state gate 130'b_0 from a plurality of state registers, such as the R/B state for the main controller, the R/B state for the flash array, and other states. The multiplexer 132'b_1 can select one of a plurality of state indicators, such as the R/B state for the master, the R/B state for the flash array, and other states, and output them to the corresponding tri-state gate 130'b_1, and so on. In addition, the decoder 130'a of the demultiplexer 130' can receive and decode the data from the mapping state register 106a, thereby enabling the corresponding tri-state gates 130'b_0~130'b_7, and each state indicator It can be output from the corresponding DQ port [7:0].

For example, the demultiplexer 130' selects which ports are to be output states and the remaining ports are high impedance. For example, if the decoding result of the decoder 130'a is 0000_1100, it means that the ports 2 and 3 are output as statuses, and the other ports are in a high-impedance state. In addition, the state selection register 106b stores the state to be output by each port. The multiplexer (second multiplexer) 132' determines which state each of the eight ports is to select as an output. For example, if the decoded result of the decoder 132'a is 1111_1211, assuming that 1 represents the R/B state used by the master, and 2 represents the R/B state used by the flash array, then the port 2 of the eight ports of the multiplexer 132' The R/B status for the array is output for flash, while the remaining ports are used as output for the R/B status for the master (ie, ports 0, 1, 3-7). In addition, the eight output ports of the demultiplexer 130 finally obtained by the multiplexer 131 (refer to FIG. 3C ) are: port 2 is in the R/B state for the flash array, port 3 is in the R/B state for the master controller, and the rest The 6 ports are all high impedance.

In this embodiment, compared to the embodiment shown in FIG. 3E , a flash memory chip only designates one DQ port to output the status indicator, a flash memory chip may designate a plurality of DQ ports, each DQ ports can represent a status indicator. Therefore, for a flash memory chip, multiple status indicators can be output simultaneously through the data bus DQ. In this embodiment, the flash memory chip will have multiple status indicators to be output. At this time, which DQ port is to output which status indicator, the corresponding relationship will be stored in the status selection temporary storage in a data format. in the device 106b.

Next, the actual operation of the above circuit structure will be described, and with reference to FIG. 6A to FIG. 6C , how to map each port of the data bus DQ to the R/B signal line in the embodiment of the present invention will be described in detail. Here, FIGS. 6A to 6C are diagrams illustrating the operation timing of one flash memory die after receiving a command from the host controller.

6A is a schematic diagram illustrating an operation flow sequence diagram of each flash memory die in the control method of the NAND flash memory according to the embodiment of the present invention, which is an explanatory diagram of the operation sequence of the flash memory die level. As shown in FIG. 6A , the control method of the present embodiment utilizes that the operation mode of the data bus DQ is divided into two stages, that is, a setup stage and a request stage. This embodiment mainly utilizes the time period when the data bus DQ is in the idle state. In this example, the data bus DQ has 8 ports DQ0~DQ7 as an illustration, but the actual situation can be adjusted appropriately according to the NAND flash memory chips. In addition, the operation of the master level will be illustrated in FIG. 7A.

As shown in FIG. 6A , in the setting stage, in the operation mode of the command input (CMD input) (based on the data transfer specification of the data bus DQ), the cycle pattern at this time is to set the R/B command. That is, after each NAND flash memory die 100_0 (...100_m-1) receives the setup command sent by the NAND flash memory controller 200, that is, the host 200, Each port DQ0 to DQ7 of the data bus DQ is corresponding to the R/B state (state index) of each flash memory die 100_0 to 100_m-1 in a channel of the flash memory.

Here, the setting command may use a vendor-specific command to correspond to each port DQ0 to DQ7 of the data bus DQ of each NAND flash memory die 100_0 to 100_m-1 of each channel. For example, a general NAND flash memory die 100_0~100_m-1 can have 8 different manufacturer-specific commands, and each manufacturer-specific command can correspond to a specific DQ port. For example, command 20h can be assigned to port DQ0, command 21h can be assigned to port DQ1, etc., and so on. In this way, different vendor-specific commands can be used to assign corresponding ports. That is, as shown in FIG. 6A , in the periodic mode of setting the R/B command, the internal chip enable signal CE# enables the chip, and sends the command 20h on DQ[7:0] of the data bus DQ.

In this way, through the setting stage, each port DQ0~DQ7 can be mapped one-to-one with the internal R/B signal lines of each NAND flash memory die by manufacturer-specific commands, and the data used to indicate the corresponding relationship (value) is stored in the R/B to DQ port registers 106 shown in FIGS. 3B to 3E above.

At the level of the main controller, in the setting stage, the schematic diagram of the operation flow is shown in step S100 of FIG. 7A . In the operation mode of command input, the main controller (such as a flash memory controller) sends a setting command to The ports DQ0 ˜ DQ7 of the data busses of each of the plurality of flash memory dies 100_0 ˜ 100_m-1 are respectively mapped to the status indicators (R/B state).

Referring again to FIG. 6A, then in the request stage, each NAND flash memory die 100_0 (...100_m-1) receives a request command sent by the NAND flash memory controller 200, That is, another manufacturer-specific command is transmitted to each NAND flash memory die 100_0 to 100_m-1.

In this request stage, as shown in FIG. 6A , when the operation mode is command input, the cycle pattern at this time is the request R/B command, that is, the NAND flash memory controller 200 responds to each NAND flash memory die. 100_0~100_m-1 send a request command to obtain the state of the R/B signal line of each NAND flash memory die 100_0~100_m-1. Next, in the data output operation mode, each NAND flash memory die 100_0~100_m-1 will use the corresponding ports DQ0~DQ7 to connect each NAND flash memory die via the data bus DQ. The master controller R/B status of the particles 100_0 to 100_m-1 transmits the NAND flash memory controller 200.

For the master controller level, in the request stage, the schematic diagram of the operation flow is shown in step S200 of FIG. 7A , in the operation mode of command input, the master controller sends each of the flash memory chips 100_0 to 100_m-1 Send a request command. Next, in step S300, in the operation mode of data output, each of the flash memory chips 100_0 to 100_m-1 in each channel transmits the state of the state indicator (the R/B state for the master) through the corresponding Each port DQ0~DQ7 of the data bus is transmitted to the host controller.

In this way, the plurality of flash memory chips 100_1 to 100_m-1 on the channel of the NAND flash memory controller 200 can obtain each of the plurality of flash memories at one time through the ports DQ0 to DQ7 of the data bus DQ. The master controllers of the bulk dies 100_1 to 100_m-1 use the R/B state and do not need external R/B signal lines and pads, thereby reducing the number of pads in the controller.

FIG. 6B is a schematic timing diagram of an operation flow of another embodiment of the setting stage of each flash memory die in the control method of the NAND flash memory according to another embodiment of the present invention. FIG. 7B is a schematic diagram illustrating the operation flow of the setting stage of the master controller level.

As shown in FIG. 6B , in this embodiment, the setting phase may further include two cycles. Only the setting phase of this embodiment is different from the setting phase of the aforementioned FIG. 4A , and the requirement phase is basically the same. Therefore, the operation of the setting stage is described here.

As shown in FIG. 6B , in the setting phase, the operation mode is divided into two cycles, the first cycle is a command input (CMD input) cycle, and the second cycle is an address input (ADDR input) cycle. The two constitute the periodic pattern of the set R/B command.

After the enabling signal CE# of the NAND flash memory chip enables the chip, in the operation mode of command input, the NAND flash memory chip is received and sent from the NAND flash memory controller (main controller) 200 The prepare command (prepare command). The prepare command can also be defined by a vendor specific command, such as command FEh shown in FIG. 6B. The prepare command mainly informs or hints that each NAND flash memory die 100_0 to 100_m-1 is ready to assign a corresponding DQ port to transmit the R/B status.

Next, in the second cycle of the address input cycle, that is, in the address input operation mode shown in FIG. 6B , the NAND flash memory controller 200 will send a specific address value, which will correspond to a A specific DQ port corresponds to the R/B signal line of a NAND flash memory die. For example, at this stage, a value of 00h can be used for DQ0, a value of 01h for DQ1, etc., and so on.

Therefore, in this embodiment, in the first cycle of the setting stage, the NAND flash memory controller 200 may first send, for example, a command FEh to notify each of the NAND flash memory dies 100_0 to 100m-1 that their respective The R/B signal line is ready to establish a corresponding relationship with each port DQ0~DQ7 of the data bus DQ, that is, it is ready to assign each port DQ0~DQ7 to be mapped to the R/B of each NAND flash memory die 100_0~100m-1 respectively signal line. Then, in the second cycle of address input, by assigning addresses, the R/B signal states of each NAND flash memory die 100_0 to 100m-1 can be actually associated with each port DQ0 to DQ7. In this way, through the two-cycle setting stage, the manufacturer-specific commands and addresses can also be used to map each port DQ0~DQ7 and the internal R/B signal of each NAND flash memory chip one-to-one, and store them in the In the mapping state temporary register 106 shown in FIG. 3B to FIG. 3E .

A schematic diagram of an operation flow at the master level in this setting stage is shown in FIG. 7B . In the setting stage, sending the setting command from the host controller may further include: in step S102, in the operation mode of command input, sending a ready command (such as the above-mentioned command FEh) on the data bus DQ to notify each flash memory The dies 100_0 to 100_m-1 are ready for the R/B signal lines (status indicators) of respectively assigning the ports DQ0 to DQ7 of the data bus DQ to the plurality of flash memory dies 100_0 to 100_m-1. Next, in step S104, in the operation mode of address input, the host controller sends an address signal ADDR (such as the above-mentioned 00h, 01h, etc.) on the data bus DQ, thereby connecting the ports DQ0~ of the data bus DQ DQ7 corresponds to the R/B state signal lines (state indicators) of each of the flash memory chips 100_0 to 100_m-1, respectively.

FIG. 8 is a schematic diagram illustrating the operation timing of the flash memory controller according to the embodiment of the present invention. First, when the flash memory starts to operate, the data input and output have not been performed on the data bus DQ, that is, the flash memory is in an idle state, which can be set as shown in FIG. 6A or FIG. 6B above. In the operation of the stage, the set R/B command operation of the flash memory die 0 to the flash memory die 3 is performed. Next, the ports DQ0 to DQ3 of the data bus DQ are respectively assigned as the R/B signal lines of the flash memory die 0 to the flash memory die 3 . In other words, at the stage of setting the flash memory die, die 0 is set to the R/B state for the DQ0 output master, and the remaining DQ ports are in the high impedance state. Die 1 is set to the R/B state for the DQ1 output master controller, and the remaining DQs are in high impedance state. The settings of the rest of the dies are deduced by analogy.

In addition, when the controller (master) sets one of the flash memory chips 0 to 3 in the setting stage, for example, selecting DQ0 as the R/B state for the output master, the other flash memory The DQ0 corresponding to the DQ0 of the chips 1 to 3, that is, the respective DQ0s of the flash memory chips 1 to 3, will output a high impedance state. Similarly, the same settings are also performed for other flash memory chips 1 to 3.

In this way, the states of the R/B signal lines of the subsequent flash memory die 0 to flash memory die 3 can be respectively transmitted from DQ0 to DQ3 of the data bus DQ to the flash memory controller 200 . At this time, the state of the internal R/B signal lines of each of the flash memory chips 0 to 3 is in a ready state.

Then, the flash memory die enters an operation mode, that is, various operations such as writing and the like can be performed on each flash memory die. At this time, the states of the internal R/B signals of each of the flash memory chips 0 to 3 enter the busy state in sequence.

Then, after a period of time, the flash memory controller sends a request RB command to each of the flash memory chips 0-3. When each flash memory chip 0~3 receives the request RB command, it then sends the status of the R/B signal to the flash memory controller through the corresponding ports DQ0~DQ3. In this way, the flash memory controller can obtain the R/B state of each flash memory die 0-3 during the period from RB to DQ in FIG. 6 .

In the request stage, the master controller will simultaneously issue a request command to all the flash memory die 0-3, and each flash memory die 0-3 will demultiplex its own according to the configuration in the setting stage. The 8 outputs of the controller 130 are mapped to DQ[7:0] and finally aggregated on a DQ data bus. Thereby, as shown in FIG. 8, the results of X1h, X3h, . . . can be output on the DQ bus. Because the master controller will assign each flash memory chip 0-3 to the corresponding port during the setting, and do not allow multiple ports to output at the same time to avoid interference between signals. In other words, the two flash memory dies do not output to the same port at the same time. For example, taking channel 0 shown in Figure 3A as an example, when the state is output, flash memory die 0 will output zzzz_zzz1 on its DQ[7:0], and flash memory die 1 will output zzzz_zzz1 on its DQ[7:0] :0] output zzzz_zz0z, flash die 2 will output zzzz_z0zz on its DQ [7:0], flash die 3 will output zzzz_0zzz on its DQ [7:0] (where z represents the high impedance state ). Finally, the master DQ bus will output zzzz_0001 to indicate the status of each flash memory die 0-3.

Therefore, under the structure of the present embodiment, the R/B signal lines of the flash memory die are replaced by the manufacturer-specific command and the data bus, so the original R/B of each flash memory die can be saved. Signal lines and pads, so the flash memory controller does not need this R/B pad accordingly, so the number of pads in the controller can be effectively reduced, and the flash memory chip will not be increased. size and circuit complexity. In addition, the operation mode of this embodiment is performed by using the existing operation mode of data input and output, that is, the setting of the R/B signal and the DQ port is performed by using the idle period of the data bus, so no additional operation is required. It can also easily achieve the assignment of R/B signal and DQ port and output the mapping status value to the data bus DQ (external data bus) at the same time, which can reduce the need to poll each of the flash memory chips in turn. number of states. .

10_0~10_m-1: NAND flash memory die 20: Flash memory controller 100_0~100_m-1: NAND flash memory die 102: Logic control unit 104: Input and output unit 106, 106a: Mapping Status Register 106b: state selection register 108: R/B signal status (internal) 110: High Voltage Circuits 112: Command scratchpad 114: address scratchpad 116: Status register 118:Data buffer 120: Memory array 122: Y-decoder 124:X-Decoder 126: page buffer 130, 132': Demultiplexer 130a, 130'a: decoder 130b_0~130b_7, 130’b_0~130’b_7: Tri-state gate 131, 132: Multiplexer 132': Multiplexer Unit 132a, 132'a: decoder 132'b_0~132'b_7: Multiplexer 200: Flash memory controller

FIG. 1 is a schematic diagram of an open-drain output of a conventional NAND flash memory die structure. 2A and 2B are schematic diagrams illustrating the structure of a conventional NAND flash memory. FIG. 3A is a schematic diagram illustrating a structure of a flash memory according to an embodiment of the present invention. FIG. 3B is a schematic structural diagram of a NAND flash memory die according to an embodiment of the present invention. 3C and 3D further illustrate a schematic diagram of the circuit structure of the I/O control unit in the flash memory die shown in FIG. 3B . FIG. 3E is a schematic diagram of the circuit structure of the demultiplexer in FIG. 3D . FIG. 4A is a schematic structural diagram of another NAND flash memory die according to an embodiment of the present invention. FIG. 4B is a schematic diagram of the circuit structure of the I/O controller unit in FIG. 4A . FIG. 5 is a schematic diagram of a circuit structure of an I/O control unit in a flash memory die according to another embodiment. FIG. 6A is a schematic diagram illustrating the operation flow of each flash memory die in the NAND flash memory control method according to the embodiment of the present invention. FIG. 6B is a schematic timing diagram of an operation flow of another embodiment of the setting stage of each flash memory die in the control method of the NAND flash memory according to another embodiment of the present invention. 7A is a schematic diagram illustrating an operation flow of a host controller on a plurality of NAND flash memory dies on a channel according to an embodiment of the present invention. FIG. 7B is a schematic diagram illustrating an operation flow of another embodiment of the setting stage of FIG. 7A . FIG. 8 is a schematic diagram illustrating the operation timing of the flash memory controller according to the embodiment of the present invention.

100_0~100_m-1: NAND flash memory die

102: Logic control unit

104: Input and output unit

106a: Map Status Register

106b: state selection register

108: R/B signal status (internal)

110: High Voltage Circuits

112: Command scratchpad

114: address scratchpad

116: Status register

118:Data buffer

120: Memory array

122: Y-decoder

124:X-Decoder

126: page buffer

Claims (26)

A control method of a flash memory, wherein the flash memory has an external data bus connecting a plurality of flash memory chips, and the control method includes: In the setting stage, in the operation mode of command input, a setting command is sent from the host controller, and each port of the external data bus is respectively mapped to the status indicator of each of the flash memory chips; and In the request stage, in the operation mode of command input, the host controller sends a request command to each of the plurality of flash memory chips, and in the operation mode of data output, each of the flash memory The state of the state indicator of the bulk die is transmitted to the host controller via the corresponding ports of the external data bus. The method for controlling a flash memory according to claim 1, wherein in the setting stage, sending the setting command by the host controller further comprises: In the operation mode of command input, the host controller sends a prepare command to notify each of the plurality of flash memory dies to prepare for assigning each port of the external data bus to each of the plurality of the state indicator of the flash memory die; and In the operation mode of address input, the host controller sends out address signals, thereby mapping each port of the external data bus to the status indicators of each of the plurality of flash memory chips, respectively. The control method of a flash memory according to claim 1, wherein each flash memory die has a plurality of output ports respectively coupled to the ports of the external data bus, and in the setting stage, the a first output port of one of the first flash memory die of one of the plurality of flash memory die is selected for transmitting the status indicator, wherein the output ports corresponding to the first output ports of each of the plurality of flash memory dies other than the first flash memory die are in an output high impedance state, Output ports other than the first output port of the first flash memory output a high impedance state. The control method of a flash memory according to claim 1, wherein the state indicator is a ready/busy state for the master The control method of a flash memory according to claim 1, wherein the setting command and the request command are defined by manufacturer-specific commands. The control method of a flash memory according to claim 1, wherein the main controller is a flash memory controller. A flash memory die, comprising at least: a plurality of output ports coupled to an external data bus; a control logic unit to provide status indicators of the flash memory die; a mapping state register for storing data for selecting one of the plurality of output ports corresponding to the state indicator of the flash memory die; and input/output control unit, Wherein the input/output control unit further includes: The first multiplexer has a plurality of inputs and outputs, the plurality of inputs respectively receive data from a plurality of sets of internal busbars, the outputs are coupled to the plurality of output ports, wherein the first multiplexer According to a selection signal provided by the control logic unit, one of the multiple inputs is selected and output to the external data bus, and the multiple sets of internal bus at least include an internal data bus, a state indicator bus and a mapping state busbars; and a demultiplexer having an input, a plurality of outputs and select lines, wherein the input receives the state indicator, the select line receives the data stored from the map state register, the demultiplexer The output of the demultiplexer is connected via the map state bus to the input of the first multiplexer, wherein the demultiplexer selects the multiplexer of the demultiplexer based on the data received by the select line One of the outputs to convey the state indicator, the unselected outputs of the demultiplexer are output at high impedance. The flash memory die of claim 7, wherein when the flash memory die receives a set command sent by a host controller, the state index of the flash memory die is mapped to one of the plurality of output ports. The flash memory die of claim 8, wherein when the flash memory die receives a request command from the master, the demultiplexer of the input/output control unit is based on the mapping the data stored in the state register, selecting the output port corresponding to the state index of the flash memory chip, and sending the state of the state index through the selected output port to the master controller. The flash memory die of claim 9, wherein when the request command is received, an unselected one of the plurality of output ports is in a high impedance state. The flash memory die of claim 9, wherein the set command and the request command are defined by vendor-specific commands. The flash memory die of claim 8, wherein the host controller is a flash memory controller. The flash memory die of claim 7, wherein the state indicator is a ready/busy state for the master. The flash memory die of claim 7, wherein the input/output control unit further comprises: A second multiplexer, the output of the second multiplexer is coupled to the input of the demultiplexer, and is used for selecting one output from a plurality of state registers to the demultiplexer. The flash memory die of claim 7, wherein the input/output control unit further comprises: a multiplexer unit coupled to the demultiplexer, wherein the multiplexer unit includes a plurality of multiplexer, Each of the plurality of multiplexers receives a plurality of state registers, and selects one of the plurality of state registers to output to the demultiplexer, The outputs of the multiplexers are provided to the demultiplexer and input to the first multiplexer via the map state bus. A control method of a flash memory, wherein the flash memory has an external data bus connecting a plurality of flash memory chips, and the control method includes: Sending a setting command from the host controller to correspond each port of the external data bus with the state index of each of the flash memory chips respectively; and sending a request command to each of the flash memory chips by the host controller; When each of the plurality of flash memory dies receives the request command, the state of the state indicator of each of the plurality of flash memory dies is passed through each of the corresponding external data buses. port to the host controller. The control method of a flash memory according to claim 16, wherein sending the setting command by the host controller further comprises: sending a prepare command to notify each of the plurality of flash memory dies to prepare for assigning ports of the external data bus to each of the plurality of flash memory dies, respectively; and An address signal is sent out, whereby each port of the external data bus of each of the plurality of flash memory chips corresponds to the state indicators of each of the plurality of flash memory chips, respectively. The control method of a flash memory according to claim 16, wherein each of the flash memory chips has a plurality of output ports respectively coupled to the ports of the external data bus, and the plurality of flash memory a first output port of one of the first flash memory dies of one of the memory dies is selected to transmit the status indicator, wherein the output ports corresponding to the first output ports of each of the plurality of flash memory dies other than the first flash memory die are in an output high impedance state, Output ports other than the first output port of the first flash memory output a high impedance state. The control method of a flash memory according to claim 16, wherein the state indicator is a ready/busy state for the master. The control method of a flash memory according to claim 16, wherein the setting command and the request command are defined by manufacturer-specific commands. The control method of a flash memory according to claim 16, wherein the main controller is a flash memory controller. A flash memory comprising: at least one external data bus with multiple ports; a plurality of flash memory chips, respectively coupled to the at least one external bus bar; and a main controller, coupled to the at least one external bus, for controlling the plurality of flash memory chips, In the setting stage, the host controller sends a setting command to correspond each port of the external data bus with the state index of each of the flash memory chips, respectively, In the request stage, the host controller sends a request command to each of the flash memory chips, and each of the plurality of flash memory chips receives the request command, and each of the plurality of flash memory chips receives the request command. The state of the state indicator of the flash memory die is transmitted to the host controller via the corresponding ports of the external data bus. The flash memory of claim 22, wherein sending the setting command by the host controller further comprises: sending a prepare command to notify each of the plurality of flash memory dies to prepare for assigning ports of the external data bus to each of the plurality of flash memory dies, respectively; and An address signal is sent out, whereby each port of the external data bus of each of the plurality of flash memory chips corresponds to the state indicators of each of the plurality of flash memory chips, respectively. The flash memory of claim 22, wherein each of the flash memory die has a plurality of output ports respectively coupled to ports of the external data bus, the plurality of flash memory die a first output port of one of the first flash memory dies of one of the dies is selected to transmit the status indicator, wherein the output ports corresponding to the first output ports of each of the plurality of flash memory dies other than the first flash memory die are in an output high impedance state, Output ports other than the first output port of the first flash memory output a high impedance state. The flash memory of claim 22, wherein the state indicator is a ready/busy state for the master. The flash memory of claim 22, wherein the set command and the request command are defined by vendor-specific commands.

Images