TWI739091B - Selection circuitries and method for preventing latch-up of memory storage system - Google Patents

Abstract

Various embodiments of selection circuitries and a method for preventing latch-up of a memory storage system are disclosed. The selection circuitry selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the selection circuitry selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the selection circuitry selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption. Moreover, the selection circuitry selectively provide the maximum operational voltage signal to bulk (B) terminals of some of their transistors to prevent latch-up of these transistors. In some situations, the selection circuitry can dynamically adjust the maximum operational voltage signal to compensate for fluctuations in the maximum operational voltage signal.

Description

Selection circuit and the one used to prevent latch-up of the memory storage system method

This disclosure relates to a selection circuit and a method for preventing latch-up of a memory storage system.

The memory storage system is an electronic device used to read and/or write electronic data. The memory storage system includes an array of memory cells, which can be implemented as volatile memory cells that require power to maintain their stored information, such as random-access memory (RAM) cells, Or a non-volatile memory unit such as a read-only memory (ROM) unit that can maintain the stored information even if it is not powered. Electronic data can be read and/or written into a memory cell array, which can be accessed through various control lines. The two basic operations performed by the memory device are " read " and " write ". In reading, the electronic data stored in the memory cell array is read, and in writing, the electronic data is written In the memory cell array.

The selection circuit of the present disclosure is used to selectively provide an operable voltage signal The selection circuit to the memory storage system. The selection circuit includes a switch circuit and a latch-up prevention circuit. The switching circuit has multiple transistors. The switch circuit is configured to select an operable voltage signal from among a plurality of operable voltage signals, and a maximum operable voltage signal among the plurality of operable voltage signals is selectively applied to the base terminal of the plurality of transistors. The latch-up prevention circuit is configured to dynamically adjust the maximum operable voltage signal to compensate for fluctuations in the maximum operable voltage signal.

Another selection circuit of the present disclosure is used in a memory storage system. The selection circuit includes a switch circuit and a latch-up prevention circuit. The switching circuit has multiple transistors. The switch circuit is configured to provide an operable voltage signal selected from the plurality of operable voltage signals to the memory storage system. The latch-up prevention circuit has a first diode connected to the transistor and a second diode connected to the transistor. The latch-up prevention circuit is configured to apply the maximum operable voltage signal selected from the plurality of operable voltage signals to the first base terminal of the first diode connection transistor and the second diode connection transistor. The second base extreme. The first diode connected to the transistor is configured to obtain the first current from the first operable voltage signal when it is started, so as to adjust the maximum operable voltage signal to compensate for the fluctuation of the maximum operable voltage signal. The second diode connected to the transistor is set to obtain the second current from the second operable voltage signal when it is started, so as to adjust the maximum operable voltage signal to compensate for the fluctuation of the maximum operable voltage signal.

The disclosed method for preventing the latch-up of a memory storage system includes: applying a maximum operable voltage signal selected from a plurality of operable voltage signals to at least one transistor of the memory storage system by the memory storage system And at least one gate area applied to at least one transistor; and when the maximum operable voltage signal fluctuates below the first operable voltage signal among the plurality of operable voltage signals, by The memory storage system increases the maximum operable voltage No.

100, 500: memory storage system

102: Voltage generator circuit

104.1, 104. x , 200.1~200. m , 220.1~220. n , 400: select circuit

106, 202, 222: memory device

150: Bias control signal

152: Select control signal

204, 224: memory array

210.1.1 ~ 210 m n, 226.1.1 ~ 226 m n:.... The memory unit

212.1~212. n , 350: word line

214.1, 214. m , 352: bit line

300: SRAM cell

402: switch circuit

404: Latch Prevention Circuit

452, 452: Bias control signal

502, 504, 506: Operation

I _DD , I _DDM : current

N1~N3, N4: n-type metal oxide semiconductor transistor

P1, P2, P4, P5, P6, P7: p-type metal oxide semiconductor transistor

V ₁ , V _DD , V _DDM , V _{DDM_INT} , V _{DDM_INT.1} , V _{DDM_INT. m} , V _{DDM_INT. n} , V _{DDM_INT. x} , V _m : operable voltage signals

V _DDMAX : Maximum operable voltage signal

Reading the following detailed description in conjunction with the accompanying drawings will best understand the aspect of the present disclosure. It should be noted that according to standard practices in the industry, various features are not drawn to scale. In fact, the size of various features can be arbitrarily increased or decreased for clarity of discussion.

FIG. 1 shows a block diagram of an exemplary memory storage system according to an exemplary embodiment of the present disclosure.

FIG. 2A shows a block diagram of a first exemplary memory device that can be implemented in an exemplary memory storage system according to an exemplary embodiment of the present disclosure.

2B shows a block diagram of a second exemplary memory device that can be implemented in an exemplary memory storage system according to an exemplary embodiment of the present disclosure.

FIG. 3 shows a block diagram of an exemplary static random-access memory (SRAM) cell that may be implemented in an exemplary memory device according to the disclosed exemplary embodiment.

FIG. 4 shows a block diagram of an exemplary selection circuit that may be implemented in an exemplary memory device according to an exemplary embodiment of the present disclosure.

FIG. 5 shows a flowchart of an exemplary operation of an exemplary memory storage system according to an exemplary embodiment of the present disclosure.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify This disclosure. Of course, these components and configurations are only examples and are not intended to be limiting. For example, in the following description, the formation of the first feature above the second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include additional features that may be formed between the first feature and the second feature. An embodiment in which features are formed so that the first feature and the second feature may not directly contact each other. In addition, the present disclosure may repeat icon numbers and/or letters in various examples. This repetition itself does not indicate the relationship between the various embodiments and settings described.

Overview

The present invention discloses various embodiments in which a memory storage system can be provided. The memory storage can be set to selectively select the operable voltage signal from a plurality of operable voltage signals to dynamically control various operating parameters. For example, the memory storage system can be set to selectively select the maximum operable voltage signal from a plurality of operable voltage signals to maximize the read/write speed. As another example, the memory storage system can be configured to selectively select the smallest operable voltage signal from a plurality of operable voltage signals to minimize power consumption. In addition, the memory storage system can be configured to selectively provide the maximum operable voltage signal to the bulk (B) terminals of some of its transistors to prevent these transistors from latching up. In some cases, the memory storage system can be configured to dynamically adjust the maximum operable voltage signal to compensate for fluctuations in the maximum operable voltage signal.

Exemplary memory storage system

FIG. 1 shows a block diagram of an exemplary memory storage system according to an exemplary embodiment of the present disclosure. In the exemplary embodiment shown in FIG. 1, the memory storage system 100 selectively selects among a plurality of operable voltage signals to dynamically control the operation. For example, the memory storage system 100 may select an operable voltage signal from a plurality of operable voltage signals to configure the memory storage system 100 to dynamically control (for example, minimize or maximize) the amount from the memory storage system 100. One or more of the operating parameters, such as power consumption and/or read/write speed. As shown in FIG. 1, the memory storage system 100 includes a voltage generator circuit 102, selection circuits 104.1 to 104. x, and a memory device 106.

The voltage generator circuit 102 selectively provides the maximum operable voltage signal V _{DDMAX from the operable voltage signal V 1} to the operable voltage signal V _m according to the bias voltage control signal 150 to the selection circuits 104.1 to 104. x . For example, the maximum operable voltage signal V _DDMAX may represent the maximum operable voltage signal among the operable voltage signals V ₁ to V _m. In some cases, the maximum operable voltage signal among the operable voltage signals V ₁ to V _{m is known empirically.} In an exemplary embodiment, the voltage generator circuit 102 includes a plurality of switches to selectively provide a maximum operable voltage signal _{from the operable voltage signals V 1} to V _{m as the maximum operable voltage signal V DDMAX} . In this exemplary embodiment, the bias control signal 150 includes one or more control bits, and various combinations of the one or more control bits correspond to various operable voltages among the _{operable voltage signals V 1} ~V _m. Signal. In this exemplary embodiment, the bias voltage control signal 150 may be set to _{a combination of control bits corresponding to the maximum operable voltage signal among the operable voltage signals V 1} ~V _m , so as to set the voltage generator circuit 102 from the operable voltage signal. _{Among the} operating voltage signals V ₁ to V _m , the maximum operable voltage signal is selectively provided as the maximum operable voltage signal V DDMAX to the selection circuits 104.1 to 104. x . In this exemplary embodiment, this combination of control bits activates (ie, closes) one or more of the plurality of switches to provide the maximum operable voltage signal _{from the operable voltage signals V 1} to V _m As the maximum operable voltage signal V _DDMAX , the remaining switches among the plurality of switches are simultaneously blocked (ie, opened).

In the exemplary embodiment shown in FIG. 1, the selection circuits 104.1 to 104. x react to the selection control signal 152 to selectively provide one of the operable voltage signals V ₁ to V _m as the operable voltage signal V _{DDM_INT.1} ~V _{DDM_INT. x} to control one or more operating parameters of the memory device 106. The selection control signal 152 can be set to various combinations of one or more control bits to selectively provide one of the operable voltage signals V ₁ ~V _m as the operable voltage signal V _{DDM_INT.1} ~V _{DDM_INT.x} , In order to dynamically control multiple operating parameters of the memory device 106. For example, one or more control bits can be set as the first bit combination to _{select the minimum operable voltage signal from the operable voltage signals V 1} ~V _m to dynamically control (for example, minimize) the memory The power consumption of the device 106. In this example, when compared with _{other operable voltage signals among the operable voltage signals V 1} ˜V _m , the minimum operable voltage signal results in less unwanted leakage in various transistors of the memory device 106. As another example, one or more control bits can be set as the second bit combination to _{select the maximum operable voltage signal from the operable voltage signals V 1} ~V _m to dynamically control (for example, maximize) the memory The read/write speed of the physical device 106. In some cases, the selection control signal 152 can be switched during the operation of the memory storage system 100 to dynamically set the memory device 106 during operation to control one or more operating parameters. In this other example, when compared with _{other operable voltage signals among the operable voltage signals V 1} ~V _m , the maximum operable voltage signal can make the various transistors of the memory cell of the memory device 106 faster The rate is off and/or on. As another example, the selection control signal 152 can be set to a second bit combination to maximize the read/write speed of the memory device 106 and dynamically reset to a different bit combination during operation, thereby reducing memory The read/write speed of the physical device 106.

In an exemplary embodiment, the selection circuits 104.1 to 104. x include a plurality of switches to selectively provide one of the operable voltage signals V ₁ to V _m as the operable voltage signal V _{DDM_INT.1} to V _{DDM_INT.x} . In this exemplary embodiment, the selection control signal 152 includes one or more control bits, and various combinations of the one or more control bits correspond to various operable voltage signals among the _{operable voltage signals V 1} to V _m. . In this exemplary embodiment, the selection control signal 152 may be set to _{a combination of control bits corresponding to the maximum operable voltage signal among the operable voltage signals V 1} ~V _m to set the selection circuit 104.1~104. x , The maximum operable voltage signal from the operable voltage signals V ₁ ~V _m is used as the operable voltage signal V ₁ ~V _m as the operable voltage signal V _{DDM_INT.1} ~V _{DDM_INT.x} , which is selectively provided to the memory device 106. In this exemplary embodiment, this combination of control bits activates (ie, closes) one or more switches from among a plurality of switches to provide a maximum operable voltage signal _{from among the operable voltage signals V 1} ~V _m And is the maximum operable voltage signal V _DDMAX , simultaneously blocking (that is, opening) the remaining switches among the plurality of switches. In this exemplary embodiment, multiple switches may be implemented using transistors, such as p-type metal-oxide-semiconductor (PMOS) transistors, which have a semiconductor substrate formed on a semiconductor substrate. The source terminal, drain terminal, gate terminal and base (B) terminal in the well area. As will be described in further detail below, the selection circuits 104.1 to 104. x provide the maximum operable voltage signal V _DDMAX from the voltage generator circuit 102 to the base (B) terminal of the transistors, so that the source of these transistors is formed The parasitic diodes between the (source; S) terminal and the well are reverse biased, that is, non-conductive, to prevent latching of these transistors. In some cases, the maximum operable voltage signal V _{DDMAX may fluctuate,} for example, in response to unwanted electromagnetic coupling and/or leakage between the well region of the transistor and the semiconductor substrate. In these cases, the selection circuits 104.1 to 104. x can dynamically adjust the maximum operable voltage signal V _DDMAX to compensate for these fluctuations of the maximum operable voltage signal V _DDMAX , as will be discussed in further detail below.

The memory device 106 receives the operable voltage signals V _{DDM_INT.1} to V _{DDM_INT.x which} are selectively selected from the operable voltage signals V ₁ to V _m . In the exemplary embodiment shown in FIG. 1, the memory device 106 includes memory cells arranged in an array of m rows and n columns. In this exemplary embodiment, the memory device 106 provides each of the operable voltage signals V _{DDM_INT.1} to V _{DDM_INT.x} to m rows of the memory array as discussed in further detail in FIG. 2A below The corresponding rows therein and/or are provided to corresponding columns among the n columns of the memory cell array as discussed in further detail in FIG. 2B below.

Exemplary memory device that can be implemented in an exemplary memory storage system

FIG. 2A shows a block diagram of a first exemplary memory device that can be implemented in an exemplary memory storage system according to an exemplary embodiment of the present disclosure. In the exemplary embodiment shown in FIG. 2A, the selection circuits 200.1 to 200. m selectively provide operable in a manner substantially similar to the selection circuits 104.1 to 104. x described in FIG. 1 above. The voltage signals V _{DDM_INT.1} to V _{DDM_INT. m are used} to set the operation of the memory device 202. The memory device 202 may represent an exemplary embodiment of the memory device 106 as described in FIG. 1 above. In an exemplary embodiment, the selection circuit 200.1 to 200. m selectively provides the first operable voltage signal as the operable voltage signal V _{DDM_INT.1} to V _{DDM_INT. m} from the plurality of operable voltage signals to set the memory The body device 202 dynamically controls (eg, minimizes) one or more of the multiple operating parameters of the memory device 202, such as power consumption and/or read/write speed. As another example, the selection circuit 200.1~200. m selectively provides a second operable voltage signal from a plurality of operable voltage signals, so as to set the memory device 202 to dynamically control (for example, maximize) the memory device 202 One or more operating parameters.

In the exemplary embodiment shown in FIG. 2A, the memory device 202 includes a memory array 204. Although not shown in FIG. 2A, the memory device 202 may include other electronic circuits, such as a sense amplifier, a column address decoder, and/or a row address decoder to provide some examples, which do not deviate from the spirit of the present disclosure. In the case of and category, it will be obvious to those with general knowledge in the relevant technical field. As shown in FIG. 2A, the memory array 204 includes memory cells 210.1.1 to 10. m . n arranged and arranged in an array of m rows and n columns. However, other configurations of the memory unit 210.1.1 to 210. m . n may not deviate from the spirit and scope of this disclosure. In the exemplary embodiment shown in FIG. 2A, the memory cells 210.1.1 to 210. m . n are connected to corresponding word lines (wordline; WL) and bits among the word lines 212.1 to 212. n Corresponding bit line (bitline; BL) among the line 214.1~bit line 214. m. Word lines 212.1 and 212. n ~ word line / bit line or bit line 214. m ~ 214.1 may be used to "read" mode of operation to read data stored in an electronic memory array 204 and / or to "write The "in" operation mode writes electronic data into the memory array 204. The " read " operation mode and the " write " operation mode represent conventional read and write operations, and will not be described in further detail.

2A, the selection circuit 200.1 ~ 200. M operably voltage signal _V DDM_INT.1 ~ V _{DDM_INT. M} is selectively supplied to the memory cell 210.1.1 ~ 210. M. N among the m One or more corresponding rows of the row. For example, the selection circuit 200.1 _{selectively provides the operable voltage signal V DDM_INT.1} to the first row of the memory cells 210.1.1 to 210.1. n , and the selection circuit 200. m will operate the voltage signal V _{DDM_INT. m is} selectively provided to the m- th row of the memory cell 210. m. 1 to 210. m . n . Although not shown in FIG. 2A, each of the selection circuits 200.1 to 200. m can transmit an operable voltage signal The corresponding operable voltage signal among V _{DDM_INT.1} to V _{DDM_INT. m} is selectively provided to more than one row among the m rows of memory cells 210.1.1 to 210. m . n. In an exemplary embodiment, the memory cell 210. m. 1 to 210. m . n may be implemented using one or more transistors, such as one or more p-type metal oxide semiconductor (PMOS) transistors. Crystal, one or more n-type metal-oxide-semiconductor (NMOS) transistors or any combination of PMOS transistors and NMOS transistors, without departing from the spirit and scope of this disclosure It will be obvious to those with ordinary knowledge in the relevant technical field. In this exemplary embodiment, the selection circuit 200.1 ~ 200. M may be operable voltage signal _V DDM_INT.1 ~ V _{DDM_INT. M} is selectively supplied to the memory cell 210.1.1 ~ 210. M. N of the m The base (B) terminal of the transistor in the corresponding row in the row. The operable voltage signal V _{DDM_INT.1} ~V _{DDM_INT. m is} effective so that the parasitic diodes formed between the source (S) terminals of these transistors and the well region in this example are reverse biased (that is, non- Conductive) to prevent latch-up, as will be discussed in further detail in Figure 3 below.

2B shows a block diagram of a second exemplary memory device that can be implemented in an exemplary memory storage system according to an exemplary embodiment of the present disclosure. In the exemplary embodiment shown in FIG. 2B, the selection circuits 220.1 to 220. n selectively provide operable in a manner substantially similar to the selection circuits 104.1 to 104. x described in FIG. 1 above. The voltage signals V _{DDM_INT.1} to V _{DDM_INT. n are used} to set the operation of the memory device 222. The memory device 222 may represent an exemplary embodiment of the memory device 106 as described in FIG. 1 above. In an exemplary embodiment, the selection circuit 220.1 to 220. n selectively provides the first operable voltage signal as the operable voltage signal V _{DDM_INT.1} to V _{DDM_INT. n} from the plurality of operable voltage signals to set the memory The body device 222 dynamically controls (eg, minimizes) one or more of the multiple operation parameters of the memory device 222, such as power consumption and/or read/write speed. As another example, the selection circuits 220.1 to 220. n selectively provide a second operable voltage signal from a plurality of operable voltage signals to set the memory device 222 to dynamically control (for example, maximize) the memory device 222 One or more operating parameters.

In the exemplary embodiment shown in FIG. 2B, the memory device 222 includes a memory array 224. Although not shown in FIG. 2B, the memory device 222 may include other electronic circuits, such as a sense amplifier, a column address decoder, and/or a row address decoder to provide some examples, without departing from the spirit and scope of the present disclosure. In the case of, it will be obvious to those with ordinary knowledge in the relevant technical field. As shown in FIG. 2B, the memory array 224 includes memory cells 226.1. 1 to 226. m . n arranged and arranged in an array of m rows and n columns. However, other configurations of the memory unit 226.1.1 to 226. m . n may not deviate from the spirit and scope of this disclosure. In the exemplary embodiment shown in FIG. 2B, the memory cells 226.1.1 to 226. m . n are connected to the corresponding word line (WL) and bit line 214.1 among word lines 212.1 to 212. n ~ The corresponding bit line (BL) among the bit lines 214. m.

As shown in FIG. 2B, the selection circuit 220.1 ~ 220. m selectively provides the operable voltage signal V _{DDM_INT.1} ~ V _{DDM_INT. n} to n rows among the memory cells 226.1.1 ~ 226. m . n One or more corresponding columns of. For example, the selection circuit operatively 220.1 _V DDM_INT.1 voltage signal is selectively supplied to the first column of the memory unit 226.1.1 ~ 226.m.1, and the selection circuit 220. n the operable voltage signal _V DDM_INT _{. n is} selectively provided to the n-th row of memory cells 226.1. n ~226. m . n . Although not shown in FIG. 2B, each of the selection circuits 220.1 to 220. m can selectively provide its corresponding operable voltage signal among the operable voltage signals V _{DDM_INT.1} to V _{DDM_INT. n to the memory} More than one column among the n columns of cells 226.1.1 to 226. m . n. In an exemplary embodiment, the memory cell 226. m. 1 to 226. m . n may be implemented using one or more transistors, such as one or more p-type metal oxide semiconductor (PMOS) transistors. Crystals, one or more n-type metal oxide semiconductor (NMOS) transistors, or any combination of PMOS transistors and NMOS transistors, without departing from the spirit and scope of this disclosure, will be useful in related technical fields. Usually the knowledgeable person is obvious. In this exemplary embodiment, the selection circuit 220.1 ~ 220. N may be operable voltage signal _V DDM_INT.1 ~ V _{DDM_INT. N} is selectively provided to the memory cell 226.1.1 ~ 226. M. N of the m The base (B) terminal of the transistor in the corresponding row in the row. The operable voltage signals V _{DDM_INT.1} to V _{DDM_INT. n are} effective so that the parasitic diodes formed between the source (S) terminals of these transistors and the well region are reverse biased (that is, non- Conductive) to prevent latching of these transistors, as will be discussed in further detail in Figure 3 below.

An exemplary memory unit that can be implemented in an exemplary memory device

As described above in FIGS. 1, 2A, and 2B, the exemplary memory device described therein, such as the memory device 106 described in FIG. 1 above, as described in FIG. 2A above, which provides some examples The memory device 202 and/or the memory device 222 as described in FIG. 2B above include an array of memory cells such as the memory cell 210.1.1 described in FIG. 2A above to provide some examples. ~210. m . n and/or the memory unit 226.1. 1 ~ 226. m . n as described in Figure 2B above. The discussion of Figure 3 below describes various embodiments of these memory cells. However, those with ordinary knowledge in the relevant technical field will recognize that without departing from the spirit and scope of the present disclosure, the teachings of the various embodiments of these memory units described below can be easily modified for any suitable use. The volatile memory cell, such as any random access memory (RAM) cell, and/or any suitable non-volatile memory cell, such as any read-only memory (ROM) cell. The RAM unit can be implemented as a dynamic random-access memory (DRAM) unit, a static random-access memory (SRAM) unit, and/or a non-volatile random-access memory (non-volatile random-access memory) unit. memory; NVRAM) cells, such as flash memory cells to provide examples. The ROM unit can be implemented as a programmable read-only memory (PROM) unit, one-time programmable ROM (OTP) unit, erasable programmable ROM (OTP) unit providing some examples Erasable programmable read-only memory (EPROM) units and/or electrically erasable programmable read-only memory (EEPROM) units.

FIG. 3 shows a block diagram of an exemplary static random access memory (SRAM) cell that can be implemented in an exemplary memory device according to an exemplary embodiment of the present disclosure. In the exemplary embodiment shown in FIG. 3, the SRAM cell 300 may be used to implement one or more memory cells of the memory device 106 as described in FIG. 1 above, and the memory as described in FIG. 2A above. memory device body unit 202 210.1.1 ~ 210. m. n or a plurality and / or the memory described above in FIG. 2B apparatus described memory cell 222 226.1.1 ~ 226. m. n One or more of. As shown in FIG. 3, the SRAM cell 300 includes p-type metal oxide semiconductor (PMOS) transistors P1 and p-type metal oxide semiconductor transistors P2, and n-type metal oxide semiconductor (NMOS) transistors N1 to N4.

In the exemplary embodiment shown in FIG. 3, the PMOS transistor P1 and the NMOS transistor N1 are configured to form a first logic inverter (INVERTER) gate, and the PMOS transistor P2 and the NMOS transistor N2 are It is configured to form a second logic inverter gate. The gate of the first logic inverter is cross-coupled with the gate of the second logic inverter as shown in FIG. 3. For example, the input coupling of the gate of the first logic inverter The output of the gate of the second logic inverter is connected, and the output of the gate of the first logic inverter is coupled to the input of the gate of the second logic inverter. In this cross-coupling configuration, the first logical inverter and the second logical inverter cooperate in function to enhance the information stored in the SRAM cell 300.

In the exemplary embodiment shown in FIG. 3, the information stored in the gate of the first logic inverter and the gate of the second logic inverter is at a logic 0 (logical zero) and a logic 1 (logical one). Cyclically convert between, such as the operable voltage signal V _{DDM_INT.} Operable embodiment, the voltage signal _V DDM_INT operable operable voltage signals represented in FIG. 1 described above the _V DDM_INT.1 ~ V DDM_INT exemplary embodiment _{in. X} of one, as described above in FIG 2A _{An exemplary} embodiment of one of the voltage signals V DDM_INT.1 to V _{DDM_INT. m} and/or one of the operable voltage signals V _{DDM_INT.1} to V _{DDM_INT. n} as described in FIG. 2B above. In another exemplary embodiment, the first logic inverter and the second logic inverter receive the operable voltage signal V _{DDM_INT} from a selection circuit such as the one described in FIG. 1 above to provide some examples the selection circuit 104.1 ~ 104. x of one, as described above in FIG selection circuit 2A described in 200.1 ~ 200. m of one and / or the above FIG selection circuit 2B described in 220.1 ~ 220. n in One of them.

During the " read " operation, NMOS transistor N3 and NMOS transistor N4 are activated by verifying word line (WL) 350. This activation of NMOS transistor N3 and NMOS transistor N4 couples the first logic inverter and the second logic inverter to the bit line (BL) 352. In an exemplary embodiment, the word line 350 may represent one of the word lines 212.1 to 212. n as described in FIGS. 2A and 2B above, and the bit line 352 may represent one of the word lines 212.1 to 212. n as described in FIGS. 2A and 2B above. One of the bit line 214.1 to the bit line 214. m described in 2B. Thereafter, the data stored in the first logic inverter and the second logic inverter are transferred to the bit line (BL) 352. Similarly, during the " write " operation, the NMOS transistor N3 and the NMOS transistor N4 are activated by verifying the word line 350 to couple the first logic inverter and the second logic inverter to the bit line 352. After that, the state of the bit line 352 is transferred to the first logic inverter and the second logic inverter to be stored as information in the first logic inverter and the second logic inverter.

In addition, as shown in FIG. 3, the operable voltage signal V _{DDM_INT is} coupled to the first base (B) terminal of the PMOS transistor P1 and the second base (B) terminal of the PMOS transistor P2. In the exemplary embodiment shown in FIG. 3, the PMOS transistor P1 is located in the first n-type well in the p-type semiconductor substrate, and the PMOS transistor P2 is located in the second n-type well in the p-type semiconductor substrate. Area. In this exemplary embodiment, the operable voltage signal V _{DDM_INT} transfers the charge from the base (B) end of the PMOS transistor P1 and the base (B) end of the PMOS transistor P2 to the first n-type well region and The second n-type well area.

An exemplary selection circuit in an exemplary memory storage system

As described in Figure 1 above, the selection circuit 104.1~104. x selectively provides one of the operable voltage signals V ₁ ~V _m as the operable voltage signal V _{DDM_INT.1} ~V _{DDM_INT. x} to control the memory One or more operating parameters of the body device 106. The following discussion of FIG. 4 describes an exemplary embodiment of one of the selection circuits 104.1 to 104. x.

FIG. 4 shows a block diagram of an exemplary selection circuit that may be implemented in an exemplary memory device according to an exemplary embodiment of the present disclosure. In the exemplary embodiment shown in FIG. 4, the selection circuit 400 selectively provides the operable voltage signal V _{DDM_INT from the operable voltage signal V DD} and the operable voltage signal V _DDM to control one of the memory devices Or a plurality of operating parameters, the memory device such as the memory device 106 to provide examples. In an exemplary embodiment, the operable voltage signal V _DDM and the operable voltage signal V _DD may represent exemplary embodiments of both of _{the operable voltage signals V 1} ˜V _m as described in FIG. 1 above. In another exemplary embodiment, the operable voltage signal V _DD corresponds to the operable voltage signal allocated to other digital circuits that are communicatively coupled to the memory device, and the operable voltage signal V _DDM corresponds to the operable voltage signal allocated to the memory device. The operable voltage signal of the body device. In some cases, the operable voltage signal V _{DD is} greater than the operable voltage signal V _DDM ; however, in other cases, the operable voltage signal V _DD may be less than the operable voltage signal V _DDM . In the exemplary embodiment shown in FIG. 4, the selection circuit 400 selects _{the larger of the operable voltage signal V DDM} and the operable voltage signal V _DD as the operable voltage signal V _{DDM_INT} to connect the memory device 106 The read/write speed of the corresponding row of memory cells as described in FIG. 2A above and/or the corresponding column of memory cells as described in FIG. 2B above is maximized. Otherwise, the selection circuit 400 selects the _{smaller of the operable voltage signal V DDM} and the operable voltage signal V _DD as the operable voltage signal V _{DDM_INT} to store the corresponding row memory cell and/or the corresponding column of the memory device 106 The power consumption of the body unit is minimized.

In addition, as will be discussed in further detail below, the selection circuit 400 includes a plurality of switches to selectively provide the operable voltage signal V _DD or the operable voltage signal V _DDM as the operable voltage signal V _{DDM_INT} . And as will be discussed in further detail below, the selection circuit 400 provides the maximum operable voltage signal V _DDMAX to the base (B) terminals of the transistors of the plurality of switches, so that the source (S) terminals and wells of the transistors are formed The parasitic diodes between the regions are reverse biased (ie, non-conductive) to prevent latch-up of these transistors. In some cases, the maximum operable voltage signal V _{DDMAX may fluctuate,} for example, in response to unwanted electromagnetic coupling and/or leakage between the well region of the transistor and the semiconductor substrate. In these cases, the selection circuit 400 can dynamically adjust the maximum operable voltage signal V _DDMAX to compensate for these fluctuations of the maximum operable voltage signal V _DDMAX , as will be discussed in further detail below. In the exemplary embodiment shown in FIG. 4, the selection circuit 400 includes a switch circuit 402 and a latch-up prevention circuit 404.

In the exemplary embodiment shown in FIG. 4, the switch circuit 402 selectively provides the operable voltage signal V _{DDM_INT from the operable voltage signal V DD} and the operable voltage signal V _DDM to control one of the memory devices Or multiple operating parameters. As shown in FIG. 4, the switch circuit 402 includes a p-type metal oxide semiconductor (PMOS) transistor P4 and a p-type metal oxide semiconductor (PMOS) transistor P5. As shown in FIG. 4, the PMOS transistor P4 and the PMOS transistor P5 selectively provide their corresponding operable voltage signal V _DDM and the operable voltage signal V _DD as the operable voltage signal V _{DDM_INT} . In an exemplary embodiment, the bias control signal 452 and the bias control signal 452 activate (ie, close) the PMOS transistor P4 and the PMOS transistor P5 when they are at the first logic level (such as the logic 0 provided in the example). The first transistor in the PMOS transistor and/or the second transistor in the PMOS transistor P4 and PMOS transistor P5 when it is at a second logic level (such as the logic 1 provided in the example). In this exemplary embodiment, the bias control signal 452 and the bias control signal 452 represent differential bias control signals, where the bias control signal 452 is a supplement to the bias control signal 452. In this exemplary embodiment, the PMOS transistor P4 and the PMOS transistor P5 selectively provide their corresponding operable voltage signal V _DDM and the operable voltage signal V _DD as the operable voltage signal V _{DDM_INT when activated} . Moreover, in this exemplary embodiment, PMOS transistor P4 and PMOS transistor P5 are selectively prohibited from providing their corresponding operable voltage signal V _DDM and operable voltage signal V _DD when blocking. In addition, the PMOS transistor P4 and PMOS transistor P5 as shown in FIG. 4 can be implemented to have a source (S) terminal, a drain (drain; D) terminal, a gate (gate; G) terminal, and a base. (B) End. As shown in FIG. 4, the source (S) terminal, the drain (D) terminal, and the base (B) terminal are formed in the well region of the semiconductor substrate. In the exemplary embodiment shown in FIG. 4, the switch circuit 402 can provide the maximum operable voltage signal V _DDMAX to the base (B) end of the PMOS transistor P4 and the PMOS transistor P5, so as to be formed in the PMOS The parasitic diode between the source (S) end of the transistor P4 and the PMOS transistor P5 and the n-well region is reverse biased (that is, non-conductive) to prevent latching of the PMOS transistor P4 and PMOS transistor Crystal P5.

In the exemplary embodiment shown in FIG. 4, the latch-up prevention circuit 404 can dynamically adjust the maximum operable voltage signal V _DDMAX to compensate for fluctuations in the maximum operable voltage signal V _DDMAX. These fluctuations can be caused by unwanted electromagnetic coupling and/or leakage between various regions of various transistors. As shown in FIG. 4, the latch-up prevention circuit 404 includes a p-type metal oxide semiconductor (PMOS) transistor P6 and a p-type metal oxide semiconductor (PMOS) transistor P7. In the exemplary embodiment shown in FIG. 4, PMOS transistor P6 and PMOS transistor P7 represent diode-connected transistors, which have their corresponding source (S) terminals coupled to their corresponding gates (G )end. During operation, the maximum operable voltage signal V _DDMAX is usually greater than or equal to the operable voltage signal V _DDM and the operable voltage signal V _DD . However, in some cases, the maximum operable voltage fluctuation signal V _DDMAX may be operable such that the maximum signal voltage V _DDMAX operable voltage signal is less than the operable voltage signal V _DDM and V _DD. In the exemplary embodiment shown in FIG. 4, the PMOS transistors P4 and P5 are characterized in that the threshold voltages of the transistors P4 and P5 are greater than the threshold voltages of the PMOS transistors P6 and P7. For example, the PMOS transistors P4 and P5 have a threshold voltage of about 0.7 volts, and the PMOS transistors P6 and P7 have a threshold voltage of about 0.2 volts. When these fluctuations cause the maximum operable voltage signal V _{DDMAX to be} less than the operable voltage signal V _DDM and the operable voltage signal V _DD , the threshold voltages of PMOS transistors P4 and P5 are between the threshold voltages of PMOS transistors P6 and P7 The difference causes the PMOS transistors P6 and P7 to start. Under these conditions, when the maximum operable voltage signal V _{DDMAX is} less than the operable voltage signal V _DDM and the operable voltage signal V _DD , PMOS transistor P6 and PMOS transistor P7 are activated by their corresponding threshold voltages (that is, closure). The PMOS transistor P6 obtains the current I _DD from the operable voltage signal V _DD at startup to adjust (ie, increase) the maximum operable voltage signal V _DDMAX . Similarly, the PMOS transistor P7 obtains the current I _{DDM from the operable voltage signal V DDM} at startup to adjust (ie, increase) the maximum operable voltage signal V _DDMAX . This adjustment of the maximum operable voltage signal V _DDMAX of the latch-up prevention circuit 404 ensures that the maximum operable voltage signal V _{DDMAX is} sufficient to prevent the transistors P5 to P7 from latching up.

Exemplary operation of an exemplary memory storage system

FIG. 5 shows a flowchart of an exemplary operation of an exemplary memory storage system according to an exemplary embodiment of the present disclosure. This disclosure is not limited to this operation description. As a matter of fact, it is obvious to a person with ordinary knowledge in the relevant technical field that other operable control processes are within the scope and spirit of this disclosure. The following discussion describes an exemplary operational process 500 of a memory storage system, such as the memory storage system 100 or the memory storage system 500 that provide examples.

At operation 502, the exemplary operable process 500 selects a maximum operable voltage signal from a plurality of operable voltage signals. In an exemplary embodiment, operation 502 may be performed by the voltage generator circuit 102 as described in FIG. 1 above.

At operation 504, the exemplary operable process 500 applies a maximum operable voltage signal, such as the maximum operable voltage signal V _DDMAX as described above, to at least one base of at least one transistor of the memory storage system (B) At the end, the memory storage system, such as the PMOS transistor P4, PMOS transistor P5, PMOS transistor P6, and PMOS transistor P7 as described in FIG. 4 above, and/or at least one circuit applied to the memory storage system At least one gate (G) terminal of the crystal, the memory storage system such as PMOS transistor P6 and PMOS transistor P7 as described in FIG. 4 above. In an exemplary embodiment, operation 504 may be performed by selecting circuits 104.1 to 104. x as described in FIG. 1 above, selecting circuits 200.1 to 200.m as described in FIG. 2A above, as described in FIG. 2B above The described selection circuits 220.1 to 200. n and/or the selection circuit 400 described above in FIG. 4 are executed.

At operation 506, when the maximum operable voltage signal fluctuates below the first operable voltage signal from the plurality of operable voltage signals, the exemplary operable process 500 adjusts (eg, increases) the maximum operable voltage signal. In an exemplary embodiment, operation 504 may be performed by selecting circuits 104.1 to 104. x as described in FIG. 1 above, selecting circuits 200.1 to 200.m as described in FIG. 2A above, as described in FIG. 2B above The described selection circuits 220.1 to 200. n and/or the selection circuit 400 described above in FIG. 4 are executed. In some cases, the maximum operable voltage signal may fluctuate. These fluctuations can be caused by unwanted electromagnetic coupling and/or leakage between various regions of various transistors of the memory storage system. The exemplary operable process 500 can obtain a current from the first operable voltage signal to increase the maximum operable voltage signal when the maximum operable voltage signal fluctuates below the first operable voltage signal.

in conclusion

The foregoing specific embodiments disclose that the operable voltage signal is selectively provided The selection circuit to the memory storage system. The selection circuit includes a switch circuit and a latch prevention circuit. The switch circuit with a plurality of transistors selects an operable voltage signal from the operable voltage signal. The maximum operable voltage signal among the operable voltage signals is selectively applied to the base terminal of the transistor. The latch-up prevention circuit dynamically adjusts the maximum operable voltage signal to compensate for fluctuations in the maximum operable voltage signal.

In the foregoing specific embodiments, the plurality of transistors include a first transistor and a second transistor. The first transistor is configured to selectively provide a first operable voltage signal from the plurality of operable voltage signals. The second transistor is configured to selectively provide a second operable voltage signal from the plurality of operable voltage signals. The maximum operable voltage signal is selectively applied to the first base terminal of the first transistor and the second base terminal of the second transistor.

In the foregoing specific embodiments, the first transistor and the second transistor include p-type metal oxide semiconductor (PMOS) transistors.

In the foregoing specific embodiments, the first transistor is configured to selectively provide the first operable voltage signal in response to the bias control signal being at the first logic level. The second transistor is configured to selectively provide the second operable voltage signal in response to the bias control signal being at a second logic level, the second logic level being different from the first logic level Bit.

In the foregoing specific embodiments, the latch-up prevention circuit includes a first diode connected to the transistor and a second diode connected to the transistor. The first diode-connected transistor and the second diode-connected transistor are respectively coupled to a first operable voltage signal and a second operable voltage signal among the plurality of operable voltage signals. The first diode connected to the transistor is set to obtain a first current from the first operable voltage signal when it is activated, so as to adjust the maximum operable voltage signal to compensate for the maximum The fluctuation of the voltage signal can be manipulated. The second diode connected to the transistor is configured to obtain a second current from the second operable voltage signal at startup to adjust the maximum operable voltage signal to compensate for the maximum operable voltage signal The fluctuations.

In the foregoing specific embodiments, the first threshold voltage of the first transistor and the second threshold voltage of the second transistor are greater than the third threshold voltage of the first diode connected to the transistor and The second diode is connected to the fourth threshold voltage of the transistor.

In the foregoing specific embodiment, when the maximum operable voltage signal is less than the first operable voltage signal, the first diode connection transistor is configured to connect to the electricity through the first diode. The third threshold voltage of the crystal is activated. When the maximum operable voltage signal is less than the second operable voltage signal, the second diode connected to the transistor is configured to connect to the fourth terminal of the transistor through the second diode. Limit voltage start.

The foregoing specific embodiments also disclose a selection circuit used in a memory storage system. The selection circuit includes a switch circuit and a latch prevention circuit. The switch circuit with a plurality of transistors provides an operable voltage signal selected from the plurality of operable voltage signals to the memory storage system. A latch-up prevention circuit having a first diode connected transistor and a second diode connected transistor applies a maximum operable voltage signal selected from a plurality of operable voltage signals to the first diode connected transistor The first base terminal and the second diode are connected to the second base terminal of the transistor. The first diode-connected transistor and the second diode-connected transistor are respectively coupled to the second operable voltage signal and the third operable voltage signal among the plurality of operable voltage signals. The first diode is connected to the transistor to obtain the first current from the second operable voltage signal when it is activated to adjust the second operable Voltage signal to compensate for fluctuations in the maximum operable voltage signal. The second diode-connected transistor obtains the second current from the third operable voltage signal when it is started, so as to adjust the second operable voltage signal, thereby compensating for the fluctuation of the maximum operable voltage signal.

In the foregoing specific embodiment, the latch-up prevention circuit is further configured to apply the maximum operable voltage signal to at least one base terminal of at least one transistor among the plurality of transistors.

In the foregoing specific embodiment, the second operable voltage signal is configured to reverse bias the parasitic diode located between the source terminal of the at least one transistor and the well region of the at least one transistor.

In the foregoing specific embodiments, the at least one transistor includes a p-type metal oxide semiconductor (PMOS) transistor. The maximum operable voltage signal is configured to reverse bias the parasitic diode located between the source terminal of the at least one transistor and the n-type well region of the at least one transistor.

In the foregoing specific embodiments, the first diode-connected transistor and the second diode-connected transistor include a diode-connected p-type metal oxide semiconductor (PMOS) transistor.

In the foregoing specific embodiment, the shutdown circuit is configured to selectively provide the maximum operable voltage signal as the operable voltage signal from the plurality of operable voltage signals, so as to reduce the power of the memory storage system Maximize the read/write speed, or selectively provide a minimum operable voltage signal from the plurality of operable voltage signals as the operable voltage signal, so as to minimize the power consumption of the memory storage system .

In the foregoing specific embodiments, the first diode-connected transistor includes a first source terminal coupled to the second operable voltage signal, and a first source terminal coupled to the maximum possible voltage signal. The first gate terminal of the operating voltage signal and the first drain terminal coupled to the maximum operable voltage signal. The second diode connected transistor includes a second source terminal coupled to the third operable voltage signal, a second gate terminal coupled to the maximum operable voltage signal, and a second gate terminal coupled to the maximum operable voltage signal. The second drain terminal of the voltage signal.

In the foregoing specific embodiment, the first transistor among the plurality of transistors is configured to selectively provide the maximum operable voltage signal as the operable voltage signal from the plurality of operable voltage signals. The second transistor among the plurality of transistors is configured to selectively provide a minimum operable voltage signal as the operable voltage signal from the plurality of operable voltage signals.

In the foregoing specific embodiments, the first transistor is configured to selectively provide the maximum operable voltage signal in response to the bias control signal being at the first logic level. The second transistor is configured to selectively provide the minimum operable voltage signal in response to the bias control signal being at a second logic level, the second logic level being different from the first logic level .

The foregoing specific embodiments further disclose a method for preventing latching of a memory storage system. The method applies a maximum operable voltage signal to at least one base region of at least one transistor of a memory storage system and to at least one gate region of at least one transistor, and when the maximum operable voltage signal is in a plurality of When the first operable voltage signal in the operable voltage signals fluctuates below, the maximum operable voltage signal is increased.

In the foregoing specific embodiment, the step of adding includes: when the maximum operable voltage signal fluctuates below the first operable voltage signal, obtaining a current from the first operable voltage signal to increase the Maximum operable voltage signal.

In the foregoing specific embodiments, the method for preventing a memory storage system from latching up further includes: selecting an operable voltage signal from the plurality of operable voltage signals by the memory storage system to dynamically control all the operating voltage signals. The operating parameters of the memory storage system are described.

In the foregoing specific embodiment, the step of selecting the operable voltage signal includes: selecting the maximum operable voltage signal from the plurality of operable voltage signals by the memory storage system to store the memory The read/write speed of the volume storage system is maximized, or the smallest operable voltage signal is selected from the plurality of operable voltage signals, so as to minimize the power consumption of the memory storage system.

The foregoing specific embodiments refer to the accompanying drawings to illustrate exemplary embodiments consistent with the present disclosure. The foregoing specific embodiments refer to the "exemplary embodiments" as reference indications. The described exemplary embodiments may include specific features, structures, or characteristics, but each exemplary embodiment may not necessarily include specific features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same exemplary embodiment. In addition, regardless of whether the features, structures, or characteristics of other exemplary embodiments are explicitly described, they may independently or in any combination include any of the features, structures, or characteristics described in combination with the exemplary embodiments.

The foregoing specific embodiments are not meant to be limiting. The fact is that the scope of this disclosure is only defined according to the scope of the following patent applications and their equivalents. It should be understood that the foregoing specific embodiments rather than the following abstract chapters are intended to interpret the scope of the patent application. The summary of the invention section may describe one or more but not all exemplary embodiments of the present disclosure, and therefore it is not intended to limit the present disclosure and the scope of the following patent applications and their equivalents in any way.

The exemplary embodiments described in the foregoing specific embodiments have been for illustration Is provided for the purpose and is not intended to be limiting. Other exemplary embodiments are possible, and may be modified while remaining within the spirit and scope of the present disclosure. The foregoing specific implementations have been described with the function building blocks used to describe implementations of specific functions and their relationships. For ease of description, this article has arbitrarily defined the boundaries of these functional building blocks. As long as the specified functions and their relationships are properly performed, alternative boundaries can be defined.

The embodiments of the present disclosure can be implemented by hardware, firmware, software, or any combination thereof. The embodiments of the present disclosure can also be implemented as instructions stored on a machine-readable medium that can be read and executed by one or more processors. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (for example, a computing circuit). For example, machine-readable media may include non-transitory machine-readable media, such as read-only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; and others media. As another example, machine-readable media may include transitory machine-readable media, such as electrical, optical, acoustic, or other forms of propagated signals (eg, carrier waves, infrared signals, digital signals, etc.). In addition, firmware, software, routines, and commands may be described herein as performing specific actions. However, it should be understood that such descriptions are only for convenience, and such actions are actually caused by computing devices, processors, controllers, or other devices that execute firmware, software, routines, commands, etc.

The foregoing specific implementations fully reveal the general nature of the disclosure: others can easily understand the general knowledge in the relevant technical field by application without departing from the spirit and scope of the disclosure and without excessive experimentation. Such exemplary embodiments are modified and/or adapted for various applications. Therefore, based on the teaching and guidance presented herein, it is intended that the meaning of these exemplary embodiments and the scope of multiple equivalents Make such adjustments and modifications within. It should be understood that the terms or terms in this article are for the purpose of description rather than limitation, so that the terms or terms in this specification should be interpreted by persons with ordinary knowledge in the relevant field in view of the teachings in this article.

100: Memory storage system

102: Voltage generator circuit

104.1, 104. x : Selection circuit

106: memory device

150: Bias control signal

152: Select control signal

V ₁ , V _{DDM_INT.1} , V _{DDM_INT. x} , V _m : operable voltage signal

V _DDMAX : Maximum operable voltage signal

Claims (9)

A selection circuit for selectively providing an operable voltage signal to a selection circuit of a memory storage system. The selection circuit includes: a switch circuit having a plurality of transistors, and is configured to select from a plurality of operable voltage signals Selecting the operable voltage signal, the largest operable voltage signal among the plurality of operable voltage signals is selectively applied to the base terminal of the plurality of transistors; and a latch-up prevention circuit including: a first two pole The body-connected transistor and the second diode-connected transistor, the first diode-connected transistor and the second diode-connected transistor are respectively coupled to the first of the plurality of operable voltage signals An operable voltage signal and a second operable voltage signal, wherein the first diode connected to the transistor is configured to obtain a first current from the first operable voltage signal at startup to adjust the maximum An operable voltage signal to compensate for the fluctuation of the maximum operable voltage signal, and wherein the second diode connection transistor is set to obtain a second operation voltage signal from the second operable voltage signal when activated. Current to adjust the maximum operable voltage signal to compensate for the fluctuation of the maximum operable voltage signal. The selection circuit according to claim 1, wherein the plurality of transistors include: a first transistor configured to selectively provide a first operable voltage signal from the plurality of operable voltage signals And a second transistor configured to selectively provide a second operable voltage signal from the plurality of operable voltage signals, The maximum operable voltage signal is selectively applied to the first base terminal of the first transistor and the second base terminal of the second transistor. The selection circuit according to item 1 of the scope of patent application, wherein the first threshold voltage of the first transistor and the second threshold voltage of the second transistor are greater than the first diode-connected transistor The third threshold voltage of and the fourth threshold voltage of the second diode connected to the transistor. The selection circuit described in item 3 of the scope of the patent application, wherein when the maximum operable voltage signal is less than the first operable voltage signal, the first diode connected transistor is configured to use the The third threshold voltage of the first diode connected to the transistor is activated, and wherein when the maximum operable voltage signal is less than the second operable voltage signal, the second diode is connected to the transistor via It is set to start by connecting the second diode to the fourth threshold voltage of the transistor. A selection circuit for a memory storage system, the selection circuit comprising: a switch circuit having a plurality of transistors, and is configured to provide an operable voltage signal selected from a plurality of operable voltage signals to the memory A storage system; and a latch-up prevention circuit, having a first diode connected transistor and a second diode connected transistor, set to apply a maximum operable voltage signal selected from the plurality of operable voltage signals The first base terminal of the transistor is connected to the first diode and the second base terminal of the transistor is connected to the second diode, wherein the first diode is connected to the transistor and the second diode The pole body connection transistor is respectively coupled to the second operable voltage signal and the third operable voltage signal among the plurality of operable voltage signals, The first diode connected to the transistor is configured to obtain a first current from the second operable voltage signal when it is activated, so as to adjust the second operable voltage signal to compensate for the maximum operable The fluctuation of the voltage signal, and wherein the second diode connected to the transistor is set to obtain a second current from the third operable voltage signal at startup to adjust the second operable voltage signal to Compensating for the fluctuation of the maximum operable voltage signal. The selection circuit according to claim 5, wherein the latch-up prevention circuit is further configured to apply the maximum operable voltage signal to at least one base of at least one of the plurality of transistors Terminal, wherein the second operable voltage signal is configured to reverse bias a parasitic diode located between the source terminal of the at least one transistor and the well region of the at least one transistor. The selection circuit according to item 5 of the scope of patent application, wherein the switch circuit is configured to selectively provide the maximum operable voltage signal as the operable voltage signal from the plurality of operable voltage signals, In order to maximize the read/write speed of the memory storage system, or selectively provide a minimum operable voltage signal from the plurality of operable voltage signals as the operable voltage signal, to convert the The power consumption of the memory storage system is minimized. The selection circuit according to claim 5, wherein the first transistor among the plurality of transistors is configured to selectively provide the maximum operable voltage signal from the plurality of operable voltage signals As the operable voltage signal, and wherein a second transistor among the plurality of transistors is configured to selectively provide a minimum operable voltage signal as the operable voltage from the plurality of operable voltage signals Signal. A method for preventing latch-up of a memory storage system, the method comprising: by the memory storage system, applying a maximum operable voltage signal selected from a plurality of operable voltage signals to the memory storage At least one base region of at least one transistor of the system and at least one gate region applied to the at least one transistor; and when the maximum operable voltage signal is the first among the plurality of operable voltage signals When the operable voltage signal fluctuates, the memory storage system obtains current from the first operable voltage signal to increase the maximum operable voltage signal.

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