TW202211626A - Latch-up prevention circuitry, selection circuitries and method for preventing latch-up - Google Patents

Abstract

Various embodiments of selection circuitries and a method for preventing latch-up of a memory storage system are disclosed. The selection circuitry selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the selection circuitry selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the selection circuitry selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption. Moreover, the selection circuitry selectively provide the maximum operational voltage signal to bulk (B) terminals of some of their transistors to prevent latch-up of these transistors. In some situations, the selection circuitry can dynamically adjust the maximum operational voltage signal to compensate for fluctuations in the maximum operational voltage signal.

Description

Latch-up prevention circuit, selection circuit, and method for latch-up prevention

The present disclosure relates to a selection circuit and method for preventing latch-up in a memory storage system.

Memory storage systems are electronic devices used to read and/or write electronic data. Memory storage systems include arrays of memory cells that can be implemented as volatile memory cells that require power to maintain the information they store, such as random-access memory (RAM) cells, Or a non-volatile memory cell such as a read-only memory (ROM) cell that maintains its stored information even when no power is supplied. Electronic data can be read and/or written into an array of memory cells that can be accessed through various control lines. The two basic operations performed by a memory device are " reading " and " writing ." In reading, electronic data stored in the memory cell array is read, and in writing, electronic data is written. in memory cell arrays.

The selection circuit of the present disclosure is used to selectively provide an operable voltage signal to the selection circuit of the memory storage system. The selection circuit includes a switch circuit and a latch-up prevention circuit. The switching circuit has a plurality of transistors. The switch circuit is configured to select an operable voltage signal from among a plurality of operable voltage signals, a maximum operable voltage signal among the plurality of operable voltage signals selectively applied to the base terminals of the plurality of transistors. The latch-up prevention circuit is configured to dynamically adjust the maximum operable voltage signal to compensate for fluctuations in the maximum operable voltage signal.

Another selection circuit of the present disclosure is used in a memory storage system. The selection circuit includes a switch circuit and a latch-up prevention circuit. The switching circuit has a plurality of transistors. The switch circuit is configured to provide an operable voltage signal selected from a plurality of operable voltage signals to the memory storage system. The latch-up prevention circuit has a first diode-connected transistor and a second diode-connected transistor. The latch-up prevention circuit is configured to apply a maximum operable voltage signal selected from the plurality of operable voltage signals to the first base terminal of the first diode-connected transistor and the second diode-connected transistor The second base extreme. The first diode-connected transistor is configured to obtain a first current from the first operable voltage signal at startup to adjust the maximum operable voltage signal to compensate for fluctuations in the maximum operable voltage signal. The second diode-connected transistor is configured to obtain a second current from the second operable voltage signal at startup to adjust the maximum operable voltage signal to compensate for fluctuations in the maximum operable voltage signal.

The method for preventing latch-up of a memory storage system of the present disclosure includes applying, by the memory storage system, a maximum operable voltage signal selected from a plurality of operable voltage signals to at least one transistor of the memory storage system at least one base region of and applied to at least one gate region of at least one transistor; and when the maximum operable voltage signal fluctuates below a first operable voltage signal among the plurality of operable voltage signals, by The memory storage system increases the maximum operable voltage signal.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these components and configurations are examples only and are not intended to be limiting. For example, in the following description, the formation of a first feature over a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include additional features that may be formed between the first feature and the second feature. Embodiments where the features are formed such that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in various instances. This repetition by itself does not indicate the relationship between the various embodiments and arrangements described.

Overview

The present disclosure discloses various embodiments of configurable memory storage systems. The configurable memory storage selectively selects an operable voltage signal from a plurality of operable voltage signals to dynamically control various operating parameters. For example, a memory storage system may be configured to selectively select a maximum operable voltage signal from a plurality of operable voltage signals to maximize read/write speed. As another example, the memory storage system may be configured to selectively select the smallest operable voltage signal from a plurality of operable voltage signals to minimize power consumption. Additionally, the memory storage system may be configured to selectively provide a maximum operable voltage signal to the bulk (B) terminals of some of its transistors to prevent latch-up of these transistors. In some cases, the memory storage system may be configured to dynamically adjust the maximum operable voltage signal to compensate for fluctuations in the maximum operable voltage signal.

Exemplary memory storage system

FIG. 1 shows a block diagram of an exemplary memory storage system according to an exemplary embodiment of the present disclosure. In the exemplary embodiment shown in FIG. 1, the memory storage system 100 selectively selects between a plurality of operable voltage signals to dynamically control operation. For example, the memory storage system 100 may select an operational voltage signal from a plurality of operational voltage signals to set the memory storage system 100 to dynamically control (eg, minimize or maximize) the plurality of voltages from the memory storage system 100 one or more of the operating parameters, such as power consumption and/or read/write speed. As shown in FIG. 1, the memory storage system 100 includes a voltage generator circuit 102, selection circuits 104.1~ 104.x , and a memory device 106.

The voltage generator circuit 102 selectively provides the maximum operable voltage signal V _DDMAX to the selection circuits 104.1~ 104.x from the operable voltage signal V ₁ to the operable voltage signal V _m according to the bias control signal 150 . For example, the maximum operable voltage signal V _DDMAX may represent the maximum operable voltage signal among the operable voltage signals V ₁ ˜V _m . In some cases, the maximum operable voltage signal among the operable voltage signals V ₁ ˜V _m is known empirically. In an exemplary embodiment, the voltage generator circuit 102 includes a plurality of switches to selectively provide the maximum operable voltage signal from the operable voltage signals V ₁ -V _m as the maximum operable voltage signal V _DDMAX . In this exemplary embodiment, the bias control signal 150 includes one or more control bits, wherein various combinations of the one or more control bits correspond to various operable voltages among the operable voltage signals V ₁ -V _m Signal. In this exemplary embodiment, the bias control signal 150 can be set to a combination of control bits corresponding to the maximum operable voltage signal among the operable voltage signals V ₁ -V _m to set the voltage generator circuit 102 from operable Among the operating voltage signals V ₁ ˜V _m , the maximum operable voltage signal is selectively provided to the selection circuits 104.1 ˜ 104. x as the maximum operable voltage signal V _DDMAX . In this exemplary embodiment, this combination of control bits activates (ie, closes) one or more of the plurality of switches to provide the maximum operable voltage signal from the operable voltage signals V ₁ -V _m As the maximum operable voltage signal V _DDMAX , the remaining switches among the plurality of switches are simultaneously blocked (ie, opened).

In the exemplary embodiment shown in FIG. 1 , the selection circuits 104.1˜104.x selectively provide _one of the operable voltage signals V 1˜V _m as the operable voltage signal in response to the selection control signal 152 _{VDDM_INT.1} ~ _{VDDM_INT.x} to control one or more operating parameters of the memory device 106 . The selection control signal 152 can be set to various combinations of one or more control bits to selectively provide one of the operable voltage signals V ₁ -V _m as the operable voltage signals V _{DDM_INT.1} -V _{DDM_INT.x} , to dynamically control various operating parameters of the memory device 106 . For example, one or more control bits can be set as the first bit combination to select the minimum operable voltage signal from the operable voltage signals V ₁ -V _m to dynamically control (eg, minimize) the memory Power consumption of device 106 . In this example, the minimum operable voltage signal results in less unwanted leakage in the various transistors of the memory device 106 when compared to other operable voltage signals in the operable voltage signals V ₁ -V _m . As another example, one or more control bits may be set to a second combination of bits to select a maximum operable voltage signal from the operable voltage signals V ₁ -V _m to dynamically control (eg, maximize) memory read/write speed of the bulk device 106 . In some cases, selection control signal 152 may be toggled during operation of memory storage system 100 to dynamically set memory device 106 in operation to control one or more operating parameters. In this other example, the maximum operable voltage signal may cause the various transistors of the memory cells of memory device 106 to operate faster when compared to other operable voltage signals among the operable voltage signals V ₁ -V _m rate off and/or on. As another example, the select control signal 152 may be set to a second bit combination to maximize the read/write speed of the memory device 106 and dynamically reset to a different bit combination during operation, thereby reducing memory read/write speed of the bulk device 106 .

In an exemplary embodiment, the selection circuits 104.1 - 104.x include a plurality of switches to selectively provide one of the operable voltage signals V ₁ -V _m as the operable voltage signals V _{DDM_INT.1} -V _{DDM_INT.x} . In this exemplary embodiment, the selection control signal 152 includes one or more control bits, wherein various combinations of the one or more control bits correspond to various operable voltage signals among the operable voltage signals V ₁ -V _m . In this exemplary embodiment, the selection control signal 152 can be set as a combination of control bits corresponding to the maximum operable voltage signal among the operable voltage signals V ₁ ˜V _m to set the selection circuits 104.1 ˜ 104. x , The maximum operable voltage signals from the operable voltage signals V ₁ ˜V _m are selectively provided to the memory device as the operable voltage signals V ₁ ˜V _m as the operable voltage signals V _{DDM_INT.1 ˜V DDM_INT.x} . 106. In this exemplary embodiment, this combination of control bits activates (ie, closes) one or more switches from among the plurality of switches to provide the maximum operable voltage signal from among the operable voltage signals V ₁ -V _m and is the maximum operable voltage signal V _DDMAX , while blocking (ie, opening) the remaining switches of the plurality of switches. In this exemplary embodiment, the plurality of switches may be implemented using transistors, such as p-type metal-oxide-semiconductor (PMOS) transistors, which have transistors formed on a semiconductor substrate. The source terminal, drain terminal, gate terminal and base (B) terminal in the well area. As will be described in further detail below, the selection circuits _{104.1-104.x provide the maximum operable voltage signal V DDMAX} from the voltage generator circuit 102 to the base (B) terminals of the transistors such that the sources formed in these transistors The parasitic diode between the (source; S) terminal and the well region is reverse biased, ie, non-conductive, to prevent latch-up of these transistors. In some cases, the maximum operable voltage signal V _DDMAX may fluctuate, eg, in response to unwanted electromagnetic coupling and/or leakage between the well region of the transistor and the semiconductor substrate. Under these circumstances, selection circuits 104.1-104.x may dynamically adjust the maximum operable voltage signal V _DDMAX to compensate for these fluctuations in the maximum operable voltage signal V _DDMAX , as will be discussed in further detail below.

The memory device 106 receives operable voltage signals V DDM_INT.1 ˜V _{DDM_INT.x} selectively selected from the operable voltage signals V _{1 ˜V m} . In the exemplary embodiment shown in FIG. 1, memory device 106 includes memory cells configured in an array of m rows and n columns. In this exemplary embodiment, memory device 106 provides each of the operational voltage signals V _{DDM_INT.1} -V _{DDM_INT.x} to m rows of a memory array as will be discussed in further detail in FIG. 2A below Corresponding rows among and/or are provided to corresponding columns among n columns of a memory cell array as will be discussed in further detail in FIG. 2B below.

Exemplary Memory Devices That Can Be Implemented within Exemplary Memory Storage Systems

2A shows a block diagram of a first exemplary memory device that may be implemented within an exemplary memory storage system according to exemplary embodiments of the present disclosure. In the exemplary embodiment shown in FIG. 2A, selection circuits 200.1-200.m are selectively operable in a manner substantially similar to selection circuits 104.1-104.x as described above in FIG. 1 The voltage signals V _{DDM_INT.1} ~ V _{DDM_INT.m} are used to set the operation of the memory device 202 . Memory device 202 may represent an exemplary embodiment of memory device 106 as described above in FIG. 1 . In an exemplary embodiment, the selection circuits 200.1˜200.m selectively provide the first operable voltage signal from the plurality of operable voltage signals as the operable voltage signals V _{DDM_INT.1˜V DDM_INT.m to} set the memory The memory device 202 dynamically controls (eg, minimizes) one or more of a plurality of operating parameters of the memory device 202 , such as power consumption and/or read/write speed. As another example, selection circuits 200.1-200.m selectively provide a second operable voltage signal from a plurality of operable voltage signals to configure memory device 202 to dynamically control (eg, maximize) memory device 202 one or more operating parameters.

In the exemplary embodiment shown in FIG. 2A , memory device 202 includes memory array 204 . Although not shown in FIG. 2A, memory device 202 may include other electronic circuits, such as sense amplifiers, column address decoders, and/or row address decoders to provide some examples, without departing from the spirit of the present disclosure and scope will be apparent to those of ordinary skill in the relevant technical fields. As shown in FIG. 2A, memory array 204 includes memory cells 210.1.1 ~ 10.m.n arranged and configured into an array of m rows and n columns. However, other configurations of the memory cells 210.1.1-210.m.n may not depart from the spirit and scope of the present disclosure. In the exemplary embodiment shown in FIG. 2A, memory cells 210.1.1 ~ 210.m.n are connected to corresponding wordlines (WL) and bits among wordlines 212.1~ 212.n Corresponding bit line (bitline; BL) among line 214.1~bit line 214.m. Wordlines 212.1 through 212.n and/or bitlines 214.1 through 214.m may be used to read electronic data stored in memory array 204 in a " read " mode of operation and/or in a " write " mode of operation The " Enter " mode of operation writes electronic data to the memory array 204. The " read " mode of operation and the " write " mode of operation represent conventional read and write operations and will not be described in further detail.

As shown in FIG. 2A, the selection circuits 200.1~ 200.m selectively provide the operable voltage signals V _{DDM_INT.1} ~V _{DDM_INT.m to m} of the memory cells 210.1.1 ~ 210.m.n One or more corresponding rows of a row. For example, the selection circuit 200.1 selectively provides the operable voltage signal V _{DDM_INT.1} to the first row of the memory cells 210.1.1 ~210.1.n, and the selection circuit 200.m supplies the operable voltage signal V _{DDM_INT. m} is selectively provided to the m - th row of the memory cells 210.m.1 ~ 210.m.n Although not shown in FIG. 2A, each of the selection circuits 200.1~ 200.m may convert the operable voltage signal Its corresponding operable voltage signal among _{VDDM_INT.1˜V DDM_INT.m} is selectively provided to more than one row among m rows of memory cells 210.1.1˜210.m.n . In an exemplary embodiment, the memory cells 210.m.1 ~ 210.m.n may be implemented using one or more transistors, such as one or more p -type metal oxide semiconductor (PMOS) transistors A crystal, one or more n-type metal-oxide-semiconductor (NMOS) transistors, or any combination of PMOS transistors and NMOS transistors, without departing from the spirit and scope of the present disclosure It will be apparent to those of ordinary skill in the relevant technical field. In this exemplary embodiment, the selection circuits 200.1~ 200.m may selectively provide the operable voltage signals V _{DDM_INT.1} ~V DDM_INT.m to _m of the memory cells 210.1.1 ~ 210.m.n The base (B) terminal of the transistor in the row which corresponds to the row. The operational voltage signals V _{DDM_INT.1} ~ V _{DDM_INT.m are} effective to reverse bias the parasitic diodes formed between the source (S) terminals and the well region of these transistors in this example (ie, non- conductive) to prevent latch-up, as will be discussed in further detail in Figure 3 below.

2B shows a block diagram of a second exemplary memory device that may be implemented within an exemplary memory storage system according to exemplary embodiments of the present disclosure. In the exemplary embodiment shown in FIG. 2B, selection circuits 220.1-220.n are selectively operable in a manner substantially similar to selection circuits 104.1-104.x as described above in FIG. 1 The voltage signals V _{DDM_INT.1} ~V _{DDM_INT.n} are used to configure the operation of the memory device 222 . Memory device 222 may represent an exemplary embodiment of memory device 106 as described above in FIG. 1 . In an exemplary embodiment, the selection circuits 220.1~ _220.n selectively provide the first operable voltage signal as the operable voltage signal V _{DDM_INT.1} ~V DDM_INT.n from the plurality of operable voltage signals to set the memory The memory device 222 dynamically controls (eg, minimizes) one or more of a plurality of operating parameters of the memory device 222 , such as power consumption and/or read/write speed. As another example, selection circuits 220.1-220.n selectively provide a second operable voltage signal from a plurality of operable voltage signals to configure memory device 222 to dynamically control (eg, maximize) memory device 222 one or more operating parameters.

In the exemplary embodiment shown in FIG. 2B , memory device 222 includes memory array 224 . Although not shown in FIG. 2B, memory device 222 may include other electronic circuits, such as sense amplifiers, column address decoders, and/or row address decoders to provide some examples, without departing from the spirit and scope of the present disclosure , it will be apparent to those of ordinary skill in the relevant technical field. As shown in FIG. 2B, memory array 224 includes memory cells 226.1.1 ~ 226.m.n arranged and arranged into an array of m rows and n columns. However, other configurations of memory cells 226.1.1 ~ 226.m.n may not depart from the spirit and scope of the present disclosure. In the exemplary embodiment shown in Figure 2B, memory cells 226.1.1 ~ 226.m.n are connected to corresponding wordlines (WL) and bit lines 214.1 among wordlines 212.1~ 212.n ~The corresponding bit line (BL) among the bit lines 214.m.

As shown in FIG. 2B, selection circuits 220.1~ 220.m selectively provide operable voltage signals V _{DDM_INT.1} ~V _{DDM_INT.n} to n columns among memory cells 226.1.1 ~ 226.m.n one or more corresponding columns of . For example, the selection circuit 220.1 selectively provides the operable voltage signal V _{DDM_INT.1} to the first column of memory cells 226.1.1~226.m.1, and the selection circuit 220.n supplies the operable voltage signal V _{DDM_INT .n} is selectively provided to the nth column of memory cells 226.1.n ~ 226.m.n . Although not shown in FIG. 2B, each of the selection circuits 220.1-220.m can selectively provide its corresponding operable voltage signal among the operable voltage signals V _{DDM_INT.1} -V _{DDM_INT.n} to the memory More than one of the n columns of cells 226.1.1 ~ 226.m.n . In an exemplary embodiment, memory cells 226.m.1 ~ 226.m.n may be implemented using one or more transistors, such as one or more p -type metal oxide semiconductor (PMOS) transistors A crystal, one or more n-type metal oxide semiconductor (NMOS) transistors, or any combination of PMOS transistors and NMOS transistors, will be of great value to those skilled in the related art without departing from the spirit and scope of the present disclosure. Usually the knowledgeable is obvious. In this exemplary embodiment, the selection circuits 220.1~ 220.n may selectively provide the operable voltage signals V _{DDM_INT.1} ~V _{DDM_INT.n} to m of the memory cells 226.1.1 ~ 226.m.n The base (B) terminal of the transistor in the row which corresponds to the row. The operable voltage signals V _{DDM_INT.1} ~ V _{DDM_INT.n are} active such that parasitic diodes formed between the source (S) terminals and the well region of these transistors of the example are reverse biased (ie, not conductive) to prevent latch-up of these transistors, as will be discussed in further detail in Figure 3 below.

Exemplary Memory Cells That Can Be Implemented in Exemplary Memory Devices

As described above in FIGS. 1 , 2A, and 2B, exemplary memory devices described therein, such as memory device 106 as described in FIG. 1 above, as described in FIG. 2A above, provide some examples Memory device 202 and/or memory device 222 as described above in Figure 2B, comprising an array of memory cells such as memory cell 210.1.1 as described above in Figure 2A to provide some examples ~ 210.m.n and/or memory cells 226.1.1 ~ 226.m.n as described above in FIG. 2B . The following discussion of FIG. 3 describes various embodiments of these memory cells. However, those of ordinary skill in the relevant art will recognize that the teachings of the various embodiments of these memory cells, which will be described below, may be readily modified for any suitable use without departing from the spirit and scope of the present disclosure. volatile memory cells, such as any random access memory (RAM) cells, and/or any suitable non-volatile memory cells, such as any read only memory (ROM) cells. RAM cells may be implemented as dynamic random-access memory (DRAM) cells, static random-access memory (SRAM) cells, and/or non-volatile random-access memory (non-volatile random-access) memory; NVRAM) units, such as flash memory cells that provide instances. A ROM unit may be implemented as a programmable read-only memory (PROM) unit, a one-time programmable ROM (OTP) unit, an erasable programmable An erasable programmable read-only memory (EPROM) unit and/or an electrically erasable programmable read-only memory (EEPROM) unit.

3 shows a block diagram of an exemplary static random access memory (SRAM) cell that may be implemented within an exemplary memory device in accordance with exemplary embodiments of the present disclosure. In the exemplary embodiment shown in Figure 3, SRAM cell 300 may be used to implement one or more memory cells of memory device 106 as described above in Figure 1, memory as described above in Figure 2A one or more of memory cells 210.1.1-210.m.n of memory device 202 and / or memory cells 226.1.1-226.m.n of memory device 222 as described above in FIG. 2B one or more of. As shown in FIG. 3 , the SRAM cell 300 includes p-type metal-oxide-semiconductor (PMOS) transistors P1 and p-type metal-oxide-semiconductor transistors P2 and n-type metal-oxide-semiconductor (NMOS) transistors N1 ˜ N4 .

In the exemplary embodiment shown in FIG. 3, PMOS transistor P1 and NMOS transistor N1 are configured to form a first logic inverter (INVERTER) gate, and PMOS transistor P2 and NMOS transistor N2 are configured to form a second logic inverter gate. The first logic inverter gate is cross-coupled with the second logic inverter gate as shown in FIG. 3 . For example, the input of the first logic inverter gate is coupled to the output of the second logic inverter gate, and the output of the first logic inverter gate is coupled to the second logic inverter gate input of. In this cross-coupled arrangement, the first logic inverter and the second logic inverter cooperate functionally to enhance the information stored in the SRAM cell 300 .

In the exemplary embodiment shown in FIG. 3, the information stored in the gate of the first logic inverter and the gate of the second logic inverter is between logical zero and logical one Cyclic transitions between, such as the operational voltage signal V _{DDM_INT .} In an exemplary embodiment, the operable voltage signal V _{DDM_INT} represents one of the operable voltage signals V _{DDM_INT.1} ~ V _{DDM_INT.x} as described above in FIG. 1 , operable as described in FIG. 2A above An exemplary embodiment of one of the voltage signals V _{DDM_INT.1} ~ V _{DDM_INT.m} and/or one of the operable voltage signals V _{DDM_INT.1} ~ V _{DDM_INT.n} as described above in FIG. 2B . In another exemplary embodiment, the first logic inverter and the second logic inverter receive an operational voltage signal V _{DDM_INT} from a selection circuit, such as described above in FIG. 1 to provide some examples One of selection circuits 104.1-104.x , one of selection circuits 200.1-200.m as described above in FIG. 2A, and/or among selection circuits 220.1-220.n as described in FIG. 2B above one of.

During a " read " operation, NMOS transistor N3 and NMOS transistor N4 are enabled by assert word line (WL) 350 . This activation of NMOS transistor N3 and NMOS transistor N4 couples the first and second logic inverters to bit line (BL) 352 . In an exemplary embodiment, word line 350 may represent one of word line 212.1˜word line 212.n as described in FIGS. 2A and 2B above, and bit line 352 may represent one of word lines 212.1 through 212.n as described in FIGS. 2A and 2B above One of the bit line 214.1~bit line 214.m described in 2B. Thereafter, the data stored in the first logical inverter and the second logical inverter are passed on to the bit line (BL) 352 . Similarly, during a " write " operation, NMOS transistor N3 and NMOS transistor N4 are enabled by assert word line 350 to couple the first and second logic inverters to the bit line 352. Thereafter, the state of the bit line 352 is transmitted to the first logic inverter and the second logic inverter to be stored as information in the first logic inverter and the second logic inverter.

Furthermore, as shown in FIG. 3 , the operable voltage signal V _{DDM_INT is} coupled to the first base (B) terminal of the PMOS transistor P1 and the second base (B) terminal of the PMOS transistor P2 . In the exemplary embodiment shown in FIG. 3, PMOS transistor P1 is located in a first n-type well region within a p-type semiconductor substrate, and PMOS transistor P2 is located in a second n-type well region within the p-type semiconductor substrate area. In this exemplary embodiment, the operable voltage signal V _{DDM_INT} transfers charge from the base (B) terminal of PMOS transistor P1 and the base (B) terminal of PMOS transistor P2 to the first n-type well region and the The second n-type well region.

Exemplary Select Circuits within Exemplary Memory Storage Systems

As described above in FIG. 1, selection circuits 104.1-104.x selectively provide one of operable voltage signals V1 _{-Vm as operable voltage signals V DDM_INT.1 -} V _{DDM_INT.x to} control memory one or more operating parameters of the body device 106 . The following discussion of FIG. 4 describes an exemplary embodiment of one of the selection circuits 104.1-104.x .

4 shows a block diagram of an exemplary select circuit that may be implemented within an exemplary memory device in accordance with exemplary embodiments of the present disclosure. In the exemplary embodiment shown in FIG. 4, the selection circuit 400 selectively provides the operable voltage signal V _{DDM_INT} from the operable voltage signal V _DD and the operable voltage signal V _DDM to control one of the memory devices or more operating parameters of a memory device such as memory device 106 providing an example. In an exemplary embodiment, the operable voltage signal V _DDM and the operable voltage signal V _DD may represent exemplary embodiments of both of the operable voltage signals V ₁ -V _m as described above in FIG. 1 . In another exemplary embodiment, the operable voltage signal V _DD corresponds to an operable voltage signal assigned to other digital circuits communicatively coupled to the memory device, and the operable voltage signal V _DDM corresponds to an operable voltage signal assigned to the memory device The operational voltage signal of the body device. In some cases, the operational voltage signal V _DD is greater than the operational voltage signal V _DDM ; however, in other cases, the operational voltage signal V _DD may be smaller than the operational voltage signal V _DDM . In the exemplary embodiment shown in FIG. 4 , the selection circuit 400 selects the operable voltage signal V _DDM and the greater of the operable voltage signal V _DD as the operable voltage signal V _{DDM_INT} to select the memory device 106 The read/write speed of the corresponding row memory cells as described above in FIG. 2A and/or the corresponding column memory cells as described above in FIG. 2B is maximized. Otherwise, the selection circuit 400 selects the lower one of the operable voltage signal V _DDM and the operable voltage signal V _DD as the operable voltage signal V _{DDM_INT} to store the corresponding row memory cells and/or the corresponding column memory cells of the memory device 106 The power consumption of the bulk unit is minimized.

In addition, as will be discussed in further detail below, the selection circuit 400 includes a plurality of switches to selectively provide the operable voltage signal V _DD or the operable voltage signal V _DDM as the operable voltage signal V _{DDM_INT} . And as will be discussed in further detail below, the selection circuit 400 provides the maximum operable voltage signal V _DDMAX to the base (B) terminals of transistors of a plurality of switches such that the source (S) terminals and wells of the transistors are formed The parasitic diodes between the regions are reverse biased (ie, non-conductive) to prevent latch-up of these transistors. In some cases, the maximum operable voltage signal V _DDMAX may fluctuate, eg, in response to unwanted electromagnetic coupling and/or leakage between the well region of the transistor and the semiconductor substrate. Under these circumstances, the selection circuit 400 may dynamically adjust the maximum operable voltage signal V _DDMAX to compensate for these fluctuations in the maximum operable voltage signal V _DDMAX , as will be discussed in further detail below. In the exemplary embodiment shown in FIG. 4 , selection circuit 400 includes switch circuit 402 and latch-up prevention circuit 404 .

在處於第一邏輯準位（諸如提供實例的邏輯0）時啟動（亦即，閉合）PMOS電晶體P4及PMOS電晶體P5中的第一電晶體，及/或在處於第二邏輯準位（諸如提供實例的邏輯1）時阻斷（亦即開路）PMOS電晶體P4及PMOS電晶體P5中的第二電晶體。在此例示性實施例中,偏壓控制信號452及偏壓控制信號

表示差分偏壓控制信號，其中偏壓控制信號452為偏壓控制信號

的補充。在此例示性實施例中，PMOS電晶體P4及PMOS電晶體P5在啟動時選擇性地提供其對應可操作電壓信號V_DDM 及可操作電壓信號V_DD 作為可操作電壓信號V_{DDM_INT} 。並且，在此例示性實施例中，在阻斷時選擇性地禁止PMOS電晶體P4及PMOS電晶體P5提供其對應可操作電壓信號V_DDM 及可操作電壓信號V_DD 。此外，如圖4中所示出的PMOS電晶體P4及PMOS電晶體P5可實施為具有源極（S）端、汲極（drain；D）端、閘極（gate；G）端以及基極（B）端。如圖4中所示出，源極（S）端、汲極（D）端、基極（B）端形成於半導體基底的井區內。在圖4中所示出的例示性實施例中，開關電路402可將最大可操作電壓信號V_DDMAX 提供至PMOS電晶體P4及PMOS電晶體P5的基極（B）端，以使得形成於PMOS電晶體P4及PMOS電晶體P5的源極（S）端與n型井區之間的寄生二極體反向偏置（亦即，非導電），以防止閂鎖PMOS電晶體P4及PMOS電晶體P5。In the exemplary embodiment shown in FIG. 4, the switch circuit 402 selectively provides the operable voltage signal V _{DDM_INT} from the operable voltage signal V _DD and the operable voltage signal V _DDM to control one of the memory devices or more operational parameters. As shown in FIG. 4, the switch circuit 402 includes a p-type metal oxide semiconductor (PMOS) transistor P4 and a p-type metal oxide semiconductor transistor P5. As shown in FIG. 4 , PMOS transistor P4 and PMOS transistor P5 selectively provide their corresponding operable voltage signal V _DDM and operable voltage signal V _DD as operable voltage signal V _{DDM_INT} . In the exemplary embodiment, the bias control signal 452 and the bias control signal

A first of PMOS transistor P4 and PMOS transistor P5 is enabled (ie, closed) at a first logic level (such as logic 0 providing an example), and/or at a second logic level ( A second one of PMOS transistor P4 and PMOS transistor P5 is blocked (ie, open circuited), such as logic 1) of the example provided. In this exemplary embodiment, the bias control signal 452 and the bias control signal

represents the differential bias control signal, wherein the bias control signal 452 is the bias control signal

supplement. In this exemplary embodiment, PMOS transistor P4 and PMOS transistor P5 selectively provide their corresponding operable voltage signal V _DDM and operable voltage signal V _DD as operable voltage signal V _{DDM_INT} at startup. Also, in this exemplary embodiment, PMOS transistor P4 and PMOS transistor P5 are selectively disabled from providing their corresponding operable voltage signal V _DDM and operable voltage signal V _DD when blocked. Furthermore, PMOS transistor P4 and PMOS transistor P5 as shown in FIG. 4 may be implemented with a source (S) terminal, a drain (Drain; D) terminal, a gate (gate; G) terminal, and a base (B) End. As shown in FIG. 4, a source (S) terminal, a drain (D) terminal, and a base (B) terminal are formed in the well region of the semiconductor substrate. In the exemplary embodiment shown in FIG. 4, the switch circuit 402 may provide the maximum operable voltage signal V _DDMAX to the base (B) terminals of PMOS transistor P4 and PMOS transistor P5 such that the The parasitic diodes between the source (S) terminals of transistors P4 and PMOS transistors P5 and the n-type well region are reverse biased (ie, non-conductive) to prevent latch-up of PMOS transistors P4 and PMOS transistors. Crystal P5.

In the exemplary embodiment shown in FIG. 4 , the latch-up prevention circuit 404 may dynamically adjust the maximum operable voltage signal V _DDMAX to compensate for fluctuations in the maximum operable voltage signal V _DDMAX . These fluctuations can be caused by unwanted electromagnetic coupling and/or leakage between various regions of the various transistors. As shown in FIG. 4, the latch-up prevention circuit 404 includes a p-type metal oxide semiconductor (PMOS) transistor P6 and a p-type metal oxide semiconductor transistor P7. In the exemplary embodiment shown in FIG. 4, PMOS transistor P6 and PMOS transistor P7 represent diode-connected transistors with their corresponding source (S) terminals coupled to their corresponding gate (G) terminals )end. During operation, the maximum operable voltage signal V _DDMAX is typically greater than or equal to the operable voltage signal V _DDM and the operable voltage signal V _DD . However, in some cases, fluctuations in the maximum operational voltage signal V _DDMAX may cause the maximum operational voltage signal V _{DDMAX to be} smaller than the operational voltage signal V _DDM and the operational voltage signal V _DD . In the exemplary embodiment shown in Figure 4, the PMOS transistors P4, P5 are characterized in that the threshold voltage of the transistors P4, P5 is greater than the threshold voltage of the PMOS transistors P6, P7. For example, PMOS transistors P4 and P5 have a threshold voltage of about 0.7 volts, and PMOS transistors P6 and P7 have a threshold voltage of about 0.2 volts. When these fluctuations cause the maximum operable voltage signal V _DDMAX to be smaller than the operable voltage signal V _DDM and the operable voltage signal V _DD , the difference between the threshold voltages of the PMOS transistors P4, P5 and the threshold voltages of the PMOS transistors P6, P7 The difference makes the PMOS transistors P6 and P7 start up. In these cases, when the maximum operable voltage signal V _DDMAX is less than the operable voltage signal V _DDM and the operable voltage signal V _DD , PMOS transistor P6 and PMOS transistor P7 are activated by their corresponding threshold voltages (ie, closure). PMOS transistor P6 draws current _IDD from operable voltage signal V _DD at startup to adjust (ie, increase) maximum operable voltage signal V _DDMAX . Similarly, PMOS transistor P7 draws current _IDDM from the operable voltage signal V _DDM at startup to adjust (ie, increase) the maximum operable voltage signal V _DDMAX . This adjustment of the maximum operable voltage signal V _DDMAX by the latch-up prevention circuit 404 ensures that the maximum operable voltage signal V _DDMAX is sufficient to prevent latch-up of transistors P5-P7.

Exemplary Operation of an Exemplary Memory Storage System

5 shows a flow diagram of an exemplary operation of an exemplary memory storage system in accordance with an exemplary embodiment of the present disclosure. The present disclosure is not limited to this operational description. Rather, other operable control flows are within the scope and spirit of the present disclosure, as will be apparent to those of ordinary skill in the relevant art. The following discussion describes an exemplary operational flow 500 of a memory storage system, such as memory storage system 100 or memory storage system 500, providing examples.

At operation 502, the exemplary operational flow 500 selects a maximum operational voltage signal from a plurality of operational voltage signals. In an exemplary embodiment, operation 502 may be performed by voltage generator circuit 102 as described above in FIG. 1 .

At operation 504, the exemplary operational flow 500 applies a maximum operable voltage signal, such as the maximum operable voltage signal V _DDMAX as described above, to at least one base (B) of at least one transistor of the memory storage system side, the memory storage system such as PMOS transistor P4, PMOS transistor P5, PMOS transistor P6, and PMOS transistor P7 as described above in FIG. 4, and/or at least one voltage applied to the memory storage system At least one gate (G) terminal of a crystal, such as PMOS transistor P6 and PMOS transistor P7 as described above in FIG. 4 . In an exemplary embodiment, operation 504 may be performed by selection circuits 104.1-104.x as described in FIG. 1 above, selection circuits 200.1-200.m as described in FIG. 2A above, and selection circuits 200.1-200.m as described in FIG. 2B above The described selection circuits 220.1-200.n and/or the selection circuit 400 as described above in FIG. 4 are performed.

At operation 506, the exemplary operational flow 500 adjusts (eg, increases) the maximum operational voltage signal when the maximum operational voltage signal fluctuates below a first operational voltage signal from the plurality of operational voltage signals. In an exemplary embodiment, operation 504 may be performed by selection circuits 104.1-104.x as described in FIG. 1 above, selection circuits 200.1-200.m as described in FIG. 2A above, and selection circuits 200.1-200.m as described in FIG. 2B above The described selection circuits 220.1-200.n and/or the selection circuit 400 as described above in FIG. 4 are performed. In some cases, the maximum operable voltage signal may fluctuate. These fluctuations can be caused by unwanted electromagnetic coupling and/or leakage between various regions of the various transistors of the memory storage system. The exemplary operational flow 500 may cause current to be derived from the first operational voltage signal to increase the maximum operational voltage signal when the maximum operational voltage signal fluctuates below the first operational voltage signal.

in conclusion

The foregoing detailed description discloses a selection circuit that selectively provides an operational voltage signal to a memory storage system. The selection circuit includes a switch circuit and a latch-up prevention circuit. A switch circuit having a plurality of transistors selects the operable voltage signal from the operable voltage signals. A maximum operable voltage signal among the operable voltage signals is selectively applied to the base terminal of the transistor. The latch-up prevention circuit dynamically adjusts the maximum operable voltage signal to compensate for fluctuations in the maximum operable voltage signal.

In the foregoing specific embodiments, the plurality of transistors include a first transistor and a second transistor. The first transistor is configured to selectively provide a first operable voltage signal from the plurality of operable voltage signals. The second transistor is configured to selectively provide a second operable voltage signal from the plurality of operable voltage signals. A maximum operable voltage signal is selectively applied to a first base terminal of the first transistor and a second base terminal of the second transistor.

In the foregoing embodiments, the first transistor and the second transistor comprise p-type metal oxide semiconductor (PMOS) transistors.

In the foregoing embodiments, the first transistor is configured to selectively provide the first operable voltage signal in response to the bias control signal being at a first logic level. A second transistor is configured to selectively provide the second operable voltage signal in response to the bias control signal being at a second logic level, the second logic level being different from the first logic level bit.

In the foregoing embodiments, the latch-up prevention circuit includes a first diode-connected transistor and a second diode-connected transistor. The first diode-connected transistor and the second diode-connected transistor are respectively coupled to a first operable voltage signal and a second operable voltage signal among the plurality of operable voltage signals. A first diode-connected transistor is configured to obtain a first current from the first operable voltage signal at start-up to adjust the maximum operable voltage signal to compensate for all of the maximum operable voltage signal. described fluctuations. The second diode-connected transistor is configured to obtain a second current from the second operable voltage signal at startup to adjust the maximum operable voltage signal to compensate for the maximum operable voltage signal of the fluctuations.

In the foregoing specific embodiment, the first threshold voltage of the first transistor and the second threshold voltage of the second transistor are greater than the third threshold voltage of the first diode-connected transistor and The second diode is connected to the fourth threshold voltage of the transistor.

In the foregoing embodiments, when the maximum operable voltage signal is less than the first operable voltage signal, the first diode connection transistor is configured to electrically connect through the first diode connection The third threshold voltage of the crystal is activated. When the maximum operable voltage signal is less than the second operable voltage signal, the second diode-connected transistor is arranged to be connected to the fourth side of the transistor through the second diode-connected transistor Voltage limit start.

The foregoing detailed description also discloses a selection circuit for a memory storage system. The selection circuit includes a switch circuit and a latch-up prevention circuit. A switch circuit with a plurality of transistors provides an operable voltage signal selected from a plurality of operable voltage signals to the memory storage system. A latch-up prevention circuit having a first diode-connected transistor and a second diode-connected transistor applies a maximum operable voltage signal selected from a plurality of operable voltage signals to the first diode-connected transistor The first base terminal and the second diode are connected to the second base terminal of the transistor. The first diode-connected transistor and the second diode-connected transistor are respectively coupled to the second operable voltage signal and the third operable voltage signal among the plurality of operable voltage signals. The first diode-connected transistor obtains a first current from the second operable voltage signal upon startup to adjust the second operable voltage signal, thereby compensating for fluctuations in the maximum operable voltage signal. The second diode-connected transistor obtains a second current from the third operable voltage signal upon startup to adjust the second operable voltage signal to compensate for fluctuations in the maximum operable voltage signal.

In the foregoing embodiments, the latch-up prevention circuit is further configured to apply the maximum operable voltage signal to at least one base terminal of at least one of the plurality of transistors.

In the foregoing embodiments, the second operable voltage signal is arranged to reverse bias a parasitic diode located between the source terminal of the at least one transistor and the well region of the at least one transistor.

In the foregoing embodiments, the at least one transistor comprises a p-type metal oxide semiconductor (PMOS) transistor. A maximum operable voltage signal is set to reverse bias the parasitic diode located between the source terminal of the at least one transistor and an n-type well region of the at least one transistor.

In the foregoing embodiments, the first diode-connected transistor and the second diode-connected transistor comprise diode-connected p-type metal oxide semiconductor (PMOS) transistors.

In the foregoing embodiments, a shutdown circuit is configured to selectively provide the maximum operable voltage signal from among the plurality of operable voltage signals as the operable voltage signal to switch the memory storage system Maximizing read/write speed, or selectively providing a minimum operable voltage signal from the plurality of operable voltage signals as the operable voltage signal to minimize power consumption of the memory storage system .

In the foregoing embodiments, the first diode-connected transistor includes a first source terminal coupled to the second operable voltage signal, a first gate terminal coupled to the maximum operable voltage signal, and a first source terminal coupled to the maximum operable voltage signal. connected to the first drain terminal of the maximum operable voltage signal. A second diode-connected transistor includes a second source terminal coupled to the third operable voltage signal, a second gate terminal coupled to the maximum operable voltage signal, and a second gate terminal coupled to the maximum operable voltage signal the second drain terminal of the voltage signal.

In the foregoing embodiments, a first transistor of a plurality of transistors is configured to selectively provide the maximum operable voltage signal as the operable voltage signal from the plurality of operable voltage signals. A second transistor of the plurality of transistors is configured to selectively provide a minimum operable voltage signal from the plurality of operable voltage signals as the operable voltage signal.

In the foregoing embodiments, the first transistor is configured to selectively provide the maximum operable voltage signal in response to the bias control signal being at a first logic level. A second transistor is configured to selectively provide the minimum operable voltage signal in response to the bias control signal being at a second logic level, the second logic level being different from the first logic level .

The foregoing detailed description further discloses a method for preventing latch-up of a memory storage system. The method applies a maximum operable voltage signal to at least one base region of at least one transistor of the memory storage system and to at least one gate region of at least one transistor, and when the maximum operable voltage signal is at a plurality of The maximum operable voltage signal is increased when the first one of the operable voltage signals fluctuates below the first operable voltage signal.

In the foregoing embodiments, the step of increasing includes: when the maximum operable voltage signal fluctuates below the first operable voltage signal, obtaining a current from the first operable voltage signal to increase the Maximum operable voltage signal.

In the foregoing embodiments, the method for preventing latch-up of a memory storage system further comprises: selecting an operable voltage signal from the plurality of operable voltage signals by the memory storage system to dynamically control all the operable voltage signals. operating parameters of the memory storage system.

In the foregoing specific embodiment, the step of selecting the operable voltage signal comprises: selecting the maximum operable voltage signal from the plurality of operable voltage signals by the memory storage system, so as to store the memory The read/write speed of the bulk storage system is maximized, or the smallest operable voltage signal is selected from the plurality of operable voltage signals to minimize power consumption of the memory storage system.

The foregoing Detailed Description refers to the accompanying drawings to describe exemplary embodiments consistent with the present disclosure. References in the foregoing Detailed Description to "exemplary embodiments" indicate that the described illustrative embodiments may include particular features, structures, or characteristics, but each illustrative embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same exemplary embodiment. In addition, any feature, structure or characteristic described in connection with the illustrative embodiments may be included independently or in any combination, whether or not explicitly described in other illustrative embodiments.

The foregoing detailed description is not meant to be limiting. Rather, the scope of the present disclosure is defined only in accordance with the following claims and their equivalents. It should be appreciated that the foregoing Detailed Description, rather than the following Summary of the Invention section, is intended to interpret the scope of the claims. The Summary of the Invention section may describe one or more, but not all, exemplary embodiments of the disclosure, and is thus not intended to limit the disclosure and the scope of the claims below and their equivalents in any way.

The illustrative embodiments described in the foregoing Detailed Description have been provided for purposes of illustration and are not intended to be limiting. Other exemplary embodiments are possible, and modifications may be made to the exemplary embodiments while remaining within the spirit and scope of the present disclosure. The foregoing detailed description has been described in terms of functional building blocks used to illustrate the implementation of specific functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for ease of description. Alternate boundaries can be defined as long as the specified functions and their relationships are properly performed.

Embodiments of the present disclosure may be implemented in hardware, firmware, software, or any combination thereof. Embodiments of the present disclosure may also be implemented as instructions stored on a machine-readable medium readable and executable by one or more processors. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (eg, a computing circuit). For example, machine-readable media may include non-transitory machine-readable media, such as read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; and others media. As another example, machine-readable media may include transitory machine-readable media, such as electrical, optical, acoustic, or other forms of propagated signals (eg, carrier waves, infrared signals, digital signals, etc.). Additionally, firmware, software, routines, instructions may be described herein as performing particular actions. It should be understood, however, that such descriptions are for convenience only and that such actions are in fact caused by a computing device, processor, controller, or other device executing firmware, software, routines, instructions, or the like.

The foregoing detailed description fully discloses the general nature of the present disclosure: others can easily, by application of knowledge of those of ordinary skill in the relevant technical fields, without departing from the spirit and scope of the present disclosure, and without undue experimentation, Such exemplary embodiments can be modified and/or adapted for various applications. Accordingly, such adaptations and modifications are intended to be within the meaning of the exemplary embodiments and the scope of their various equivalents, based on the teachings and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not limitation, such that the terms or phraseology of this specification should be interpreted by one of ordinary skill in the relevant art in light of the teachings herein.

:偏壓控制信號 502、504、506:操作 I_DD 、I_DDM 、:電流 N1~N3、N4:n型金屬氧化物半導體電晶體 P1、P2、P4、P5、P6、P7:p型金屬氧化物半導體電晶體 V₁ 、V_DD 、V_DDM 、V_{DDM_INT} 、V_{DDM_INT.1} 、V_{DDM_INT.m} 、V_{DDM_INT.n} 、V_{DDM_INT.x} 、V _m :可操作電壓信號 V_DDMAX :最大可操作電壓信號100, 500: memory storage system 102: voltage generator circuit 104.1, 104.x , 200.1~ 200.m , 220.1~ 220.n , 400: selection circuit 106, 202, 222: memory device 150: bias voltage control Signal 152: selection control signals 204, 224: memory arrays 210.1.1 ~ 210.m.n , 226.1.1 ~ 226.m.n : memory cells 212.1~ 212.n , 350: word lines 214.1, 214. m , 352: bit line 300: SRAM cell 402: switch circuit 404: latch-up prevention circuit 452,

: bias voltage control signals 502, 504, 506: operation _IDD , _IDDM ,: current N1~N3, N4: n-type metal oxide semiconductor transistors P1, P2, P4, P5, P6, P7: p-type metal oxide V ₁ , V _DD , V _DDM , V _{DDM_INT} , V _{DDM_INT.1} , V DDM_INT.m , V _{DDM_INT.n ,} V _{DDM_INT.x} , V _m : operable voltage signal V _DDMAX : maximum operable voltage Signal

Aspects of the present disclosure are best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 shows a block diagram of an exemplary memory storage system according to an exemplary embodiment of the present disclosure. 2A shows a block diagram of a first exemplary memory device that may be implemented within an exemplary memory storage system according to exemplary embodiments of the present disclosure. 2B shows a block diagram of a second exemplary memory device that may be implemented within an exemplary memory storage system according to exemplary embodiments of the present disclosure. 3 shows a block diagram of an exemplary static random-access memory (SRAM) cell that may be implemented within an exemplary memory device in accordance with disclosed exemplary embodiments. 4 shows a block diagram of an exemplary select circuit that may be implemented within an exemplary memory device in accordance with exemplary embodiments of the present disclosure. 5 shows a flow diagram of an exemplary operation of an exemplary memory storage system in accordance with an exemplary embodiment of the present disclosure.

100: Memory Storage System

102: Voltage generator circuit

104.1, 104. x : Selection circuit

106: Memory device

150: Bias voltage control signal

152: Select control signal

V ₁ , V _{DDM_INT.1} , V _{DDM_INT.x} , V _m : operable voltage signals

V _DDMAX : maximum operable voltage signal

Claims (10)

A latch-up prevention circuit for a memory storage system, comprising: a first transistor and a second transistor respectively configured to apply a first operable voltage signal selected from a plurality of operable voltage signals to a first base terminal of the first transistor and the second the second base terminal of the transistor, wherein the first transistor and the second transistor are respectively coupled to a second operable voltage signal and a third operable voltage signal among the plurality of operable voltage signals, wherein the first transistor is further configured to obtain a first current from the second operable voltage signal upon start-up to adjust the first operable voltage signal to compensate for the first operable voltage signal volatility, and wherein the second transistor is further configured to obtain a second current from the third operable voltage signal upon start-up to adjust the first operable voltage signal to compensate for the first operable voltage signal the fluctuations. The latch-up prevention circuit of claim 1, wherein the first transistor is configured to be activated in response to the first operable voltage signal, wherein the first operable voltage signal is higher than the second operable voltage signal the operating voltage signal is less than at least the first threshold voltage of the first transistor, and wherein the second transistor is configured to be activated in response to the first operable voltage signal, wherein the first operable voltage signal is less than the third operable voltage signal by at least the second transistor's The second threshold voltage. The latch-up prevention circuit of claim 2, wherein when the first transistor is activated is set to obtain the first current from a first source region to a first drain region to increase all the first operable voltage signal, and wherein when the second transistor is activated is set to obtain the second current from a second source region to a second drain region to increase the first operable voltage signal. A method for preventing latch-up of a memory storage system, comprising: A first operable voltage signal selected from a plurality of operable voltage signals is applied by the memory storage system to the first base terminal of the first diode-connected transistor and the second diode-connected transistor two base extremes; By activating the first diode-connected transistor to adjust the maximum operable voltage signal to compensate for the fluctuation of the maximum operable voltage signal, the memory storage system obtains from a plurality of operable voltage signals the first current of the second operable voltage signal; and The maximum operable voltage signal is adjusted by activating the second diode-connected transistor to compensate for the fluctuation of the maximum operable voltage signal, so that the memory storage system obtains from a plurality of operable voltages The second current of the third operable voltage signal among the signals. The method of claim 4, wherein the step of obtaining the first current comprises: The first diode-connected transistor is activated in response to the first operable voltage signal, wherein the first operable voltage signal is less than the second operable voltage signal by at least a second of the first transistor a threshold voltage; and The step of obtaining the second current includes: The second diode-connected transistor is activated in response to the first operable voltage signal, wherein the first operable voltage signal is less than the third operable voltage signal by at least a second of the second transistor 2. Threshold voltage. The method of claim 5, wherein the step of obtaining the first current further comprises: obtaining the first current from a first source region to a first drain region to increase the first operable voltage signal when the first diode-connected transistor is activated, and The step of obtaining the second current includes: The second current from the second source region to the second drain region is obtained to increase the first operable voltage signal when the second diode-connected transistor is activated. A latch-up prevention circuit for a memory storage system, comprising: a transistor configured to apply a first operable voltage signal selected from a plurality of operable voltage signals to the base terminal of the transistor, wherein the transistor is coupled to a second operable voltage signal among the plurality of operable voltage signals, and wherein the transistor is further configured to obtain current from the second operable voltage signal to adjust the operable voltage signal to compensate for fluctuations in the operable voltage signal. The latch-up prevention circuit of claim 7, wherein the transistor is configured to be activated in response to the first operable voltage signal, wherein the first operable voltage signal is higher than the second operable voltage The signal is at least the threshold voltage of the transistor. The latch-up prevention circuit of claim 8, wherein the transistor is configured to obtain the current from the source region to the drain region to increase the first operable voltage signal when activated. A selection circuit for selectively providing an operable voltage signal to a memory storage system, comprising: a switch circuit having a plurality of transistors configured to select the operable voltage signal from among a plurality of operable voltage signals, the switch circuit configured to provide the operable voltage signal to the memory storage system, A maximum operable voltage signal among the plurality of operable voltage signals is selectively applied to the base terminals of the plurality of transistors; and A latch-up prevention circuit configured to dynamically adjust the maximum operable voltage signal to compensate for fluctuations in the maximum operable voltage signal.

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