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TWI720623B - 半導體裝置及其形成方法 - Google Patents

半導體裝置及其形成方法 Download PDF

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Publication number
TWI720623B
TWI720623B TW108133987A TW108133987A TWI720623B TW I720623 B TWI720623 B TW I720623B TW 108133987 A TW108133987 A TW 108133987A TW 108133987 A TW108133987 A TW 108133987A TW I720623 B TWI720623 B TW I720623B
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Taiwan
Prior art keywords
wafer
connectors
semiconductor device
area
sealing rings
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TW108133987A
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English (en)
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TW202013636A (zh
Inventor
劉浩君
蕭景文
許國經
李明機
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台灣積體電路製造股份有限公司
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Abstract

提供一種半導體裝置及其形成方法。上述半導體裝置包括：一晶片結構，包括複數個晶片區；以及複數個第一密封環。每個第一密封環圍繞複數個晶片區中的一對應的晶片區。上述半導體裝置更包括：一第二密封環，圍繞複數個第一密封環；以及複數個連接器，接合於該晶片結構。每個複數個連接器具有一延伸的平面圖下的形狀，每個複數個連接器的延伸的平面圖下的形狀的長軸指向晶片結構的中心。

Description

半導體裝置及其形成方法
本發明實施例是關於一種半導體裝置及其形成方法，特別是關於用於積體電路封裝體的接合結構及其形成方法。
半導體裝置用於各種電子應用領域，例如個人電腦、行動電話、數位相機及其他電子設備。半導體裝置的製造，通常藉由在一半導體基底的上方系列地沉積絕緣或介電層、導體層及半導體層的材料以及使用光微影以將上述各種材料層圖形化而形成電路構件及其上的元件。
半導體工業持續改善各種電子構件(例如：電晶體、二極體、電阻器、電容器等等)的集積密度，藉由持續縮小其最小特徵尺寸，而得以將更多的構件整合至既定的面積。在一些應用中，這些較小的電子構件亦需要比傳統封裝體使用較少面積或較低的高度的較小的封裝體。
因此，已經開始發展新的封裝技術。這些用於半導體裝置的相對較新型式的封裝技術，面臨製造上的挑戰。
一實施例是關於一種半導體裝置，包括：一晶片結構，包括複數個晶片區；複數個第一密封環，每個上述第一密封環圍繞上述晶片區中的一對應的晶片區；一第二密封環，圍繞上述第一密封環；以及複數個連接器，接合於上述晶片結構，每個上述連接器具有一延伸的平面圖下的形狀，每個上述連接器的上述延伸的平面圖下的形狀的長軸指向上述晶片結構的中心。
另一實施例是關於一種半導體裝置，包括：一晶片結構，包括一第一區與一第二區，上述第一區包括複數個第一晶片區，上述第二區包括複數個第二晶片區；複數個第一密封環，每個上述第一密封環圍繞上述第一晶片區與上述第二晶片區中的一對應的晶片區；一第二密封環，圍繞上述第一區與上述第二區；以及複數個連接器，接合於上述晶片結構，每個上述連接器具有一延伸的平面圖下的形狀，沿著每個上述連接器的上述延伸的平面圖下的形狀的長軸之線，與上述晶片結構的中心相交。
又另一實施例是關於一種半導體裝置的形成方法，包括：在一晶圓形成複數個單位區域，每個上述單位區域包括複數個晶片區；在上述晶圓形成複數個第一密封環，每個上述第一密封環圍繞上述晶片區中的一對應的晶片區；在上述晶圓形成複數個第二密封環，每個上述第二密封環圍繞上述單位區域中的一對應的單位區域；以及在上述晶圓的上方形成複數個連接器，每個上述連接器具有一延伸的平面圖下的形狀，每個上述連接器的上述延伸的平面圖下的形狀的長軸指向上述單位區域中的一對應的單位區域的中心。
要瞭解的是，以下的揭露內容提供許多不同的實施例或範例以實現本發明實施例的不同構件。以下的揭露內容敘述各個構件及其排列方式的特定實施例或範例，以簡化本發明實施例的說明。當然，這些特定的範例並非用以限定。例如，元件的尺寸並非受限於所揭露的範圍或值，但可能依存於製程條件及/或裝置所需求的性質。此外，若是本發明實施例敘述了一第一構件形成於一第二構件之上或上方，即表示其可能包括上述第一構件與上述第二構件是直接接觸的實施例，亦可能包括了有附加構件形成於上述第一構件與上述第二構件之間，而使上述第一構件與第二構件可能未直接接觸的實施例。為了簡潔，可能以任意的比例繪示各種構件。此外，本發明實施例可能會在各種實施例重複使用相同的元件符號。這樣的重複是為了敘述上的簡化與明確，而非意指所討論的不同實施例及/或結構之間的關係。
此外，其與空間相關用詞。例如「在…下方」、「下方」、「較低的」、「上方」、「較高的」及類似的用詞，係為了便於描述圖示中一個元件或構件與另一個(些)元件或構件之間的關係。除了在圖式中繪示的方位外，這些空間相關用詞意欲包括使用中或操作中的裝置之不同方位。裝置可能被轉向不同方位(旋轉90度或其他方位)，則在此使用的空間相關詞也可依此相同解釋。
以下將敘述的實施例是關於在特定背景的實施例，即用於積體電路封裝體的接合結構(例如連接墊上的凸塊的結構(bump-on-pad structures))及其形成方法。然而，本發明實施例亦可應用於其他實施形態而應用於其他電性接合構件，其包括但不限於在組裝及封裝中、在基底加工中、在中介物或中介層(interposers)加工中或類似加工中或類似者；抑或但不限於在安裝輸入構件、電路板、晶片或其他構件；抑或但不限於用於連接物的封裝或安裝任何形式的積體電路或電性構件的組合中的封裝體對封裝體堆疊的組裝(package-on-package assemblies)、晶片對晶片的組裝(die-to-die assemblies)、晶圓對晶圓的組裝(wafer-to-wafer assemblies)、晶片對基底的組裝(die-to-substrate assemblies)。
在此敘述的各種實施例得以用來形成連接器或接合結構，上述連接器或接合結構用於將一多晶片結構接合於一基底，而使接合結構具有延伸的形狀而沿著從上述多晶片結構或上述基底的中心發散的線對準。在此敘述的各種實施例還得以用來形成一多晶片結構中的密封環結構。在此敘述的各種實施例還得以用來減少施加於上述多晶片結構的各層(例如：低介電常數介電層)的應力，此應力是由於上述多晶片結構與上述基底之間的熱膨脹係數(coefficient of thermal expansion；CTE)的差異所引發。還有，亦減少施加於上述接合結構的應力，而改善上述接合結構的電性的性能及機械性的性能。
第1A與1B圖分別顯示關於一些實施例的一晶圓100的一俯視圖與一剖面圖。第1A圖顯示晶圓100的俯視圖，而第1B圖則顯示晶圓100之沿著第1A圖所示的BB線的剖面圖。在一些實施例中，晶圓100包括複數個單位區域101，單位區域101被複數個劃分線(scribe lines)103(亦稱為切割線或切割道)所分離。如後文較詳細的說明，將會沿著劃分線103對晶圓100作切割，以形成個別的晶片結構(例如繪示於第8圖的一晶片結構801)。在一些實施例中，每個單位區域101是一多晶片結構，此多晶片結構包括複數個晶片區，例如晶片區105、107、109與111。每個晶片區105、107、109與111可包括一積體電路晶片，例如一邏輯裝置、記憶體裝置(例如：靜態隨機存取記憶體)、射頻裝置、輸入/輸出(I/O)裝置、系統整合晶片(system-on-chip；SoC)裝置、上述之組合或任何適當形式的裝置。
在一些實施例中，晶圓100包括一基底113以及基底113上的一或多個主動及/或被動裝置115。在一些實施例中，基底113可以以矽形成，但亦可以以例如矽、鍺、砷化鎵或上述之組合等的其他III族、IV族及/或V族元素形成。基底113可以是絕緣層上覆矽(silicon-on-insulator；SOI)的形式。上述絕緣層上覆矽的基底可包括形成在一絕緣層(例如：埋入式氧化物及/或類似物)的上方的一半導體材料(例如：矽、鍺及/或類似物)，而上述絕緣層則形成在一矽基底上。此外，可使用其他的基底，包括多層基底、組成漸變基底、混合取向基底(hybrid orientation substrates)、上述的任意組合及/或類似基底。在一些實施例中，上述一或多個主動及/或被動裝置115可包括各種n型金屬―氧化物―半導體(n-type metal-oxide semiconductor；NMOS)裝置及/或p型金屬―氧化物―半導體(p-type metal-oxide semiconductor；PMOS)裝置，例如電晶體、電容器、二極體、光學二極體、熔斷器及/或類似裝置。
在基底113的上方以及上述一或多個主動及/或被動裝置115的上方，形成複數個介電層117。介電層117可包括一層間介電(inter-layer dielectric；ILD)層及複數個金屬間介電(inter-metal dielectric；IMD)層。上述層間介電層及複數個金屬間介電層可以以例如一低介電常數介電材料形成，例如磷矽玻璃(Phospho-Silicate Glass；PSG)、硼磷矽玻璃(Boron-Doped Phospho-Silicate Glass；BPSG) 、摻氟的矽玻璃(fluorinated silicate glass；FSG)、SiOx Cy 、旋塗玻璃(Spin-On-Glass)、旋塗聚合物(Spin-On-Polymers)、矽碳材料(silicon carbon material)、上述之組合物、上述之複合物、上述之組合或類似物，並可藉由在本技術領域習知的任何方法形成，例如旋轉塗佈法(spin-on coating method)、化學氣相沉積(Chemical Vapor Deposition；CVD)、電漿輔助化學氣相沉積(Plasma Enhanced Chemical Vapor Deposition；PECVD)、上述之組合或類似方法。介電層117可包括複數個導體互連結構119。在一些實施例中，互連結構119可包括複數個導線121與複數個導通孔123。在一些實施例中，互連結構119可使用例如一鑲嵌製程(damascene process)、一雙鑲嵌製程(dual damascene process)或類似製程而形成於介電層117。在一些實施例中，互連結構119可包括銅、銅合金、銀、金、鎢、鉭、鋁或類似物。互連結構119與基底113上的上述一或多個主動及/或被動裝置115電性互連，以在晶片區105、107、109與111中形成功能性的電路。
介電層117可更包括複數個密封環部125A與125B，其延伸穿透介電層117。可將密封環部125A置於晶片區105、107、109與111的邊緣區；而以平面圖觀之，密封環部125A可環繞或圍繞晶片區105、107、109與111的內部。可將密封環部125B置於單位區域101的邊緣區；而以平面圖觀之，密封環部125B可環繞或圍繞單位區域101的內部。每個密封環部125B可環繞或圍繞對應的密封環部125A。在一些實施例中，密封環部125A與125B可包括導線121與導通孔123，且可使用與互連結構119類似的材料與製程來形成。例如，用於形成互連結構119的相同製程可同時形成密封環部125A與125B。在一些實施例中，密封環部125A與125B可以被彼此電性隔離。在一些實施例中，密封環部125A與125B可以與互連結構119電性隔離。
在一些實施例中，在介電層117的上方、互連結構119的上方及密封環部125A與125B的上方，形成一鈍化層127。在一些實施例中，鈍化層127可包括一或多層的不可藉由光線圖形化(non-photo-patternable)的介電材料，例如氮化矽、氧化矽、磷矽玻璃(Phospho-Silicate Glass；PSG)、硼矽玻璃(Boro-Silicate Glass；BSG)、硼磷矽玻璃(Boron-Doped Phospho-Silicate Glass；BPSG)、上述之組合或類似材料，且可使用化學氣相沉積、物理氣相沉積(physical vapor deposition；PVD)、原子層沉積(Atomic Layer Deposition；ALD)、一旋轉塗佈製程、上述之組合或類似方法而形成。在其他實施例中，鈍化層127可包括一或多層的可藉由光線圖形化(photo-patternable)的絕緣材料，例如聚苯并㗁唑(polybenzoxazole；PBO)、聚醯亞胺(polyimide；PI)、苯環丁烯(benzocyclobutene；BCB)或類似材料，且可使用一旋轉塗佈製程或類似方法而形成。這樣的可藉由光線圖形化的介電材料，可以如同一光阻材料而使用類似的光學微影方法將其圖形化。
在形成鈍化層127之後，在鈍化層127的上方形成導體墊129A、129B與129C。導體墊129A物理性地連接於對應的密封環部125A，導體墊129B物理性地連接於對應的密封環部125B，導體墊129C物理性地連接於對應的互連結構119。在一些實施例中，導體墊129A、129B與129C包括一導體材料，例如鋁、銅、鎢、銀、金、上述之組合或類似材料。在一些實施例中，可使用適當的光學微影及蝕刻方法來將鈍化層127圖形化，以暴露出互連結構119及密封環部125A與125B。使用例如物理氣相沉積、原子層沉積、電化學鍍(electro-chemical plating)、無電化學鍍(electroless plating) 、上述之組合或類似方法，在鈍化層127的上方、互連結構119的暴露的部分的上方以及密封環部125A與125B的暴露的部分的上方，形成一適當的導體材料。後續，將此導體材料圖形化，以形成導體墊129A、129B與129C。在一些實施例中，可使用適當的光學微影及蝕刻方法來將上述導體材料圖形化。每個導體墊129A可環繞或圍繞晶片區105、107、109與111中的對應的一個的內部。每個導體墊129B可環繞或圍繞單位區域101中的對應的一個的內部。
密封環部125A與導體墊129A形成一密封環131A，密封環131A環繞晶片區105、107、109與111中的對應的一個的內部。密封環部125B與導體墊129B形成一密封環131B，密封環131B環繞單位區域101中的對應的一個的內部。每個密封環131B環繞密封環131A中與其對應者。在一些實施例中，密封環131A與131B可以與彼此電性隔離。在一些實施例中，密封環131A與131B可以與互連結構119電性隔離。在一些實施例中，密封環131A與131B可具有實質上類似的結構。在其他實施例中，密封環131A與131B可具有不同的結構。
在形成導體墊129A、129B與129C之後，在導體墊129A、129B與129C的上方形成一鈍化層133，在鈍化層133的上方形成一緩衝層135。鈍化層133可使用與鈍化層127類似的材料及方法而形成，在此不再重複敘述。在一些實施例中，鈍化層133與鈍化層127包括相同的材料；在其他實施例中，鈍化層133與鈍化層127包括不同的材料。在一些實施例中，緩衝層135可包括一或多層的可藉由光線圖形化(photo-patternable)的絕緣材料，例如聚苯并㗁唑(polybenzoxazole；PBO)、聚醯亞胺(polyimide；PI)、苯環丁烯(benzocyclobutene；BCB)或類似材料，且可使用一旋轉塗佈製程或類似方法而形成。在一些實施例中，緩衝層135部分地(如第1B圖中的緩衝層135的實線部分所示)或完全(如第1B圖中的緩衝層135的虛線部分所示)覆蓋密封環131A，同時暴露出密封環131B。
在形成緩衝層135之後，分別在導體墊129C的上方形成連接器137。在一些實施例中，每個連接器137延伸而穿透緩衝層135與鈍化層133，並物理性地接觸導體墊129C中的對應的一個。在一些實施例中，每個連接器137包括一凸塊下金屬(under-bump metallurgy；UBM)層139、在凸塊下金屬層139的上方的一導體柱141與在導體柱141的上方的一焊料層143。在一些實施例中，凸塊下金屬層139包括一擴散阻障層與一種子層(未個別繪示)。上述擴散阻障層可以以氮化鉭、氮化鈦、鉭、鈦、上述之組合或類似材料來形成。上述種子層可以是形成在上述擴散阻障層上的銅種子層。上述銅種子層可以以銅或銅合金的一種形成，上述銅合金包括銀、鉻、鎳、錫、金及/或上述之組合。在一些實施例中，凸塊下金屬層139包括以鈦形成的一擴散阻障層以及以銅形成的一種子層。導體柱141包括一導體材料，例如銅、鎢、鋁、銀、金、上述之組合或類似材料。在一些實施例中，焊料層143包括適當的焊材。上述焊材可以是例如PbSn的成分的含鉛銲料、包含InSb與錫和銀還有銅(「SAC」)的成分的無鉛銲料、也可以是具有共通熔點並形成關於電的應用中的導體焊料連接的其他共晶材料。作為無鉛銲料，可使用不同成分的SAC焊料，例如SAC 105(98.5%的錫、1.0%的銀、0.5%的銅)、SAC 305、SAC 405等等。無鉛銲料亦包括未使用銀(Ag)的SnCu組合物(SnCu compounds)、未使用銅(Cu)的SnAg組合物(SnAg compounds)。
請進一步參考第1A圖，在一些實施例中，連接器137具有一延伸的平面圖下的形狀。上述延伸的平面圖下的形狀可以是卵形、橢圓形、跑道形狀(racetrack shapes)或類似形狀。將連接器137排列成沿著每個連接器137的一延伸的平面圖下的形狀的長軸之線145，與單位區域101中的對應的一個的中心147相交。在第1A圖所示的連接器137的數量及位置僅提供作為一範例。在其他實施例中，連接器137的數量及位置可根據所形成的封裝裝置的設計需求而變化。在一些實施例中，中心147可以是被密封環131B圍繞的區域的中心。
第2至7圖為一系列之剖面圖，顯示關於一些實施例的連接器137(請見第1A與1B圖)的形成的中間階段。上述形成方法是針對複數個連接器137中的一個作敘述，因為其餘的連接器137亦是在相同的形成製程的過程中形成為類似的形式。請參考第2圖，在導體墊129C的上方形成鈍化層133之後，在鈍化層133中形成一開口201，以暴露出導體墊129C的一部分。在鈍化層133包括不可藉由光線圖形化的介電材料的一些實施例中，可使用適當的光學微影及蝕刻方法來將鈍化層133圖形化。在形成開口201之後，在鈍化層133的上方及開口201中形成緩衝層135。將緩衝層135圖形化，以移除緩衝層135之在開口201中的部分，以暴露出導體墊129C。在一些實施例中，可使用一適當的光學微影技術來將緩衝層135圖形化。在將緩衝層135圖形化之後，在緩衝層135的上方及開口201中毯覆式地沉積凸塊下金屬層139。在一些實施例中，可藉由原子層沉積、物理氣相沉積、濺鍍、上述之組合或類似方法，形成凸塊下金屬層139的各層。
請參考第3圖，在凸塊下金屬層139的上方形成一圖形化的遮罩301。在一些實施例中，圖形化的遮罩301包括一光阻材料或任何可藉由光線圖形化的材料。在一些實施例中，使用一適當的光學微影技術，將圖形化的遮罩301的材料圖形化，以形成一開口303，藉以形成圖形化的遮罩301。開口303暴露出凸塊下金屬層139之形成在導體墊129C的上方、開口201中的部分。
請參考第4圖，在以開口201與303(請見第3圖)形成的複合開口中，形成導體柱141。在一些實施例中，使用電化學鍍、無電化學鍍、原子層沉積、物理氣相沉積、上述之組合或類似方法，以一適當的導體材料填入上述複合開口。在一些實施例中，導體柱141部分地填入上述複合開口，而以一焊材填入上述複合開口的其餘部分，以形成在導體柱141的上方的焊料層143。在一些實施例中，可使用蒸鍍、電化學鍍、無電化學鍍、印刷、焊料轉移、上述之組合或類似方法，來形成上述焊材。
請參考第5圖，在形成導體柱141與焊料層143之後，移除圖形化的遮罩301(請見第4圖)。在一些實施例中，包含一光阻材料的圖形化的遮罩301可使用一灰化製程(ashing process)及後續的一溼式清潔製程來移除。
請參考第6圖，在將圖形化的遮罩301(請見第4圖)移除之後，使用例如一或多道的適當的蝕刻製程，移除凸塊下金屬層139之暴露的部分。
請參考第7圖，在將凸塊下金屬層139之暴露的部分移除之後，對焊料層143進行一回流(reflow)製程，以將焊料層143的焊材的形狀重塑成一所欲的形狀。
請進一步參考第1A、1B與2至7圖，在將連接器137形成在晶圓100上之後，沿著相鄰的密封環131B之間的劃分線103將單位區域101分離，以形成例如示於第8圖的一晶片結構801等的複數個個別的晶片結構。上述分離製程可包括一切割製程(sawing process)、一蝕刻製程、一雷射剝蝕(laser ablation)製程、上述之組合或類似製程。密封環131B在分離的過程中保護單位區域101的各種構件，並可減少或避免缺陷(例如：脫層、龜裂或類似缺陷)的形成。請參考第8圖，由於晶片結構801對應於單獨的單位區域101(請見第1A圖)，複數個連接器137指向晶片結構801的中心803，而晶片結構801的中心803重合於單位區域101的中心147。在晶片結構801具有矩形的平面圖形狀的一些實施例中，在平面圖中，晶片結構801具有一第一寬度W1 與一第二寬度W2 。在一些實施例中，晶片結構801的第一寬度W1 可大於、等於或小於晶片結構801的第二寬度W2 。在一些實施例中，晶片結構801的第一寬度W1 可小於約26mm，例如約26mm。在一些實施例中，晶片結構801的第二寬度W2 可小於約32mm，例如約32mm。在一些實施例中，在平面圖中，密封環131B具有一第一寬度W3 與一第二寬度W4 。在一些實施例中，密封環131B的第一寬度W3 可大於、等於或小於密封環131B的第二寬度W4 。在一些實施例中，第一寬度W3 可等於第二寬度W4 ，且可等於約21.6µm。在一些實施例中，在平面圖中，密封環131A具有一第一寬度W5 與一第二寬度W6 。在一些實施例中，密封環131A的第一寬度W5 可大於、等於或小於密封環131A的第二寬度W6 。在一些實施例中，第一寬度W5 可等於第二寬度W6 ，且可等於約21.6µm。在平面圖中，連接器137具有沿著短軸的一第一寬度W7 與沿著長軸的一第二寬度W8 。在一些實施例中，連接器137的第一寬度W7 小於連接器137的第二寬度W8 。在一些實施例中，連接器137的第一寬度W7 是在約30µm與約210µm之間。在一些實施例中，連接器137的第二寬度W8 是在約40µm與約270µm之間。在一些實施例中，比值W7 /W8 是在約0.75與約0.80之間。
第9A與9B圖分別顯示關於一些實施例的一封裝體900的一俯視圖與一剖面圖。封裝體900包括晶片結構801，其中使用複數個接合結構903而將晶片結構801貼附於一基底901。一底膠(underfill)材料905是形成在晶片結構801與基底901之間，並圍繞接合結構903。底膠材料905可以是例如一液態環氧樹脂、可形變的膠體(deformable gel)、矽橡膠(silicon rubber)或類似材料，將上述材料分配於上述結構之間，然後使其熟化而硬化。可在其他構件之間使用底膠材料905，以減少對接合結構903的傷害並保護接合結構903。用於將晶片結構801接合至基底901的製程步驟以及用於形成接合結構903的製程步驟，是繪示在後續而請參考第10與11圖，且在後續提供詳細敘述。在一些實施例中，基底901可包括類似於參考第1A與1B圖的前述的基底113的半導體晶圓的一部分，在此不再重複敘述。在一些實施例中，基底901亦包括被動裝置或主動裝置，上述被動裝置例如為電阻器、電容器、電感器及/或類似裝置，上述主動裝置例如為電晶體。在一些實施例中，基底901包括額外的積體電路。基底901可進一步包括複數個穿透矽通孔(through substrate vias；TSVs)，並可以是一中介物或中介層(interposer)。在一些實施例中，基底901可以是一封裝基板、一已封裝的晶片、一晶片結構或類似構件。在一些實施例中，基底901可更包括複數個連接器907，連接器907可用來將封裝體900機械性及電性連接於例如一晶片結構、一印刷電路板、另一個封裝體或類似構件等的外部構件。在一些實施例中，連接器907可以是焊料球(solder balls)、塌陷高度控制晶片連接(controlled collapse chip connection；C4)的凸塊、球閘陣列(ball grid array；BGA)的球、化學鍍鎳化學鍍鈀與浸金技術(electroless nickel-electroless palladium-immersion gold technique；ENEPIG)形成的凸塊或類似構件。
第10與11圖為一系列之剖面圖，顯示關於一些實施例的封裝體900及接合結構903(請見第9A與9B圖)的形成的中間階段。第10與11圖繪示基底901與晶片結構801的局部的放大圖，此部分在完成接合製程後將會成為封裝體900的一部分909(請見第9B圖)。第10圖繪示在施行接合製程而形成封裝體900之前的晶片結構801與基底901的相對位置。基底901可包括複數個導體墊，例如為導體墊1001，導體墊1001介於鈍化層1003與1005之間。在一些實施例中，可使用類似於參考第1A與1B圖的前述的鈍化層127的材料與方法來形成鈍化層1003與1005，在此不再重複敘述。可使用類似於參考第1A與1B圖的前述的導體墊129C的材料與方法來形成導體墊1001，在此不再重複敘述。導體墊1001被鈍化層1005部分地覆蓋。在鈍化層1005的上方形成一焊料層1007，以填入形成於鈍化層1005中的一開口，用於後續與晶片結構801的對應的連接器137的焊料層143或導體柱141(如果省略焊料層143)的接合。可使用類似於參考第1A、1B、4至7圖的前述的焊料層143的材料與方法來形成焊料層1007，在此不再重複敘述。
請參考第11圖，使焊料層143與1007(請見第10圖)物理性接觸，並施行一回流製程，以將焊料層143與1007合併成為一共通焊料層1101，共通焊料層1101將導體墊1001接合至導體柱141。凸塊下金屬層139、導體柱141與共通焊料層1101形成一接合結構903。
請參考第9A、9B、10與11圖，由於晶片結構801與基底901中的材料之間的熱膨脹係數(coefficients of thermal expansion；CTE)的不同，在例如前述的回流製程等的一熱處處理的施行的過程中或之後，其相對位置會移動。在一些實施例中，上述相對位置的移動可能會導致晶片結構801的連接器137與基底901的對應的焊料層1007之間失去對準，並降低接合結構903的電性的功能及機械性的功能。在一些實施例中，相對於晶片結構801與基底901的中心，上述相對位置的移動在晶片結構801與基底901的邊緣會變得較顯著。為了避免晶片結構801的連接器137與基底901的對應的焊料層1007之間失去對準，將連接器137排列成每個連接器137的延伸的平面圖下的形狀的長軸實質上指向晶片結構801的中心803，以將連接器137與對應的焊料層1007之間的接合面積最大化。在一些實施例中，將晶片結構801的連接器137排列成連接器137的延伸的平面圖下的形狀的長軸還實質上指向基底901的中心。在這樣的實施例中，在平面圖中，基底901的中心是與晶片結構801的中心803重合。連接器137的這樣的排列及形狀以及接合結構903的結果，減少了接合結構903上的應力。還有，在上述接合製程(例如：一回流製程)的期間由於晶片結構801與基底901之間的熱膨脹係數的不匹配所引發的施加於晶片結構801的各層(例如，示於第1B圖的複數個介電層117)的應力可被降低，其可避免晶片結構801的各層的龜裂或脫層。
第12A與12B圖分別顯示關於一些實施例的一晶圓1200的一俯視圖與一剖面圖。第12A圖顯示晶圓1200的俯視圖，而第12B圖則顯示晶圓1200之沿著第12A圖所示的BB線的剖面圖。在一些實施例中，晶圓1200類似於晶圓100，其中類似的構件標上類似的元件符號，而在此不再重複類似構件的敘述。在一些實施例中，晶圓1200包括複數個單位區域101，單位區域101被複數個劃分線103所分離。在一些實施例中，可使用類似於參考第1A、1B、2至7圖的前述的晶圓100的材料與方法來形成晶圓1200，在此不再重複敘述。在一些實施例中，將密封環131B形成為使每個密封環131B環繞二個相鄰的單位區域101，以形成雙單位區域1201。在一些實施例中，在雙單位區域1201的上方形成連接器137，而使沿著每個連接器137的一延伸的平面圖下的形狀的長軸之線1203，與雙單位區域1201中的對應的一個的中心1205相交。在一些實施例中，中心1205可以是被密封環131B圍繞的區域的中心。在第12A圖所示的連接器137的數量及位置僅提供作為一範例。在其他實施例中，連接器137的數量及位置可根據所形成的封裝裝置的設計需求而變化。
請進一步參考第12A與12B圖，在將連接器137形成在晶圓1200上之後，沿著相鄰的密封環131B之間的劃分線103將雙單位區域1201分離，以形成例如示於第13圖的一晶片結構1301等的複數個個別的晶片結構。上述分離製程可包括一切割製程、一蝕刻製程、一雷射剝蝕製程、上述之組合或類似製程。密封環131B在分離的過程中保護雙單位區域1201的各種構件，並可減少或避免缺陷(例如：脫層、龜裂或類似缺陷)的形成。請參考第13圖，由於晶片結構1301對應於單獨的雙單位區域1201(請見第12A圖)，複數個連接器137指向晶片結構1301的中心1303，而晶片結構1301的中心1303重合於對應的雙單位區域1201的中心1205。在晶片結構1301具有矩形的平面圖形狀的一些實施例中，在平面圖中，晶片結構1301具有一第一寬度W9 與一第二寬度W10 。在一些實施例中，晶片結構1301的第一寬度W9 可大於、等於或小於晶片結構1301的第二寬度W10 。在一些實施例中，晶片結構1301的第一寬度W9 在約26mm與約286mm之間。在一些實施例中，晶片結構1301的第二寬度W10 在約32mm與約288mm之間。亦可將晶片結構1301稱為2×光罩結構，而亦可將晶片結構801(請見第8圖)稱為1×光罩結構。
第14A與14B圖分別顯示關於一些實施例的一封裝體1400的一俯視圖與一剖面圖。封裝體1400類似於在第9A與9B圖所示的封裝體900，其中類似的構件標上類似的元件符號，而在此不再重複類似構件的敘述。封裝體1400包括晶片結構1301，其中使用複數個接合結構903而將晶片結構1301貼附於一基底901。在一些實施例中，可使用類似於參考第10與11圖的前述的製程步驟來將晶片結構1301接合至基底901，在此不再重複敘述。在一些實施例中，在平面圖中，晶片結構1301的中心1303可以與基底901的中心重合。
請參考第1A、1B與15圖，在一些實施例中，省略密封環131B的形成。在這樣的實施例中，在將連接器137形成在晶圓100上之後，沿著相鄰的密封環131A之間的區域將晶片區域105、107、109、111分離，以形成個別的晶片結構，例如示於第15圖的晶片結構1501、1503、1505與1507。上述分離製程可包括一切割製程、一蝕刻製程、一雷射剝蝕製程、上述之組合或類似製程。密封環131A在分離的過程中保護晶片區域105、107、109、111的各種構件，並可減少或避免缺陷(例如：脫層、龜裂或類似缺陷)的形成。晶片結構1501對應於晶片區域105，晶片結構1503對應於晶片區域107，晶片結構1505對應於晶片區域109，而晶片結構1507對應於晶片區域111。
第16A與16B圖分別顯示關於一些實施例的一封裝體1600的一俯視圖與一剖面圖。第16A圖顯示封裝體1600的俯視圖，而第16B圖則顯示封裝體1600之沿著第16A圖所示的BB線的剖面圖。封裝體1600類似於在第9A與9B圖所示的封裝體900，其中類似的構件標上類似的元件符號，而在此不再重複類似構件的敘述。封裝體1400包括晶片結構1501、1503、1505與1507，其中使用複數個接合結構903而將晶片結構1501、1503、1505與1507貼附於一基底901。在一些實施例中，可使用類似於參考第10與11圖的前述的製程步驟來將晶片結構1501、1503、1505與1507接合至基底901，在此不再重複敘述。在一些實施例中，將晶片結構1501、1503、1505與1507排列在基底901上，而使沿著每個連接器137的一延伸的平面圖下的形狀的長軸之線1601，與基底901的中心1603相交。
第17A與17B圖分別顯示關於一些實施例的一封裝體1700的一俯視圖與一剖面圖。第17A圖顯示封裝體1700的俯視圖，而第17B圖則顯示封裝體1700之沿著第17A圖所示的BB線的剖面圖。封裝體1700類似於在第9A與9B圖所示的封裝體900，其中類似的構件標上類似的元件符號，而在此不再重複類似構件的敘述。除了晶片結構801之外，封裝體1700還包括複數個裝置1701，其中使用複數個接合結構1703而將裝置1701貼附於基底901。裝置1701可以是離散被動裝置(discrete passive devices；DPDs)、表面黏著裝置(surfaces mounted devices；SMDs)、上述之組合或類似裝置。裝置1701可包括一或多個被動裝置，例如電阻器、電容器、電感器、熔斷器、上述之組合或類似裝置。在一些實施例中，可使用類似於參考第10與11圖的前述的接合結構903的材料及方法來形成接合結構1703，在此不再重複敘述。在其他實施例中，接合結構1703可包括焊料球、塌陷高度控制晶片連接的凸塊、球閘陣列的球、化學鍍鎳化學鍍鈀與浸金技術形成的凸塊或類似構件。在一些實施例中，將晶片結構801排列在基底901上，而使沿著每個連接器137的一延伸的平面圖下的形狀的長軸之線1601，與基底901的中心1603相交。
第18A與18B圖分別顯示關於一些實施例的一封裝體1800的一俯視圖與一剖面圖。第18A圖顯示封裝體1800的俯視圖，而第18B圖則顯示封裝體1800之沿著第18A圖所示的BB線的剖面圖。封裝體1800類似於在第14A、14B、17A與17B圖所示的封裝體1400與1700，其中類似的構件標上類似的元件符號，而在此不再重複類似構件的敘述。在與封裝體1700區別方面，封裝體1800包括晶片結構1301而取代晶片結構801。在一些實施例中，將晶片結構1301排列在基底901上，而使沿著每個連接器137的一延伸的平面圖下的形狀的長軸之線1601，與基底901的中心1603相交。
第19圖為一流程圖，顯示關於一些實施例的晶片結構的形成方法1900。方法1900始於步驟1901，其中如參考第1A與1B圖的前述內容，在一晶圓(例如第1A與1B圖所示的晶圓100)上形成複數個晶片區(例如第1A與1B圖所示的晶片區105、107、109與111)。在步驟1903，如參考第1A與1B圖的前述內容，在上述晶圓形成複數個第一密封環(例如第1A與1B圖所示的密封環131A)與一第二密封環(例如第1A與1B圖所示的密封環131B)。在一些實施例中，每個上述複數個第一密封環圍繞上述晶片區中的對應的一個。在一些實施例中，上述第二密封環圍繞上述複數個第一密封環。在一些實施例中，上述複數個第一密封環與上述第二密封環是藉由相同的製程而同時形成。在這樣的實施例中，可使用相同的一或多個遮罩來同時圖形化上述複數個第一密封環的構件及上述第二密封環的構件。在替代性的實施例中，藉由不同的製程來形成上述複數個第一密封環與上述第二密封環。在這樣的實施例中，可以在不同時間使用不同遮罩，在形成上述第二密封環之前或之後，形成上述複數個第一密封環。在又其他替代性的實施例中，可省略上述第二密封環的形成。在步驟1905，在如參考第1A、1B與2至7圖的前述的內容，在上述晶圓的上方形成複數個連接器(例如第1A與1B圖所示的連接器137)。在步驟1907，如參考第1A、1B與8圖的前述內容，將上述晶圓分離成複數個晶片結構(例如第8圖所示的晶片結構801)。
關於一實施例，是提供一種半導體裝置，包括：一晶片結構，包括複數個晶片區；複數個第一密封環，每個上述第一密封環圍繞上述晶片區中的一對應的晶片區；一第二密封環，圍繞上述第一密封環；以及複數個連接器，接合於上述晶片結構，每個上述連接器具有一延伸的平面圖下的形狀，每個上述連接器的上述延伸的平面圖下的形狀的長軸指向上述晶片結構的中心。在一實施例中，上述半導體裝置更包括一基底，上述基底貼附於上述連接器。在一實施例中，以平面圖觀之，上述晶片結構的中心與上述基底的中心重合。在一實施例中，上述晶片結構的中心與被上述第二密封環圍繞的區域的中心重合。在一實施例中，每個上述連接器包括：一導體柱；以及一焊料層，在上述導體柱的上方。在一實施例中，以平面圖觀之，上述晶片區的一第一晶片區具有一第一區、上述晶片區的一第二晶片區具有一第二區，上述第二區異於上述第一區。在一實施例中，上述延伸的平面圖下的形狀為卵形、橢圓形、或跑道形狀。
關於另一實施例，是提供一種半導體裝置，包括：一晶片結構，包括一第一區與一第二區，上述第一區包括複數個第一晶片區，上述第二區包括複數個第二晶片區；複數個第一密封環，每個上述第一密封環圍繞上述第一晶片區與上述第二晶片區中的一對應的晶片區；一第二密封環，圍繞上述第一區與上述第二區；以及複數個連接器，接合於上述晶片結構，每個上述連接器具有一延伸的平面圖下的形狀，沿著每個上述連接器的上述延伸的平面圖下的形狀的長軸之線，與上述晶片結構的中心相交。在一實施例中，以平面圖觀之，上述第一區與上述第二區具有相同的形狀。在一實施例中，上述第二密封環圍繞上述第一密封環。在一實施例中，上述第一晶片區中的晶片區的數量與上述第二晶片區中的晶片區的數量相同。在一實施例中，上述半導體裝置更包括一基底，上述基底物理性地貼附於上述連接器。在一實施例中，以平面圖觀之，上述晶片結構的中心與上述基底的中心重合。在一實施例中，上述晶片結構的中心與被上述第二密封環圍繞的區域的中心重合。
關於又另一實施例，是提供一種半導體裝置的形成方法，包括：在一晶圓形成複數個單位區域，每個上述單位區域包括複數個晶片區；在上述晶圓形成複數個第一密封環，每個上述第一密封環圍繞上述晶片區中的一對應的晶片區；在上述晶圓形成複數個第二密封環，每個上述第二密封環圍繞上述單位區域中的一對應的單位區域；以及在上述晶圓的上方形成複數個連接器，每個上述連接器具有一延伸的平面圖下的形狀，每個上述連接器的上述延伸的平面圖下的形狀的長軸指向上述單位區域中的一對應的單位區域的中心。在一實施例中，上述半導體裝置的形成方法更包括：分離上述晶圓以形成複數個晶片區。在一實施例中，分離上述晶圓，包括：沿著上述晶圓之位於相鄰的第二密封環之間的區域，進行切割。在一實施例中，每個上述晶片區包括上述單位區域中的一對應的單位區域。在一實施例中，每個上述晶片區包括上述單位區域中的對應的一對單位區域。在一實施例中，上述半導體裝置的形成方法更包括：在上述晶圓形成複數個互連結構，其中上述互連結構、上述第一密封環及上述第二密封環是藉由相同的製程同時形成。
本發明實施例亦可包括其他構件及製程。例如，可包括測試結構，以輔助三維封裝或三維積體電路裝置的確認測試。上述測試結構可包括例如：複數個測試墊，形成於一重分布層(redistribution layer)中或一基底上，其用於三維封裝或三維積體電路裝置的測試、探針及或探針卡的使用等等。可以針對中間結構、亦可以針對最後完工的結構，施行上述確認測試。此外，此處揭露的結構及方法可用於與納入已知為良品的晶片(known good dies)的中間確認的測試方法組合，以增加良率並降低成本。
前述內文概述了許多實施例的特徵，使所屬技術領域中具有通常知識者可以從各個方面更佳地了解本發明實施例。所屬技術領域中具有通常知識者應可理解，且可輕易地以本發明實施例為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。所屬技術領域中具有通常知識者也應了解這些均等的結構並未背離本發明實施例的發明精神與範圍。在不背離本發明實施例的發明精神與範圍之前提下，可對本發明實施例進行各種改變、置換或修改。
100、1200:晶圓 101:單位區域 103:劃分線 105、107、109、111:晶片區 113、901:基底 115:主動及/或被動裝置 117:介電層 119:互連結構 121:導線 123:導通孔 125A、125B:密封環部 127、133、1003、1005:鈍化層 129A、129B、129C、1001:導體墊 131A、131B:密封環 135:緩衝層 137、907:連接器 139:凸塊下金屬層 141:導體柱 143、1007:焊料層 145、1203、1601、BB:線 147、803、1303、1603:中心 201、303:開口 301:圖形化的遮罩 801、1301、1501、1503、1505、1507:晶片結構 900、1400、1600、1700:封裝體 903、1703:接合結構 905:底膠材料 909:部分 1101:共通焊料層 1201:雙單位區域 1701:裝置 1900:方法 1901、1903、1905、1907:步驟 W1、W3、W5、W7、W9:第一寬度 W2、W4、W6、W8、W10:第二寬度
根據以下的詳細說明並配合所附圖式做完整揭露。應注意的是，根據本產業的一般作業，圖示並未必按照比例繪製。事實上，可能任意的放大或縮小元件的尺寸，以做清楚的說明。 第1A與1B圖分別顯示關於一些實施例的一晶圓的一俯視圖與一剖面圖。 第2圖為一剖面圖，顯示關於一些實施例的連接器的形成的中間階段。 第3圖為一剖面圖，顯示關於一些實施例的連接器的形成的中間階段。 第4圖為一剖面圖，顯示關於一些實施例的連接器的形成的中間階段。 第5圖為一剖面圖，顯示關於一些實施例的連接器的形成的中間階段。 第6圖為一剖面圖，顯示關於一些實施例的連接器的形成的中間階段。 第7圖為一剖面圖，顯示關於一些實施例的連接器的形成的中間階段。 第8圖為一俯視圖，顯示關於一些實施例的晶片結構。 第9A與9B圖分別顯示關於一些實施例的一封裝體的一俯視圖與一剖面圖。 第10圖為一剖面圖，顯示關於一些實施例的封裝體及接合結構的形成的中間階段。 第11圖為一剖面圖，顯示關於一些實施例的封裝體及接合結構的形成的中間階段。 第12A與12B圖分別顯示關於一些實施例的一晶圓的一俯視圖與一剖面圖。 第13圖為一俯視圖，顯示關於一些實施例的晶片結構。 第14A與14B圖分別顯示關於一些實施例的一封裝體的一俯視圖與一剖面圖。 第15圖顯示關於一些實施例的晶片結構的一系列的剖面圖。 第16A與16B圖分別顯示關於一些實施例的一封裝體的一俯視圖與一剖面圖。 第17A與17B圖分別顯示關於一些實施例的一封裝體的一俯視圖與一剖面圖。 第18A與18B圖分別顯示關於一些實施例的一封裝體的一俯視圖與一剖面圖。 第19圖為一流程圖，顯示關於一些實施例的晶片結構的形成方法。
100:晶圓
101:單位區域
103:劃分線
105、107、109、111:晶片區
131A、131B:密封環
133:鈍化層
137:連接器
145、BB:線
147:中心

Claims (17)

  1. 一種半導體裝置，包括：一晶片結構，包括複數個晶片區與在該些晶片區的上方的一緩衝層；複數個第一密封環，每個該些第一密封環圍繞該些晶片區中的一對應的晶片區，該些第一密封環的至少一個至少部分地被該緩衝層覆蓋；一第二密封環，圍繞該些第一密封環且未被該緩衝層覆蓋；以及複數個連接器，穿透該緩衝層而接合於該晶片結構，每個該些連接器具有一狹長形狀，每個該些連接器的狹長形狀的長軸指向該晶片結構的中心。
  2. 如申請專利範圍第1項所述之半導體裝置，更包括一基底，該基底貼附於該些連接器。
  3. 如申請專利範圍第2項所述之半導體裝置，其中以平面圖觀之，該晶片結構的中心與該基底的中心重合。
  4. 如申請專利範圍第2項所述之半導體裝置，其中藉由該些連接器電性連接該晶片結構與該基底。
  5. 如申請專利範圍第1至4項任一項所述之半導體裝置，其中該晶片結構的中心與被該第二密封環圍繞的區域的中心重合。
  6. 如申請專利範圍第1至4項任一項所述之半導體裝置，其中每個該些連接器包括：一導體柱；以及一焊料層，在該導體柱的上方。
  7. 一種半導體裝置，包括：一晶片結構，包括一第一區、一第二區及在該第一區與第二區的上方的一緩衝層，該第一區包括複數個第一晶片區，該第二區包括複數個第二晶片區；複數個第一密封環，每個該些第一密封環圍繞該些第一晶片區與該些第二 晶片區中的一對應的晶片區，該些第一密封環的至少一個至少部分地被該緩衝層覆蓋；一第二密封環，圍繞該第一區與該第二區且未被該緩衝層覆蓋；以及複數個連接器，穿透該緩衝層而接合於該晶片結構，每個該些連接器具有一狹長形狀，沿著每個該些連接器的狹長形狀的長軸之線，與該晶片結構的中心相交。
  8. 如申請專利範圍第7項所述之半導體裝置，其中該第二密封環圍繞該些第一密封環。
  9. 如申請專利範圍第7項所述之半導體裝置，更包括一基底，該基底物理性地貼附於該些連接器。
  10. 如申請專利範圍第9項所述之半導體裝置，其中以平面圖觀之，該晶片結構的中心與該基底的中心重合。
  11. 如申請專利範圍第7項所述之半導體裝置，其中該些連接器僅形成在該晶片結構的邊緣區域。
  12. 如申請專利範圍第7至11項任一項所述之半導體裝置，其中該晶片結構的中心與被該第二密封環圍繞的區域的中心重合。
  13. 一種半導體裝置的形成方法，包括：在一晶圓形成複數個單位區域，每個該些單位區域包括複數個晶片區；在該晶圓形成複數個第一密封環，每個該些第一密封環圍繞該些晶片區中的一對應的晶片區；在該晶圓形成複數個第二密封環，每個該些第二密封環圍繞該些單位區域中的一對應的單位區域；在該晶圓的上方形成一緩衝層，該緩衝層至少部份地覆蓋該些第一密封環的至少一個但未覆蓋該些第二密封環；以及 在該晶圓的上方形成複數個連接器，該些連接器穿透該緩衝層，每個該些連接器具有一狹長形狀，每個該些連接器的該狹長形狀的長軸指向該些單位區域中的一對應的單位區域的中心。
  14. 如申請專利範圍第13項所述之半導體裝置的形成方法，更包括分離該晶圓以形成複數個晶片區。
  15. 如申請專利範圍第14項所述之半導體裝置的形成方法，其中分離該晶圓包括沿著該晶圓之位於相鄰的第二密封環之間的區域進行切割。
  16. 如申請專利範圍第14項所述之半導體裝置的形成方法，其中每個該些晶片區包括該些單位區域中的一對應的單位區域或對應的一對單位區域。
  17. 如申請專利範圍第13至16項任一項所述之半導體裝置的形成方法，更包括在該晶圓形成複數個互連結構，其中該些互連結構、該些第一密封環及該些第二密封環是藉由相同的製程同時形成。
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