TWI697887B - Display device - Google Patents

Abstract

A display device includes a display panel and a driving circuit. The display panel includes a first display region and a second display region, the first display region is coupled to a plurality of first driving lines, the second display region is coupled to a plurality of second driving lines, wherein a first load provided by a plurality of first pixels corresponding to the first driving lines is larger than a second load provided by a plurality of second pixels corresponding to the second driving lines. The driving circuit provides a plurality of first driving signals to the first driving lines and provides a plurality of second driving signals to the second driving lines respectively, wherein the driving circuit sets electric characteristics of the first driving signals and the second driving signals respectively according to the loading of the first load and the second load.

Description

Display device

The present invention relates to a display device, and more particularly to a display device that makes the display image brightness of the display panel uniform.

In today’s display panels, in order to respond to the diversity of products and provide customized designs, various display panels of different shapes have gradually been developed. Different from the traditional rectangular frame design, it uses a curved or streamlined frame design. As a result, display panels with a variety of shapes such as notch shapes or rounded corners have been produced.

However, the shape of the notch and the rounded corner shape on the display panel will affect the display panel. Because the source driving lines and the gate driving lines on the display panel are in the general display area (that is, the non-notch shape and Non-rounded corners of the display area), the number of pixels that need to be driven is relatively large, with a large load, which will cause the brightness of the area to be relatively low, and the notch shape or rounded corner shape of the display panel The display area nearby, because each source drive line and each gate drive line need to drive a relatively small number of pixels, has a small load, so that the shape of the notch or rounded corner of the display panel The brightness of the display area is higher than that of the general display area, which in turn causes the uneven brightness of the display image of the display panel (Mura).

The present invention provides a display device, and particularly relates to a display device that makes the brightness of the displayed image of the display panel uniform.

The display device of the present invention includes a display panel and a driving circuit. The display panel includes a first display area and a second display area. The first display area is coupled to a plurality of first driving lines, and the second display area is coupled to a plurality of second driving lines, wherein each first driving line corresponds to a plurality of The first load provided by the first pixel is greater than the second load provided by the plurality of second pixels corresponding to each second driving line. The driving circuit is coupled to a plurality of first driving lines and a plurality of second driving lines for respectively providing a plurality of first driving signals to the plurality of first driving lines, and respectively providing a plurality of second driving signals to the plurality of second driving lines, Wherein, the driving circuit respectively sets the electrical characteristics of the plurality of first driving signals and the plurality of second driving signals according to the sizes of the first load and the second load.

Based on the above, the driving circuit of the present invention can respectively set a plurality of first driving signals provided to the first display area and provide the first load in the first display area and the second load in the second display area. The electrical characteristics of the plurality of second driving signals to the second display area are used to set the brightness of the first display area and the second display area respectively, so as to improve the uniformity of the overall brightness of the display panel, so that the display panel can display images The purpose of uniform brightness and increase the quality of display.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Please refer to FIG. 1. FIG. 1 is a circuit block diagram of a display device according to an embodiment of the present invention. The display device 100 includes a display panel 110, a source driving circuit 120, and a gate driving circuit 130. The display panel 110 includes a first display area 111 and a second display area 112. The first display area 111 is coupled to a plurality of gate driving lines (for example, gate driving lines DL3 to DLn) and a plurality of source driving lines (for example, Source driving lines SL1~SLn), the second display area 112 is coupled to a plurality of gate driving lines (for example, gate driving lines DL1, DL2) and a plurality of source driving lines (for example, source driving lines SL1, SL2) , SLn-1, SLn). It should be noted that, in order to simplify the description, this embodiment only shows that two gate driving lines DL1, DL2 and four source driving lines SL1, SL2, SLn-1, SLn are coupled to the second display area 112 as In an exemplary embodiment, the present invention does not limit the number of source driving lines and gate driving lines coupled to the second display area 112. Those skilled in the art can set the coupling according to actual application conditions. The number of source driving lines and gate driving lines to the second display area 112.

The source driving circuit 120 is coupled to the source driving lines SL1~SLn for providing a plurality of source driving signals VS1, VS2, VSn-1, VSn to the source driving line SL1 coupled to the second display area 112, respectively , SL2, SLn-1, SLn, and respectively provide a plurality of source driving signals VS1~VSn to the source driving lines SL1~SLn coupled to the first display area 111.

The gate driving circuit 130 is coupled to the gate driving lines DL1 to DLn to provide a plurality of gate driving signals VG1, VG2 to the gate driving lines DL1, DL2 coupled to the second display area 112, and respectively provide A plurality of gate driving signals VG3 ˜VGn is coupled to the gate driving lines DL3 ˜DLn of the first display area 111.

In addition, in the display panel 110, each gate driving line DL3 ~ DLn corresponding to the first load provided by the plurality of first pixels in the first display area 111 is greater than that of each gate driving line DL1, DL2 corresponding to the second The second load provided by the plurality of second pixels in the display area 112. In detail, the first display area 111 has a plurality of first pixels, the second display area 112 has a plurality of second pixels, and the number of the first pixels is greater than the number of the second pixels, that is, The first load provided by the plurality of first pixels is greater than the second load provided by the plurality of second pixels. Therefore, the load when the gate driving lines DL3~DLn coupled to the first display area 111 drive the first pixel is greater than the gate driving lines DL1, DL2 coupled to the second display area 112 to drive the second picture. Therefore, the voltage values of the gate drive signals VG1 and VG2 in the second display area 112 near the notch shape of the display panel 110 will be greater than those of the gate drive signals VG3~VGn in the general display area. Voltage value.

It is worth mentioning that the gate driving circuit 130 and/or the source driving circuit 120 of this embodiment will set a plurality of source driving signals (for example, source driving signals) according to the magnitude of the first load and the second load. VS1~VSn) and/or electrical characteristics of a plurality of gate drive signals (for example, gate drive signals VG1~VGn), thereby setting the brightness of the first display area 111 and the second display area 112, so that the display panel The uniformity of the overall brightness of the 110 is improved to achieve the purpose of uniformizing the brightness of the displayed image on the display panel 110.

To describe in detail the embodiment of the present invention for setting the electrical characteristics of each source driving signal and/or each gate driving signal, please refer to FIGS. 1 and 2A simultaneously. FIG. 2A shows the setting rotation of the embodiment of the present invention in FIG. 1 Schematic diagram of the gate drive signal waveform of the rate implementation mode. In this embodiment, the gate driving circuit 130 sets the slew rate of multiple gate driving signals (for example, the gate driving signals VG1 and VG2) according to the magnitude of the first load and the second load. Furthermore, the gate drive circuit 130 of this embodiment sets the slew rate of the multiple gate drive signals VG1 and VG2 so that the slew rate of each gate drive signal VG1 and VG2 is lower than the original slew rate ( For example, 100%). For example, when the gate drive circuit 130 sets the slew rate of each gate drive signal VG1 and VG2 to 75%, the voltage value of the rising edge of each gate drive signal VG1 and VG2 will decrease , And will decrease to lower than the voltage value of each gate drive signal VG1 and VG2 when the original slew rate is 100%.

At the same time, the voltage value of the falling edge of each gate driving signal VG1 and VG2 will increase, and will increase to be higher than the voltage value of each gate driving signal VG1 and VG2 when the original slew rate is 100%, so that each gate The voltage levels of the rising edges of the gate drive signals VG1 and VG2 sequentially increase from the disable voltage level VDis to the enable voltage level VEn, and the voltage levels of the falling edges of the gate drive signals VG1 and VG2 are changed from the same The energy voltage level VEn is sequentially reduced to the disable voltage level VDis. It should be noted that the embodiment in which the slew rate of each gate driving signal VG1 and VG2 is set to 50% and 25% is similar to the embodiment in which the slew rate is set to 75%, and will not be repeated here.

In this way, the embodiment of the present invention can set the slew rate of the gate driving signals VG1 and VG2 coupled to the second display area 112 to distort the voltage waveforms of the gate driving signals VG1 and VG2 (even if each The voltage waveforms of the gate drive signals VG1 and VG2 are not ideal square waves), and the effective voltage values of the gate drive signals VG1 and VG2 are reduced, so that the voltage waveforms of the gate drive signals VG1 and VG2 and the gate drive The voltage waveforms of the signals VG3~VGn are similar. Accordingly, the brightness of the second display area 112 is set to be substantially equal to the brightness of the first display area 111, so as to improve the uniformity of the overall brightness of the display panel 110 to achieve the brightness of the image displayed on the display panel 110 The purpose of uniformity and increase the quality of the display.

On the other hand, please refer to FIG. 1 and FIG. 2B synchronously. FIG. 2B is a schematic diagram of the gate driving signal waveform of the voltage level setting implementation of the embodiment of FIG. 1 of the present invention. In this embodiment, the gate driving circuit 130 divides the gate driving signals VG1 and VG2 into multiple time intervals (for example, time intervals T1 to T5), and sets multiple voltage levels (for example, voltage levels). VGND, voltage level VSSp, enable voltage level VEn, disable voltage level VDis, and voltage level VSSn), so that each gate drive signal VG1 and VG2 can be maintained at multiple corresponding time intervals. Voltage level. In addition, the gate driving circuit 130 will set a plurality of voltage levels and the size of at least one of the plurality of time intervals according to the size of the first load and the second load, so that the voltage of each gate driving signal VG1 and VG2 is Each time interval T1 to T5 has a plurality of different voltage levels.

In detail, the gate drive circuit 130 of this embodiment divides the voltage waveforms of the gate drive signals VG1 and VG2 into time intervals T1 to T5 according to the magnitude of the first load and the second load, and sets each gate The voltage levels of the driving signals VG1 and VG2 in each time interval. For example, in the time interval T1, the gate driving circuit 130 will set so that the voltage levels of the gate driving signals VG1 and VG2 are maintained at the voltage level VGND In the time interval T2 after the time interval T1, the voltage levels of the gate driving signals VG1 and VG2 are maintained at the voltage level VSSp.

Then, in the time interval T3 after the time interval T2, the gate driving circuit 130 is set to maintain the voltage levels of the gate driving signals VG1 and VG2 at the enabling voltage level VEn, and at the time after the time interval T3 In the interval T4, the voltage levels of the gate driving signals VG1 and VG2 are maintained at the voltage level VGND, and in the time interval T5 after the time interval T4, the voltage levels of the gate driving signals VG1 and VG2 are maintained At the voltage level VSSn, the voltage levels of the rising edges of the gate drive signals VG1 and VG2 are sequentially increased from the disable voltage level VDis to the enable voltage level VEn, and the gate drive signals VG1 , The voltage level of the falling edge of VG2 decreases sequentially from the enable voltage level VEn to the disable voltage level VDis, where the voltage level VSSn is higher than the disable voltage level VDis, and the voltage level VGND is higher than the voltage level VSSn, the voltage level VSSp is higher than the voltage level VGND, and the enabling voltage level VEn is higher than the voltage level VSSp. It should be noted that in order to simplify the description, this embodiment only shows five time intervals and five different voltage levels as exemplary embodiments. However, in fact, those with ordinary knowledge in the art can adjust each according to actual application conditions. The number of time intervals, the size of time intervals, the number of voltage levels, and the size of voltage levels in the voltage waveform of the gate driving signal are not limited by the present invention.

In this way, in the embodiment of the present invention, the gate driving signals VG1 and VG2 are set so that the gate driving signals VG1 and VG2 are maintained at corresponding voltage levels in the time intervals T1 to T5, respectively, so as to enable The voltage waveform of each gate drive signal VG1, VG2 is distorted, and the effective voltage value of each gate drive signal VG1, VG2 is reduced, so that the voltage waveform of each gate drive signal VG1, VG2 and the voltage of each gate drive signal VG3~VGn The waveform is similar, and the brightness of the second display area 112 is set accordingly to improve the uniformity of the overall brightness of the display panel 110, achieve the purpose of uniformizing the brightness of the displayed image of the display panel 110, and increase the display quality.

It is worth mentioning that the present invention also mentions that the display panel in the display device may further include a third display area. Please refer to FIG. 3A. FIG. 3A shows a circuit block diagram of a display device according to another embodiment of the present invention. . In this embodiment, the display device 300 includes a display panel 310, a source driving circuit 320, and a gate driving circuit 330. The difference from the embodiment in FIG. 1 is that the display panel 310 includes a first display area 311, a second display area 312, and a third display area 313. The first display area 311 is coupled to a plurality of gate drive lines DL3~DLn-2. And a plurality of source driving lines SL1~SLn, the second display area 312 is coupled to a plurality of gate driving lines DL1, DL2 and a plurality of source driving lines SL1, SL2, SLn-1, SLn, and the third display area 313 is coupled to Connect multiple gate drive lines DLn-1, DLn and multiple source drive lines SL1, SL2, SLn-1, SLn. It should be noted that, in order to simplify the description, this embodiment only shows two gate drive lines DLn-1, DLn and four source drive lines SL1, SL2, SLn-1, SLn coupled to the third display area 313. As an exemplary embodiment, however, the present invention does not actually limit the number of source drive lines and gate drive lines coupled to the third display area 313. Those skilled in the art can rely on actual application conditions. , Set the number of source driving lines and gate driving lines coupled to the third display area 313.

In addition, the third display area 313 of the display panel 310 has a plurality of third pixels, and the gate driving circuit 330 and/or the source driving circuit 320 will depend on the magnitude of the first load, the second load, and the third load. , Respectively setting the gate drive signal and/or multiple source drive signals coupled to the first display area 311, the gate drive signal and/or multiple source drive signals coupled to the second display area 312, and The electrical characteristics of the multiple gate drive signals and/or multiple source drive signals coupled to the third display area 313, thereby setting the display of the first display area 311, the second display area 312, and the third display area 313 The image brightness improves the uniformity of the displayed image brightness of the first display area 311, the second display area 312, and the third display area 313, so as to achieve the purpose of uniformizing the display image brightness of the display panel 310.

In addition, the present invention also mentions that the display panel 310 of the embodiment of FIG. 3A has another embodiment. Please refer to FIGS. 3A and 3B simultaneously. FIG. 3B shows another embodiment of the display panel of the embodiment of FIG. 3A of the present invention. Schematic. In this embodiment, the display panel 310 can divide the display area in a vertical manner. The display panel 310 is divided into a first display area 311a, a second display area 312a, and a third display area 313a. The method of dividing the display area is not limited, nor does it limit the size of the divided area, that is, those with ordinary knowledge in the art can adjust the first display area 311a, the second display area 312a, and the second display area 311a according to the actual application. Three display area 313a shape and size. In addition, the display panel 310 of the present embodiment is coupled to a plurality of driving lines, and the gate driving line or the source driving line can be selected according to the division method of the display area to connect the plurality of driving lines provided to the first display area 311a. The electrical characteristics of the first driving signal, the plurality of second driving signals provided to the second display area 312a, and the plurality of third driving signals provided to the third display area 313a are set.

In detail, the embodiment of the present invention can be set by driving lines (for example, driving lines LIN1~LINn) in the same extending direction as the display area. For example, when the driving lines LIN1~LINn are gate driving lines, The gate drive signals transmitted to the first display area 311a, the second display area 312a, and the third display area 313a are set to set the display image brightness of each display area. In contrast, when the driving lines LIN1~LINn are source driving lines, the source driving signals transmitted to the first display area 311a, the second display area 312a, and the third display area 313a can be set, thereby setting each The brightness of the displayed image in the display area. That is, the driving lines LIN1 to LINn of this embodiment may be gate driving lines or source driving lines. Those with ordinary knowledge in the art can make adjustments according to actual application conditions, and the present invention is not limited thereto.

On the other hand, the implementation of setting the gate drive signal of the embodiment of FIG. 2A and FIG. 2B of the present invention can be applied to the display device 300 of the embodiment of FIG. 3A and FIG. 3B, and its operation principle and operation method are similar to the aforementioned embodiment of FIG. , I will not repeat them here.

Please refer to FIG. 1 and FIG. 4A synchronously. FIG. 4A shows a schematic diagram of a driving signal waveform of the embodiment of the present invention for setting the gate driving signal enable time. In this embodiment, the gate driving circuit 130 sets the gate driving signal VG (for example, the gate driving signals VG3~VGn) transmitted to the first display area 111 according to the size of the first load and the second load. The enable time of at least one of the gate driving signals VG (for example, the gate driving signals VG1, VG2) transmitted to the second display area 112 to set the plurality of first pixels in the first display area 111 and The charging time of the multiple second pixels in the second display area 112.

In detail, the gate driving circuit 130 of this embodiment sets the gate driving signals VG1 and VG2 coupled to the second display area 112 according to the size of the first load and the second load, so that each gate The enabling time of the electrode driving signals VG1 and VG2 is shortened by a time TSDT1, thereby reducing the charging time for each second pixel to receive the data voltage VS (for example, the source driving signals VS1, VS2, VSn-1, VSn). The brightness of the displayed image in the second display area 112 is reduced, so that the brightness of the displayed image in the first display area 111 and the second display area 112 are substantially the same, so that the brightness of the displayed image on the display panel 110 is uniform.

It is worth mentioning that the present invention also mentions that while setting the gate driving signals VG1 and VG2 of the second display area 112, the gate driving circuit 130 can also be based on the size of the first load and the second load. The gate driving signals VG3~VGn coupled to the first display area 111 are set so that the enabling time of each gate driving signal VG3~VGn is shortened by a time TSDT2, so that each first pixel receives the data voltage VS (For example, the charging time of the source driving signals VS1~VSn) is reduced, so that the display image brightness of the first display area 111 and the second display area 112 can be set at the same time, wherein the time TSDT1 will be greater than the time TSDT2, that is, In this embodiment, by shortening the enabling time of the second display area 112 with higher brightness (that is, the load is smaller), the brightness of the second display area 112 is reduced by a greater extent, and by reducing the original brightness ( That is, the first display area 111 with higher load shortens the shorter time TSDT2, which reduces the brightness of the first display area 111 to a smaller extent. In this way, the second display area 112 and the first display area 111 can be The brightness uniformity is improved to achieve the purpose of uniformizing the brightness of the displayed image of the display panel 110.

In addition, please refer to FIGS. 3A and 4B simultaneously. FIG. 4B is a schematic diagram of the driving signal waveform of the embodiment of setting the gate driving signal enable time in the embodiment of FIG. 3A of the present invention. The difference from the embodiment in FIG. 1 is that the gate driving circuit 330 of this embodiment sets the gate driving signal VG in the first display area 311 (for example, according to the magnitude of the first load, the second load, and the third load). Are the gate drive signals VG3~VGn-2), the gate drive signal VG in the second display area 312 (for example, the gate drive signals VG1 and VG2), and the gate drive signal VG in the third display area 313 (for example It is the enable time of at least one of the gate drive signals VGn-1, VGn). In other words, the gate driving circuit 330 can set the gate driving signals VGn-1, VGn according to the magnitude of the first load, the second load, and the third load, so that the gate driving signals VGn-1, The enabling time of VGn is shortened by a time TSDT3 to set the charging time for a plurality of third pixels in the third display area 313 to receive the data voltage VS (for example, the source driving signals VS1, VS2, VSn-1, VSn) That is, in this embodiment, the charging time of each first pixel, each second pixel, and each third pixel can be set at the same time, or only the charging time of each second pixel and each third pixel can be set at the same time. It is also possible to individually set each second pixel or only the charging voltage of each third pixel separately. Those with ordinary knowledge in the art can, according to the actual application, make a difference to each first pixel, each second pixel and each The charging time of the third pixel is set, which is not limited by the present invention.

In addition, it should be noted that the present invention does not limit the size of the third load and the second load. Those skilled in the art can determine whether the time TSDT3 is greater than the time according to the size of the third load and the second load in actual application. TSDT1 is used to control the brightness of the displayed image in the third display area 313 and the second display area 312, so as to improve the brightness uniformity of the first display area 311, the second display area 312, and the third display area 313 to achieve The brightness of the displayed image of the display panel 110 is uniform.

Please refer to FIG. 1 and FIG. 5A synchronously. FIG. 5A is a schematic diagram of the driving signal waveform of the embodiment of setting the enable time of the switch control signal in the embodiment of FIG. 1 of the present invention. In this embodiment, the display panel 110 in the display device 100 further includes a plurality of first multiplexers and a plurality of second multiplexers. The plurality of first multiplexers include a plurality of first switches to respectively receive a plurality of first switch control signals (for example, the first switch control signals VMR1, VMG1, VMB1), and each first multiplexer corresponds to the second Display area 112. The plurality of second multiplexers include a plurality of second switches to respectively receive a plurality of second switch control signals (for example, the second switch control signals VMR2, VMG2, VMB2), and each second multiplexer corresponds to the first switch control signal. One display area 111. In addition, the source driving circuit 120 includes a timing controller, which is coupled to each first multiplexer and each second multiplexer, for respectively providing each first switch control signal VMR1, VMG1, VMB1 and each second switch Control signals VMR2, VMG2, VMB2 to each first switch and each second switch.

The source driving circuit 120 will set the first switch control signals VMR1, VMG1, VMB1 transmitted to the second display area 112 and the settings transmitted to each of the first display area 111 according to the size of the first load and the second load. The activation time of at least one of the second switch control signals VMR2, VMG2, and VMB2 to set the charging of the plurality of first pixels in the first display area 111 and the plurality of second pixels in the second display area 112 time. To explain in detail, the source driving circuit 120 of this embodiment will set each first switch control signal VMR1, VMG1, VMB1 according to the size of the first load and the second load, so that each first switch control signal VMR1, The enabling time of VMG1 and VMB1 are all shortened by a time TRGB1, thereby reducing the time that each first switch in each first multiplexer is turned on to reduce the data voltage VS (for example, the source driving signals VS1, VS2, VSn -1. The charging time of the data (such as data Rdata, Gdata, Bdata) in VSn) for each second pixel, thereby reducing the brightness of the image displayed in the second display area 112, so that the first display area 111 and the The brightness of the displayed image of the two display areas 112 is substantially the same, so that the brightness of the displayed image of the display panel 110 is uniform.

It is worth mentioning that the present invention also mentions that while the source driving circuit 120 sets the first switch control signals VMR1, VMG1, and VMB1 to be transmitted to the second display area 112, the source driving circuit 120 can also be based on The magnitudes of the first load and the second load are set for each second switch control signal VMR2, VMG2, VMB2 transmitted to the first display area 111, so that the enable time of each second switch control signal VMR2, VMG2, VMB2 The time TRGB2 is shortened to shorten the charging time of the data Rdata, Gdata, and Bdata in the data voltage VS (for example, the source drive signal VS1~VSn) received by each first pixel, so that the first display area 111 and The brightness of the displayed image in the second display area 112, where the time TRGB1 is greater than the time TRGB2, that is to say, the first switch control signals VMR1 and VMR1 in the second display area 112 with higher brightness (that is, less load) The enabling time of VMG1 and VMB1 is shortened for a longer time TRGB1 to reduce the brightness of a larger magnitude, and the second switch control signals VMR2 and VMG2 in the first display area 111 with lower brightness (that is, larger load) are reduced. The enabling time of VMB2 is shortened by a shorter time TRGB2, so as to reduce the brightness of a smaller range, thereby improving the brightness uniformity of the second display area 112 and the first display area 111, so as to achieve the purpose of making the display panel 110 uniformly emit light.

In addition, please refer to FIGS. 3A and 5B simultaneously. FIG. 5B is a schematic diagram of the driving signal waveform of the embodiment of setting the enable time of the switch control signal in the embodiment of FIG. 3A of the present invention. The difference from the embodiment in FIG. 1 is that the display panel 310 in the display device 300 of this embodiment further includes a plurality of third multiplexers. The plurality of third multiplexers include a plurality of third switches to respectively receive a plurality of third switch control signals (for example, third switch control signals VMR3, VMG3, VMB3), and each third multiplexer corresponds to the third switch control signal. Display area 313. The source driving circuit 320 sets the first switch control signals VMR1, VMG1, VMB1, and VMB1 transmitted to the second display area 312 according to the size of the first load, the second load, and the third load. The activation time of at least one of the second switch control signals VMR2, VMG2, VMB2 and the third switch control signals VMR3, VMG3, VMB3 transmitted to the third display area 313. In other words, the source driving circuit 320 can set the third switch control signals VMR3, VMG3, VMB3 according to the size of the first load, the second load, and the third load, so that the third switch control signals VMR3, The enabling time of VMG3 and VMB3 is shortened by a time TRGB3 to reduce the data Rdata in the third pixel receiving data voltage VS (for example, source driving signals VS1, VS2, VSn-1, VSn) in the third display area 313 , Gdata, Bdata charging time, that is, in this embodiment, the charging time of each first pixel, each second pixel, and each third pixel can be set at the same time, or only the second pixel and each third pixel can be set at the same time. The charging time of the three pixels can also be set individually for each second pixel or only the charging voltage of each third pixel. Those with ordinary knowledge in the art can compare each first pixel, The charging time of each second pixel and each third pixel is set, which is not limited by the present invention.

In addition, it should be noted that the present invention does not limit the size of the third load and the second load. Those skilled in the art can determine whether the time TRGB3 is greater than the time according to the size of the third load and the second load in actual application. TRGB1, to control the display image brightness of the third display area 313 and the second display area 312, thereby improving the brightness uniformity of the first display area 311, the second display area 312, and the third display area 313 to make the display panel The 110 display image brightness is uniform.

Please refer to FIG. 1 and FIG. 6A synchronously. FIG. 6A is a schematic diagram of the source driving signal waveform of the implementation of setting the data voltage in the embodiment of FIG. 1 of the present invention. In this embodiment, each source driving signal VS (for example, the source driving signals VS1~VSn) correspondingly drives the second display area 112 in the first time interval, and correspondingly drives the first display area in the second time interval 111. The source driving circuit 120 will set each source driving signal VS1~VSn to the voltage level Vp- in the first time interval according to the size of the first load in the first display area 111 and the second load in the second display area 112. DV1, and set each source driving signal VS1~VSn to the voltage level Vp in the second time interval, where the voltage level Vp-DV1 and the voltage level Vp have an offset value DV1.

To explain in detail, in one screen period of this embodiment, the time interval from the gate driving signals VG1, VG2 provided by the gate driving lines DL1 and DL2 to the second display area 112 is the first time interval, and the gate The time interval during which the driving lines DL3 ˜DLn provide the gate driving signals VG3 ˜VGn to the first display area 111 is the second time interval. The source driving circuit 120 will set the voltage level of the data voltage (that is, the source driving signals VS1~VSn) to be charged to each first pixel and each second pixel according to the size of the first load and the second load, For example, the source driving circuit 120 sets the source driving signals VS1~VSn to the voltage level Vp-DV1 in the first time interval, so that the source driving signals VS1~VSn are no longer in the first time interval. The original normal voltage level Vp reduces the charging voltage for each second pixel of each source driving signal VS1~VSn. Then, in a second time interval after the first time interval, the source driving circuit 120 will set each source driving signal VS1~VSn to the normal voltage level Vp in the second time interval, so that it can be in the second time interval The voltage level Vp is used to charge each first pixel. In this way, the image display brightness of the second display area 112 can be reduced to substantially equal to the image display brightness of the first display area 111, and the reduction range of the image display brightness of the second display area 112 can be transmitted through The offset value DV1 is set to control. Those skilled in the art can set the magnitude of the offset value DV1 between the voltage level Vp-DV1 and the voltage level Vp according to the actual application. The present invention does not limit this .

It should be noted that when the polarity of each first pixel and each second pixel is reversed, the source drive circuit 120 will set the source drive signals VS1~VSn to the voltage level Vn+DV3 in the first time interval. , So that the source driving signals VS1~VSn are no longer at the original normal voltage level Vn in the first time interval, thereby reducing the charging voltage of the source driving signals VS1~VSn to each second pixel, And in the second time interval after the first time interval, the source driving circuit 120 sets the source driving signals VS1~VSn to the normal voltage level Vn in the second time interval, and accordingly, the voltage level Vn can be used in the second time interval. The voltage level Vn is used to charge each first pixel. Since the voltage level Vn is a negative voltage, the absolute value of the voltage level Vn will be greater than the absolute value of the voltage level Vn+DV3, that is, the absolute value of each first pixel The charging voltage will be greater than the charging voltage of each second pixel, so that the image display brightness of the second display area 112 is reduced, and is reduced to substantially equal to the image display brightness of the first display area 111, wherein the offset can be set The value DV3 controls the reduction of the image display brightness of the second display area 112. Those skilled in the art can set the voltage level Vn+DV3 and the offset value DV3 between the voltage level Vn according to actual application conditions. The present invention does not limit this. In addition, the magnitudes of the offset value DV3 and the offset value DV1 may be the same or different, and those with ordinary knowledge in the art can also make adjustments according to actual application conditions, which is not limited by the present invention.

In this way, in this embodiment, by setting the voltage level of the data voltage (ie, the source driving signal VS) received by each second pixel in the second display area 112, the charging voltage of each second pixel The absolute value of the voltage level is less than the absolute value of the voltage level of the charging voltage of each first pixel, thereby reducing the brightness of the image displayed in the second display area 112, thereby allowing the second display area 112 and the first display area 111 The brightness uniformity is improved to achieve the purpose of making the display panel 110 emit light uniformly.

Please refer to FIGS. 3A and 6B synchronously. FIG. 6B is a schematic diagram of the driving signal waveform of the embodiment of setting the data voltage in the embodiment of FIG. 3A of the present invention. The difference from the embodiment in FIG. 1 is that the source driving signals VS (for example, the source driving signals VS1~VSn) in this embodiment drive the second display area 312 in the first time interval, and in the second time The interval corresponds to driving the first display area 311, and the third time interval corresponds to driving the third display area 313. The source driving circuit 320 sets each source driving signal VS1~VSn to the voltage level Vp-DV1 in the first time interval according to the magnitude of the first load, the second load and the third load, and sets each source driving signal VS1 ~VSn is the voltage level Vp in the second time interval, and each source drive signal VS1~VSn is set to the voltage level Vp-DV2 in the third time interval, where the voltage level Vp-DV1 and the voltage level Vp have a The offset value DV1, and the voltage level Vp-DV2 and the voltage level Vp have an offset value DV2.

To explain in detail, in one screen period of this embodiment, the time period from the gate driving signals VG1 and VG2 provided by the gate driving lines DL1 and DL2 to the second display area 312 is the first time period, and the gate The time interval when the driving lines DL3~DLn-2 provide the gate driving signals VG3~VGn-2 to the first display area 311 is the second time interval, and the gate driving lines DLn-1~DLn provide the gate driving signals The time interval from VGn-1 to VGn to the third display area 313 is the third time interval. The source driving circuit 320 sets the data voltage to charge each first pixel, each second pixel, and each third pixel according to the size of the first load, the second load, and the third load (that is, the source driving The voltage levels of the signals VS1~VSn). For example, in the present embodiment, the source driving circuit 320 sets the source driving signals VS1~VSn to be in the third time interval after the second time interval. The time interval is the voltage level Vp-DV2, so that the source driving signals VS1~VSn are no longer the original normal voltage level Vp in the third time interval, thereby reducing the pair of source driving signals VS1~VSn. The charging voltage of the third pixel.

In this way, each third pixel can be charged at the voltage level Vp-DV2 in the third time interval, so as to reduce the image display brightness of the third display area 313 to substantially equal to that of the first display area 311. For the purpose of image display brightness, the reduction range of the image display brightness of the third display area 313 can be controlled by setting the offset value DV2. Those skilled in the art can set the voltage level Vp-DV2 according to the actual application. The magnitude of the offset value DV2 between and the voltage level Vp is not limited by the present invention.

It should be noted that when the polarity of each first pixel, each second pixel, and each third pixel is reversed, the source driving circuit 320 will set the source driving signals VS1~VSn to be in the third time interval. Voltage level Vn+DV4, so that the source drive signals VS1~VSn are no longer at the original normal voltage level Vn in the third time interval, thereby reducing the effect of each source drive signal VS1~VSn on each third picture Since the voltage level Vn is a negative voltage, the absolute value of the voltage level Vn will be greater than the absolute value of the voltage level Vn+DV4, that is, the charging voltage of each first pixel will be greater than that of each third pixel. According to the charging voltage of the element, the image display brightness of the third display area 313 is reduced, and is reduced to substantially equal to the image display brightness of the first display area 111. The third display area can be controlled by setting the offset value DV4. For the reduction range of the image display brightness of 313, those skilled in the art can set the voltage level Vn+DV4 and the offset value DV4 between the voltage level Vn according to the actual application. The present invention does not add to this. limited. In addition, the magnitudes of the offset value DV4 and the offset value DV2 may be the same or different, and those with ordinary knowledge in the art can also set according to actual application conditions, which is not limited by the present invention.

On the other hand, the operation mode of the source driving circuit 320 setting the voltage levels of the source driving signals VS1~VSn in the first time interval and the second time interval is similar to the foregoing embodiment of FIG. 1, and will not be repeated here. .

Please refer to FIG. 1 and FIG. 7A synchronously. FIG. 7A is a schematic diagram of the driving signal waveform of the implementation of setting the common voltage in the embodiment of FIG. 1 of the present invention. In this embodiment, each source driving signal VS (for example, the source driving signals VS1~VSn) correspondingly drives the second display area 112 in the first time interval, and correspondingly drives the first display area in the second time interval 111. The source driving circuit 120 will set the common voltage VCOM to the voltage level VCOM1+DVa in the first time interval according to the size of the first load of the first display area 111 and the second load of the second display area 112, and set the common The voltage VCOM is the voltage level VCOM1 in the second time interval, where the voltage levels VCOM1+DVa and VCOM1 have an offset value DVa.

To explain in detail, in one screen period of this embodiment, the time interval from the gate driving signals VG1, VG2 provided by the gate driving lines DL1 and DL2 to the second display area 112 is the first time interval, and the gate The time interval during which the driving lines DL3 ˜DLn provide the gate driving signals VG3 ˜VGn to the first display area 111 is the second time interval. The source driving circuit 120 sets the voltage level of the common voltage VCOM when charging each first pixel and each second pixel according to the size of the first load and the second load. For example, the source driving circuit 120 Set the voltage level of the common voltage VCOM to the voltage level VCOM1+DVa in the first time interval, so that the voltage level of the common voltage VCOM is no longer the original normal voltage level VCOM1 in the first time interval, thereby reducing The charging voltage of each source driving signal VS1~VSn to each second pixel (the voltage value of the charging voltage at this time is the voltage level Vp minus the voltage level VCOM1+DVa). Then, in a second time interval after the first time interval, the source driving circuit 120 sets the voltage level of the common voltage VCOM to the voltage level VCOM1 in the second time interval. In this way, each first pixel in the second time interval will have a higher voltage value of the charging voltage (the voltage value of the charging voltage at this time is the voltage level Vp minus the voltage level VCOM1). The purpose of reducing the image display brightness of the second display area 112 to substantially equal to the image display brightness of the first display area 111, and the reduction of the image display brightness of the second display area 112 can be controlled by setting the offset value DVa Those skilled in the art can set the voltage level VCOM1+DVa and the offset value DVa between the voltage level VCOM1 according to actual application conditions, which is not limited by the present invention.

It should be noted that when the polarity of each first pixel and each second pixel is reversed, the source driving circuit 120 sets the voltage level of the common voltage VCOM to the voltage level VCOM1-DVc in the first time interval, so The voltage level of the common voltage VCOM is no longer the original normal voltage level VCOM1 in the first time interval, thereby reducing the charging voltage of each source driving signal VS1~VSn to each second pixel (at this time, the charging voltage The voltage value of is the absolute value of the voltage level Vn minus the voltage level VCOM1-DVc).

Then, in a second time interval after the first time interval, the source driving circuit 120 sets the voltage level of the common voltage VCOM to the voltage level VCOM1 in the second time interval, and accordingly, it can be compared in the second time interval. The voltage value of the high charging voltage (the voltage value of the charging voltage at this time is the voltage level Vn minus the absolute value of the voltage level VCOM1) to charge each first pixel. Since the voltage level Vn is a negative voltage, the voltage The absolute value of the level VCOM1-DVc will be greater than the absolute value of the voltage level VCOM1, that is, the charging voltage of each first pixel will be greater than the charging voltage of each second pixel, so that the image in the second display area 112 is displayed accordingly The brightness is reduced, and can be reduced to substantially equal to the image display brightness of the first display area 111, wherein the reduction range of the image display brightness of the second display area 112 can be controlled by setting the offset value DVc. Those skilled in the art The magnitude of the offset value DVc between the voltage level VCOM1-DVc and the voltage level VCOM1 can be set according to actual application conditions, which is not limited by the present invention. In addition, the magnitudes of the offset value DVc and the offset value DVa may be the same or different, and those with ordinary knowledge in the art can also set it according to actual application conditions, which is not limited in the present invention.

In this way, the voltage value of the charging voltage received by each second pixel in the second display area 112 can be reduced, and each first pixel in the first display area 111 receives a higher charging voltage voltage. Since the source driving circuit 120 reduces the charging voltage of each second pixel, the brightness of the second display area 112 is reduced, thereby achieving the purpose of setting the brightness uniformity of the display image of the display panel 110.

Please refer to FIG. 3A and FIG. 7B simultaneously. FIG. 7B is a schematic diagram of the driving signal waveform of the embodiment of the embodiment of FIG. 3A for setting the common voltage. The difference from the embodiment in FIG. 1 is that the source driving signals VS (for example, the source driving signals VS1~VSn) in this embodiment drive the second display area 312 in the first time interval, and in the second time The interval corresponds to driving the first display area 311, and the third time interval corresponds to driving the third display area 313. The source driving circuit 320 sets the voltage level of the common voltage VCOM to the voltage level VCOM1+DVa in the first time interval according to the size of the first load, the second load and the third load, and sets the voltage level of the common voltage VCOM In the second time interval it is the voltage level VCOM1, and the voltage level of the common voltage VCOM is set to the voltage level VCOM1+DVb in the third time interval, where the voltage level VCOM1+DVa and the voltage level VCOM1 have an offset value DVa, and the voltage level VCOM1+DVb and the voltage level VCOM1 have an offset value DVb.

To explain in detail, in one screen period of this embodiment, the time period from the gate driving signals VG1 and VG2 provided by the gate driving lines DL1 and DL2 to the second display area 312 is the first time period, and the gate The time interval when the driving lines DL3~DLn-2 provide the gate driving signals VG3~VGn-2 to the first display area 311 is the second time interval, and the gate driving lines DLn-1~DLn provide the gate driving signals The time interval from VGn-1 to VGn to the third display area 313 is the third time interval. The source driving circuit 320 sets the voltage standard of the common voltage VCOM when charging each first pixel, each second pixel, and each third pixel according to the size of the first load, second load, and third load. For example, in this embodiment, the source driving circuit 320 sets the voltage level of the common voltage VCOM to the voltage level VCOM1+DVb in the third time interval after the second time interval, so that the common voltage VCOM The voltage level of is no longer the original normal voltage level VCOM1 in the third time interval, thereby reducing the charging voltage of each source driving signal VS1~VSn to each third pixel (the voltage value of the charging voltage at this time is The voltage level Vp minus the voltage level VCOM1+DVb).

In this way, each third pixel can be charged with a lower charging voltage in the third time interval, and the image display brightness of the third display area 313 can be reduced to substantially equal to that of the first display area. The purpose of the image display brightness of 311, and the reduction range of the image display brightness of the third display area 313 can be controlled by setting the offset value DVb. Those skilled in the art can set the voltage level VCOM1 according to the actual application. The magnitude of the offset value DVb between +DVb and the voltage level VCOM1 is not limited by the present invention.

It should be noted that when the polarity of each first pixel, each second pixel, and each third pixel is reversed, the source driving circuit 320 will set the voltage level of the common voltage VCOM as the voltage level in the third time interval. Level VCOM1-DVd, so that the voltage level of the common voltage VCOM is no longer the original normal voltage level VCOM1 in the third time interval, thereby reducing the effect of each source driving signal VS1~VSn on each third pixel Charging voltage (the voltage value of the charging voltage at this time is the voltage level Vn minus the absolute value of the voltage level VCOM1-DVd). Since the voltage level Vn is a negative voltage, the absolute value of the voltage level VCOM1 will be less than the voltage level The absolute value of VCOM1-DVd, that is, the charging voltage of each third pixel will be less than the charging voltage of each first pixel, so that the image display brightness of the third display area 313 is reduced, and can be reduced to substantially equal to the first pixel. The image display brightness of a display area 311, wherein the reduction range of the image display brightness of the third display area 313 can be controlled by setting the offset value DVd. Those skilled in the art can set the voltage level VCOM1 according to the actual application. The magnitude of the offset value DVd between DVd and the voltage level VCOM1, which is not limited by the present invention.

In addition, the operation mode in which the source driving circuit 320 sets the voltage level of the common voltage VCOM in the first time interval and the second time interval is similar to the foregoing embodiment of FIG. 1 and will not be repeated here.

Please refer to FIG. 1 and FIG. 8 simultaneously. FIG. 8 is a schematic diagram of an implementation manner of setting gamma curve information in the embodiment of FIG. 1 of the present invention. In this embodiment, each source driving signal VS (for example, the source driving signals VS1~VSn) correspondingly drives the second display area 112 in the first time interval, and correspondingly drives the first display area in the second time interval 111. The source driving circuit 120 has reference gamma curve information GamC1 and at least one adjusted gamma curve information (for example, adjusted gamma curve information GamC2), wherein the reference gamma curve information GamC1 (ie, adjusted gamma curve information) The dotted line of the GamC2 waveform) corresponds to the first display area 111, and the adjusted gamma curve information GamC2 corresponds to the second display area 112.

The source driving circuit 120 generates the source driving signals VS1~VSn according to the reference gamma curve information GamC1 and provides them to the first display area 111, and generates the source driving signals VS1~VSn according to the adjusted gamma curve information GamC2 , To provide to the second display area 112. To explain in detail, the horizontal axis of the reference gamma curve information GamC1 and the adjusted gamma curve information GamC2 is the gray level G, and the vertical axis is the brightness L, and the curvature of the reference gamma curve information GamC1 and the adjusted gamma curve information GamC2 are different That is, the brightness voltage corresponding to the brightness L of the reference gamma curve information GamC1 is greater than the brightness voltage corresponding to the brightness L of the adjusted gamma curve information GamC2. It should be noted that, in order to simplify the description, this embodiment only shows one adjusted gamma curve information GamC2, but those skilled in the art can adjust the amount of adjusted gamma curve information according to actual application conditions. The present invention It is not limited.

The source driving circuit 120 will be set according to the size of the first load and the second load. Since the first load is greater than the second load, the source driving circuit 120 will generate the signal according to the reference gamma curve information GamC1 in the second time interval. Each source driving signal VS1~VSn is provided to provide each source driving signal VS1~VSn to each first pixel in the first display area 111, and in the first time interval, the source driving circuit 120 is adjusted according to the adjusted value. The Ma curve information GamC2 generates each source driving signal VS1~VSn to provide each source driving signal VS1~VSn for each second pixel in the second display area 112.

As a result, since the curvature of the adjusted gamma curve information GamC2 is greater than the curvature of the reference gamma curve information GamC1, that is, the brightness voltage of the adjusted gamma curve information GamC2 is less than the brightness voltage of the reference gamma curve information GamC1, this embodiment By providing the brightness voltage of the adjusted gamma curve information GamC2 with a larger curvature to the second display area 112, the brightness of the second display area 112 can be reduced to substantially equal to the brightness of the first display area 111 to achieve The purpose of improving the uniformity of the overall light emission of the display panel 110.

Please refer to FIG. 1 and FIG. 9A simultaneously. FIG. 9A is a schematic diagram of another embodiment of setting gamma curve information according to the embodiment of FIG. 1 of the present invention. In this embodiment, each source driving signal VS (for example, the source driving signals VS1~VSn) correspondingly drives the second display area 112 in the first time interval, and correspondingly drives the first display area in the second time interval 111, and the source driving circuit 120 has reference gamma curve information IDGam and at least one adjusted gamma curve information (for example, adjusted gamma curve information ADGam), wherein the dotted line in the adjusted gamma curve information ADGam is Reference gamma curve information IDGam waveform.

The reference gamma curve information IDGam has multiple grayscale intervals, and the multiple grayscale intervals correspond to multiple reference brightness intervals. The multiple grayscale intervals of the adjusted gamma curve information ADGam correspond to multiple adjusted brightness intervals. The voltage value corresponding to each adjusted brightness interval (ie, the voltage value off1~offK) will be less than or equal to the voltage value corresponding to each reference brightness interval (ie, the voltage value at the dotted line of the waveform in FIG. 9A). The source driving circuit 120 generates the source driving signals VS1~VSn according to the reference gamma curve information IDGam and provides them to the first display area 111, and generates the source driving signals VS1~VSn according to the adjusted gamma curve information ADGam, And provided to the second display area 112.

To explain in detail, the horizontal axis of the reference gamma curve information IDGam and the adjusted gamma curve information ADGam is the gray level G, and the vertical axis is the brightness L. The source driving circuit 120 of this embodiment sets the reference gamma curve information IDGam The gray scale G is divided into K gray scale intervals (for example, the gray scale interval S1~SK), the K gray scale intervals S1~SK respectively correspond to K reference brightness intervals, and the adjusted gamma curve information ADGam has K gray scales The intervals S1~SK correspond to K adjusted brightness intervals respectively, where the reference gamma curve information IDGam and the adjusted gamma curve information ADGam are different curves, and K is an integer not less than 1.

The voltage value corresponding to each adjusted brightness interval (ie voltage value off1~offK) will be less than or equal to the voltage value corresponding to each reference brightness interval (ie the dotted line of the waveform in Figure 9A). For example, adjust in the grayscale interval S1 The voltage value Off1 corresponding to the rear brightness interval is equal to the voltage value corresponding to the reference brightness interval. The voltage value Off2 corresponding to the brightness interval after adjustment in the grayscale interval S2 will be less than the voltage value corresponding to the reference brightness interval, in the grayscale interval SK-1 The voltage value OffK-1 corresponding to the adjusted brightness interval will be less than the voltage value corresponding to the reference brightness interval, and the voltage value OffK corresponding to the adjusted brightness interval in the grayscale interval SK will be equal to the voltage value corresponding to the reference brightness interval. It should be noted that the size of the K grayscale intervals in this embodiment may be the same or different. Those with ordinary knowledge of the present invention can adjust the number of grayscale intervals and adjust the corresponding brightness intervals according to the actual application. The voltage value is not limited by the present invention.

In this way, in this embodiment, the voltage value Off1~OffK corresponding to the adjusted brightness interval in the adjusted gamma curve information ADGam is set, so that the source driving circuit 120 generates the corresponding second display area according to the adjusted gamma curve information ADGam The source driving signals VS1~VSn of 112, and the source driving circuit 120 generates the source driving signals VS1~VSn corresponding to the first display area 111 according to the reference gamma curve information IDGam. In this way, the second display area 112 has a lower brightness, and the brightness uniformity of the second display area 112 and the first display area 111 is improved, so that the display panel 110 can emit light uniformly.

Please refer to FIGS. 3A and 9B simultaneously. FIG. 9B is a schematic diagram of another embodiment of setting gamma curve information in the embodiment of FIG. 3A of the present invention. The difference from the aforementioned embodiment in FIG. 1 is that the source driving circuit 320 of this embodiment can be set to provide each third pixel in the third display area 313 according to the size of the first load, the second load, and the third load. And the magnitude of the brightness voltage provided to each second pixel in the second display area 312. In detail, the source driving circuit 320 sets the adjusted gamma curve information ADGam according to the magnitude of the first load, the second load and the third load, and generates each source driving signal VS1 according to the adjusted gamma curve information ADGam. ~VSn, and provided to the third display area 313 to reduce the charging voltage of each third pixel, and reduce the charging voltage of each third pixel, thereby making the first display area 311, the second display area 312, and the The brightness of the three display areas 313 is uniform, wherein the adjusted gamma curve information ADGam corresponding to the third display area 313 may be the same as the adjusted gamma curve information ADGam corresponding to the second display area 312, or it may be a different adjusted gamma curve. Ma curve information, those skilled in the art can adjust the size of the second load and the third load in actual applications, and the present invention is not limited.

In addition, in this embodiment, the operation of setting gamma curve information for each first pixel and each second pixel is similar to that of the embodiment in FIG. 1, and will not be repeated here.

Please refer to FIG. 1 and FIG. 10 simultaneously. FIG. 10 is a schematic diagram of another embodiment of setting the common voltage in the embodiment of FIG. 1 of the present invention. In this embodiment, the source driving circuit 120 provides the first common voltage VCOMDC1 to each of the first display area 111 according to the size of the first load in the first display area 111 and the second load in the second display area 112. The first pixel and each second pixel in the second display area 112 provided with the second common voltage VCOMDC2, wherein the voltage level of the first common voltage VCOMDC1 is lower than the voltage level of the second common voltage VCOMDC2. To explain in detail, the source driving circuit 120 of this embodiment sets common voltages with different voltage levels (ie, the first common voltage VCOMDC1 and the second common voltage VCOMDC2) according to the sizes of the first load and the second load. Set the charging voltage of each first pixel and each second pixel.

For example, the source driving circuit 120 sets the first common voltage VCOMDC1 with a lower voltage level as the common voltage of each first pixel in the first display area 111 according to the size of the first load and the second load, so that A higher charging voltage is set, and the second common voltage VCOMDC2 with a higher set voltage level is the common voltage of each second pixel in the second display area 112 to set a lower charging voltage. In this way, since the source driving circuit 120 provides a lower charging voltage for each second pixel of the second display area 112, and provides a higher charging voltage for each first pixel of the first display area 111, thereby making The brightness of the displayed image in the second display area 112 is reduced to substantially equal to the brightness of the displayed image in the first display area 111, so as to improve the uniformity of the overall brightness of the display panel 110 and achieve the goal of uniform brightness of the displayed image of the display panel 110.

It is worth mentioning that the embodiments of FIG. 8 and FIG. 10 of the present invention can also be applied to the display device 300 having the first display area 311, the first display area 312, and the third display area 313 in the embodiment of FIG. 3A. And the operation mode is similar to the foregoing embodiment in FIG. 1, and the details are not repeated here.

Please refer to FIGS. 1, 3A, and 11A to 11C simultaneously. FIGS. 11A to 11C show schematic diagrams of different implementations of the display panel according to the embodiment of the present invention. The shape of the display panel (such as the display panel 110, 310) in the display device (such as the display device 100, 300) of this embodiment can be implemented in many different ways. For example, the display panel 110, 310 can be shown in FIG. 11A. The illustrated embodiment of the display panel 1110a has an L shape with a single bend. It may also be a display panel 1110b as shown in FIG. 11B, which has two rounded corners (ie rounded corners CV1 and CV2) and two right angles on the edge of the panel. It can also be the display panel 1110c shown in FIG. 11C. The edge of the panel has a rounded corner CV3, a missing corner area LR, and two right angles, and the display panel 1110c has a shape of a hollow area HOL. In other words, the present invention does not limit the position and number of the notch shape, rounded corner shape, right angle shape, missing corner area, and hollowed out area in the display panels 110, 310, that is, the display panel 110 of the present invention , 310 can be any shape.

In summary, the driving circuit of the present invention will be based on the size of the first load provided by the plurality of first pixels in the first display area and the second load provided by the plurality of second pixels in the second display area respectively. Set the electrical characteristics of each first drive signal and each second drive signal to set the brightness of the first display area and the second display area, thereby improving the brightness uniformity of the second display area and the first display area on the display panel, In this way, the brightness of the displayed image of the display panel is uniform, thereby increasing the quality of the display.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make slight changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to those defined by the attached patent scope.

100, 300‧‧‧Display device 110, 310, 1110a, 1110b, 1110c‧‧‧Display panel 120, 320‧‧‧Source drive circuit 130, 330‧‧‧Gate drive circuit 111, 311, 311a‧‧‧ The first display area 112, 312, 312a‧‧‧The second display area 313,313a‧‧‧The third display area CV1, CV2, CV3‧‧‧Rounded corner DL1~DLn‧‧‧Gate drive line G‧‧ ‧Gray level HOL‧‧‧Knocked out area IDGam, ADGam, GamC1, GamC2‧‧‧Gamma curve information L‧‧‧Luminance LIN1~LINn‧‧‧Drive line LR‧‧‧Corner area Off1~OffK‧‧‧ Voltage values Rdata, Gdata, Bdata‧‧‧Data S1~SK‧‧‧Gray scale interval SL1~SLn‧‧‧Source drive line T1~T5‧‧‧Time interval TSDT1~TSDT3, TRGB1~TRGB3‧‧‧Time VCOM ‧‧‧Common voltage VDis‧‧‧Disable voltage level VEn‧‧‧Enable voltage level VG, VG1~VGn‧‧‧Gate drive signal VMR1~VMR3, VMG1~VMG3, VMB1~VMB3‧‧‧Switch Control signal VS, VS1~VSn‧‧‧Source drive signal VSSp, VSSn, VGND, Vp, Vp-DV1, Vp-DV2, Vn, Vn+DV3, Vn+DV4, VCOM1, VCOM1+DVa, VCOM1+DVb, VCOM1-DVc, VCOM1-DVd, VCOMDC1, VCOMDC2‧‧‧Voltage level

FIG. 1 is a circuit block diagram of a display device according to an embodiment of the invention. FIG. 2A is a schematic diagram showing the waveform of the gate drive signal in the implementation of setting the slew rate in the embodiment of FIG. FIG. 2B is a schematic diagram of the gate driving signal waveform of the voltage level setting implementation of the embodiment of FIG. 1 of the present invention. FIG. 3A is a circuit block diagram of a display device according to another embodiment of the invention. 3B is a schematic diagram of another embodiment of the display panel of the embodiment in FIG. 3A of the present invention. FIG. 4A is a schematic diagram of the driving signal waveform of the embodiment of setting the gate driving signal enable time in the embodiment of FIG. 1 of the present invention. 4B is a schematic diagram of the driving signal waveform of the embodiment of setting the gate driving signal enable time in the embodiment of FIG. 3A of the present invention. FIG. 5A is a schematic diagram of the driving signal waveform of the embodiment of setting the enable time of the switch control signal in the embodiment of FIG. 1 of the present invention. FIG. 5B is a schematic diagram of the driving signal waveform of the embodiment of setting the enable time of the switch control signal in the embodiment of FIG. 3A of the present invention. FIG. 6A is a schematic diagram of the source driving signal waveform of the embodiment of setting the data voltage in the embodiment of FIG. 1 of the present invention. 6B is a schematic diagram of the driving signal waveforms of the embodiment of setting the data voltage in the embodiment of FIG. 3A of the present invention. FIG. 7A is a schematic diagram of the driving signal waveform of the embodiment of setting the common voltage in the embodiment of FIG. 1 of the present invention. FIG. 7B is a schematic diagram of the driving signal waveform of the embodiment of setting the common voltage in the embodiment of FIG. 3A of the present invention. FIG. 8 is a schematic diagram of an implementation of setting gamma curve information in the embodiment of FIG. 1 of the present invention. FIG. 9A is a schematic diagram of another embodiment of setting gamma curve information in the embodiment of FIG. 1 of the present invention. FIG. 9B is a schematic diagram of another embodiment of setting gamma curve information in the embodiment of FIG. 3A of the present invention. FIG. 10 is a schematic diagram of another embodiment of setting a common voltage in the embodiment of FIG. 1 of the present invention. 11A to 11C show schematic diagrams of different implementations of the display panel according to an embodiment of the present invention.

100‧‧‧Display device

110‧‧‧Display Panel

120‧‧‧Source drive circuit

130‧‧‧Gate drive circuit

111‧‧‧First display area

112‧‧‧Second display area

DL1~DLn‧‧‧Gate drive line

SL1~SLn‧‧‧Source drive line

VG1~VGn‧‧‧Gate drive signal

VS1~VSn‧‧‧Source drive signal

Claims (16)

A display device includes: a display panel, including a first display area and a second display area, the first display area is coupled to a plurality of first driving lines, and the second display area is coupled to a plurality of second driving lines , Wherein a first load provided by a plurality of first pixels corresponding to each of the first driving lines is greater than a second load provided by a plurality of second pixels corresponding to each of the second driving lines; and a driving circuit, Coupled to the first driving lines and the second driving lines for respectively providing a plurality of first driving signals to the first driving lines, and respectively providing a plurality of second driving signals to the second driving lines , Wherein the driving circuit respectively sets the electrical characteristics of the first driving signals and the second driving signals according to the magnitudes of the first load and the second load, wherein the first driving lines and the second driving signals The driving lines are gate driving lines, the first driving signals and the second driving signals are gate driving signals, and the driving circuit sets the second driving according to the magnitude of the first load and the second load The slew rate of the signal. For the display device described in item 1 of the scope of patent application, the driving circuit divides each of the second driving signals into a plurality of time intervals, and sets a plurality of voltage levels so that each of the second driving signals is at the The time intervals are respectively maintained at the corresponding voltage levels, wherein the driving circuit is based on the magnitude of the first load and the second load to Set the voltage levels and the size of at least one of the time intervals. As for the display device described in claim 1, wherein the driving circuit sets the alignment of at least one of the first driving signals and the second driving signals according to the magnitudes of the first load and the second load Can time. According to the display device described in claim 1, wherein the display panel further includes: a third display area, the third display area is coupled to a plurality of third driving lines, wherein each of the third driving lines corresponds to A plurality of third pixels provide a third load, and the driving circuit is further coupled to the third driving lines to provide a plurality of third driving signals to the third driving lines. The display device according to the first item of the scope of patent application, wherein the display panel has a notch shape, a rounded corner shape, a right angle shape, a missing corner area or a hollowed out area. A display device includes: a display panel, including a first display area and a second display area, the first display area is coupled to a plurality of first driving lines, and the second display area is coupled to a plurality of second driving lines , Wherein a first load provided by a plurality of first pixels corresponding to each of the first driving lines is greater than a second load provided by a plurality of second pixels corresponding to each of the second driving lines; and a driving circuit, Coupled to the first driving lines and the second driving lines for respectively providing a plurality of first driving signals to the first driving lines, and respectively providing a plurality of second driving signals to the second driving lines , Wherein the driving circuit is based on the size of the first load and the second load The electrical characteristics of the first driving signals and the second driving signals are respectively set, wherein the first driving lines and the second driving lines are source driving lines, and the first driving signals and the first driving signals are The two driving signals are source driving signals, wherein each of the first driving signal and each of the second driving signals correspondingly drives the second display area in a first time interval, and correspondingly drives the first display in a second time interval Area. According to the display device described in claim 6, wherein the display panel further includes: a plurality of first multiplexers, including a plurality of first switches respectively receiving a plurality of first switch control signals, the first multiplexers The second multiplexer corresponds to the second display area; a plurality of second multiplexers including a plurality of second switches respectively receive a plurality of second switch control signals, and the second multiplexers correspond to the first display area, wherein, The driving circuit sets the enabling time of at least one of each of the first switch control signal and each of the second switch control signals according to the size of the first load and the second load. For the display device described in item 6 of the scope of patent application, the driving circuit sets the first driving signal and the second driving signal to be in the first time interval according to the magnitude of the first load and the second load Is a first voltage level, and each of the first driving signals and each of the second driving signals is set to a second voltage level in the second time interval, wherein the first voltage level and the second voltage level The bit has an offset value. For the display device described in item 6 of the scope of patent application, the driving circuit sets a common voltage to a first voltage level in the first time interval according to the size of the first load and the second load, and sets The common voltage is a second voltage level in the second time interval, wherein the first voltage level and the second voltage level have an offset value. According to the display device described in claim 6, wherein the driving circuit has a reference gamma curve information and at least one adjusted gamma curve information, the reference gamma curve information corresponds to the first display area, the At least one adjusted gamma curve information corresponds to the second display area. The display device according to claim 10, wherein the driving circuit generates the first driving signals according to the reference gamma curve information, and generates the second driving signals according to the at least one adjusted gamma curve information , Wherein the reference gamma curve information and the at least one adjusted gamma curve information have different curvatures. For the display device described in item 10 of the scope of patent application, the reference gamma curve information has a plurality of grayscale intervals, the grayscale intervals correspond to a plurality of reference brightness intervals, and the at least one adjusted gamma curve information The gray scale intervals respectively correspond to a plurality of adjusted brightness intervals, wherein the voltage values corresponding to the adjusted brightness intervals are less than or equal to the voltage values corresponding to the reference brightness intervals. The display device according to claim 12, wherein the driving circuit generates the first driving signals according to the reference gamma curve information, and generates the second driving signals according to the at least one adjusted gamma curve information . The display device according to claim 6, wherein the driving circuit provides a first common voltage to each of the first pixels in the first display area according to the size of the first load and the second load , And providing a second common voltage to each of the second pixels in the second display area, wherein the voltage level of the first common voltage is lower than the voltage level of the second common voltage. According to the display device described in claim 6, wherein the display panel further includes: a third display area, the third display area is coupled to a plurality of third driving lines, wherein each of the third driving lines corresponds to A plurality of third pixels provide a third load, and the driving circuit is further coupled to the third driving lines to provide a plurality of third driving signals to the third driving lines. According to the display device described in item 6 of the scope of patent application, the display panel has a notch shape, a rounded corner shape, a right angle shape, a missing corner area or a hollowed out area.

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