TW201941182A - Display device - Google Patents

Abstract

A display device includes a display panel and a driving circuit. The display panel includes a first display region and a second display region, the first display region is coupled to a plurality of first driving lines, the second display region is coupled to a plurality of second driving lines, wherein a first load provided by a plurality of first pixels corresponding to the first driving lines is larger than a second load provided by a plurality of second pixels corresponding to the second driving lines. The driving circuit provides a plurality of first driving signals to the first driving lines and provides a plurality of second driving signals to the second driving lines respectively, wherein the driving circuit sets electric characteristics of the first driving signals and the second driving signals respectively according to the loading of the first load and the second load.

Description

Display device

The present invention relates to a display device, and more particularly to a display device for making the brightness of a display image of a display panel uniform.

In today's display panels, in order to respond to the diversity of products and provide customized designs, various display panels of different shapes have been gradually developed. Different from the traditional rectangular frame design, it uses a curved or streamlined frame design. As a result, display panels with various shapes such as notch shapes or rounded corners have been produced.

However, the shape of the notch and the shape of the rounded corners on the display panel will affect the display panel. As each source driving line and each gate driving line on the display panel are in the general display area (ie, the non-notched shape and Non-rounded corner display area), the number of pixels to be driven is relatively large, and a large load will cause the brightness of this area to be relatively low, while the notch shape or rounded corner shape of the display panel In the nearby display area, the number of pixels to be driven by each source driving line and each gate driving line is relatively small, and it has a small load, so that the shape of the notch or round corner of the display panel is near. The brightness of the display area is higher than that of a normal display area, which causes a non-uniform brightness (Mura) phenomenon on the display image of the display panel.

The present invention provides a display device, and more particularly, to a display device for making the display image brightness of a display panel uniform.

A display device of the present invention includes a display panel and a driving circuit. The display panel includes a first display area and a second display area. The first display area is coupled to a plurality of first drive lines, and the second display area is coupled to a plurality of second drive lines. The first load provided by the first pixel is greater than the second load provided by the plurality of second pixels corresponding to each second driving line. The driving circuit is coupled to a plurality of first driving lines and a plurality of second driving lines for providing a plurality of first driving signals to the plurality of first driving lines and a plurality of second driving signals to the plurality of second driving lines, respectively. The driving circuit sets the electrical characteristics of the plurality of first driving signals and the plurality of second driving signals respectively according to the magnitude of the first load and the second load.

Based on the above, the driving circuit of the present invention can respectively set a plurality of first driving signals provided to the first display area and provide the first driving signals according to the magnitude of the first load in the first display area and the second load in the second display area. The electrical characteristics of the plurality of second driving signals to the second display area are used to set the brightness of the first display area and the second display area respectively, so as to improve the uniformity of the overall brightness of the display panel and achieve the display image of the display panel. The purpose of uniform brightness and increase the quality of the display.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

Please refer to FIG. 1. FIG. 1 is a schematic circuit block diagram of a display device according to an embodiment of the present invention. The display device 100 includes a display panel 110, a source driving circuit 120, and a gate driving circuit 130. The display panel 110 includes a first display area 111 and a second display area 112. The first display area 111 is coupled to a plurality of gate driving lines (such as gate driving lines DL3 to DLn) and a plurality of source driving lines (such as Source drive lines SL1 ~ SLn), the second display area 112 is coupled to multiple gate drive lines (eg, gate drive lines DL1, DL2) and multiple source drive lines (eg, source drive lines SL1, SL2) , SLn-1, SLn). It should be noted that, in order to simplify the description, this embodiment only shows two gate driving lines DL1, DL2 and four source driving lines SL1, SL2, SLn-1, and SLn are coupled to the second display area 112 as the Exemplary embodiment, however, the present invention does not limit the number of source driving lines and gate driving lines coupled to the second display area 112. Those skilled in the art can set the coupling according to the actual application. The number of source driving lines and gate driving lines to the second display area 112.

The source driving circuit 120 is coupled to the source driving lines SL1 to SLn to provide a plurality of source driving signals VS1, VS2, VSn-1, VSn to the source driving line SL1 coupled to the second display area 112, respectively. , SL2, SLn-1, SLn, and providing a plurality of source driving signals VS1 ~ VSn to the source driving lines SL1 ~ SLn coupled to the first display area 111, respectively.

The gate driving circuit 130 is coupled to the gate driving lines DL1 to DLn to provide a plurality of gate driving signals VG1 and VG2 to the gate driving lines DL1 and DL2 respectively coupled to the second display area 112, and provides them respectively. The plurality of gate driving signals VG3 to VGn are connected to the gate driving lines DL3 to DLn coupled to the first display area 111.

In addition, in the display panel 110, each gate driving line DL3 to DLn corresponds to a first load provided by a plurality of first pixels in the first display area 111 and is greater than each gate driving line DL1, DL2 corresponds to a second A second load provided by the plurality of second pixels of the display area 112. In detail, there are multiple first pixels in the first display area 111 and multiple second pixels in the second display area 112, and the number of the first pixels is greater than the number of the second pixels, that is, The first load provided by the plurality of first pixels may be larger than the second load provided by the plurality of second pixels. Therefore, the load of the gate driving lines DL3 to DLn coupled to the first display area 111 when driving the first pixel is greater than that of the gate driving lines DL1 and DL2 coupled to the second display area 112 to drive the second image. The load voltage is constant, so the voltage values of the gate driving signals VG1 and VG2 in the second display area 112 near the notch shape of the display panel 110 will be larger than those of the gate driving signals VG3 to VGn in the general display area. Voltage value.

It is worth mentioning that the gate driving circuit 130 and / or the source driving circuit 120 in this embodiment will set multiple source driving signals (for example, source driving signals) according to the magnitude of the first load and the second load. VS1 ~ VSn) and / or multiple gate drive signals (eg, gate drive signals VG1 ~ VGn), thereby setting the brightness of the first display area 111 and the second display area 112 to make the display panel The uniformity of the overall brightness of 110 is improved to achieve the purpose of making the brightness of the displayed image of the display panel 110 uniform.

An embodiment of setting the electrical characteristics of each source driving signal and / or each gate driving signal according to the present invention will be described in detail. Please refer to FIG. 1 and FIG. 2A synchronously. FIG. 2A shows the setting rotation of the embodiment of FIG. 1 of the present invention. Schematic diagram of the gate drive signal waveforms of the rate implementation. In this embodiment, the gate driving circuit 130 sets slew rates of a plurality of gate driving signals (eg, the gate driving signals VG1 and VG2) according to the magnitude of the first load and the second load. Further, the gate driving circuit 130 of this embodiment sets the slew rates of the gate driving signals VG1 and VG2 so that the slew rates of the gate driving signals VG1 and VG2 are lower than the original slew rates ( For example, 100%), for example, when the gate drive circuit 130 sets the slew rate of each gate drive signal VG1, VG2 to 75%, the voltage values of the rising edges of each gate drive signal VG1, VG2 will decrease. , And will be lower than the voltage values of the gate drive signals VG1 and VG2 when the original slew rate is 100%.

At the same time, the voltage values of the falling edges of the gate driving signals VG1 and VG2 will increase and will be higher than the voltage values of the gate driving signals VG1 and VG2 when the original slew rate is 100%. The voltage levels of the rising edges of the gate driving signals VG1 and VG2 are sequentially increased from the disabling voltage level VDis to the enabling voltage level VEn, and the voltage levels of the falling edges of the gate driving signals VG1 and VG2 are made uniform. The energy voltage level VEn is sequentially decreased to the disabled voltage level VDis. It should be noted that the implementation manner of setting the slew rates of the gate driving signals VG1 and VG2 to 50% and 25% is similar to the foregoing implementation manner of setting the slew rate to 75%, and is not repeated here.

In this way, in the embodiment of the present invention, the voltage waveforms of the gate driving signals VG1 and VG2 can be distorted by setting the slew rates of the gate driving signals VG1 and VG2 coupled to the second display area 112 (even if each The voltage waveforms of the gate driving signals VG1 and VG2 are not ideal square waves), and the effective voltage values of the gate driving signals VG1 and VG2 are reduced to make the voltage waveforms of the gate driving signals VG1 and VG2 and the gate driving The voltage waveforms of the signals VG3 to VGn are similar. Accordingly, the brightness of the second display area 112 and the brightness of the first display area 111 are set to be substantially equal, so as to improve the uniformity of the overall brightness of the display panel 110 and achieve brightness of the image displayed by the display panel 110. The purpose of uniformity and increase the quality of the display.

On the other hand, please refer to FIG. 1 and FIG. 2B simultaneously. FIG. 2B shows a schematic diagram of a gate driving signal waveform of the voltage level setting implementation of the embodiment of FIG. 1 of the present invention. In this embodiment, the gate driving circuit 130 divides each gate driving signal VG1, VG2 into multiple time intervals (for example, time intervals T1 to T5), and sets multiple voltage levels (for example, voltage levels). VGND, voltage level VSSp, enabled voltage level VEn, disabled voltage level VDis, and voltage level VSSn), so that each gate driving signal VG1, VG2 can be maintained at a corresponding multiple in multiple time intervals, respectively. Voltage level. In addition, the gate driving circuit 130 sets at least one of a plurality of voltage levels and a plurality of time intervals according to the magnitude of the first load and the second load, so that the voltages of the gate driving signals VG1 and VG2 are between Each of the time intervals T1 to T5 has a plurality of different voltage levels.

To explain in detail, the gate driving circuit 130 of this embodiment divides the voltage waveforms of the gate driving signals VG1 and VG2 into time intervals T1 to T5 according to the magnitude of the first load and the second load, and sets each gate. The voltage levels of the driving signals VG1 and VG2 in each time interval. For example, in the time interval T1, the gate driving circuit 130 is set to maintain the voltage levels of the gate driving signals VG1 and VG2 at the voltage level VGND. In a time interval T2 after the time interval T1, the voltage levels of the gate driving signals VG1 and VG2 are maintained at the voltage level VSSp.

Next, in the time interval T3 after the time interval T2, the gate driving circuit 130 is set so that the voltage levels of the gate driving signals VG1 and VG2 are maintained at the enable voltage level VEn, and the time after the time interval T3 In the interval T4, the voltage levels of the gate driving signals VG1 and VG2 are maintained at the voltage level VGND, and in the time interval T5 after the time interval T4, the voltage levels of the gate driving signals VG1 and VG2 are maintained. At the voltage level VSSn, the voltage levels of the rising edges of the gate driving signals VG1 and VG2 are sequentially increased from the disabled voltage level VDis to the enabled voltage level VEn, and the gate driving signals VG1 are increased. The voltage level of the falling edge of VG2 gradually decreases from the enabled voltage level VEn to the disabled voltage level VDis, where the voltage level VSSn is higher than the disabled voltage level VDis and the voltage level VGND is higher than the voltage level VSSn, the voltage level VSSp is higher than the voltage level VGND, and the enable voltage level VEn is higher than the voltage level VSSp. It should be noted that in order to simplify the description, this embodiment only shows five time intervals and five different voltage levels as exemplary embodiments, but in fact, those with ordinary knowledge in the art can adjust each according to the actual application situation. The number of time intervals, the size of time intervals, the number of voltage levels, and the size of voltage levels in the gate drive signal voltage waveform are not limited by the present invention.

In this way, in the embodiment of the present invention, the gate driving signals VG1 and VG2 are set so that the gate driving signals VG1 and VG2 are maintained at corresponding voltage levels in the time intervals T1 to T5, respectively. The voltage waveforms of the gate driving signals VG1 and VG2 are distorted, reducing the effective voltage values of the gate driving signals VG1 and VG2, so that the voltage waveforms of the gate driving signals VG1 and VG2 and the voltages of the gate driving signals VG3 to VGn are reduced. The waveforms are similar. Accordingly, the brightness of the second display area 112 is set to improve the uniformity of the overall brightness of the display panel 110, to achieve the purpose of uniformizing the brightness of the image displayed by the display panel 110, and to increase the display quality.

It is worth mentioning that the present invention further mentions that the display panel in the display device may further include a third display area. Please refer to FIG. 3A, which is a schematic circuit block diagram of a display device according to another embodiment of the present invention. . In this embodiment, the display device 300 includes a display panel 310, a source driving circuit 320, and a gate driving circuit 330. The difference from the embodiment in FIG. 1 is that the display panel 310 includes a first display area 311, a second display area 312, and a third display area 313. The first display area 311 is coupled to a plurality of gate driving lines DL3 to DLn-2. And a plurality of source driving lines SL1 to SLn, the second display area 312 is coupled to a plurality of gate driving lines DL1, DL2 and a plurality of source driving lines SL1, SL2, SLn-1, SLn, and a third display area 313 is coupled A plurality of gate driving lines DLn-1, DLn and a plurality of source driving lines SL1, SL2, SLn-1, SLn are connected. It should be noted that, in order to simplify the description, this embodiment only shows two gate driving lines DLn-1, DLn and four source driving lines SL1, SL2, SLn-1, and SLn are coupled to the third display area 313. As an exemplary embodiment, the present invention does not actually limit the number of source driving lines and gate driving lines coupled to the third display area 313, and those with ordinary knowledge in the art may according to actual application conditions. , Set the number of source driving lines and gate driving lines coupled to the third display area 313.

In addition, the third display area 313 in the display panel 310 has a plurality of third pixels, and the gate driving circuit 330 and / or the source driving circuit 320 will depend on the size of the first load, the second load, and the third load. , Respectively setting a gate driving signal and / or a plurality of source driving signals coupled to the first display area 311, a gate driving signal and / or a plurality of source driving signals coupled to the second display area 312, and Electrical characteristics of the plurality of gate driving signals and / or the plurality of source driving signals coupled to the third display area 313, thereby setting the display of the first display area 311, the second display area 312, and the third display area 313. The brightness of the images is to increase the uniformity of the brightness of the displayed images of the first display area 311, the second display area 312, and the third display area 313, so as to achieve the purpose of making the brightness of the displayed images of the display panel 310 uniform.

In addition, the present invention further mentions that the display panel 310 of the embodiment of FIG. 3A has another implementation manner. Please refer to FIG. 3A and FIG. 3B simultaneously. FIG. 3B illustrates another embodiment of the display panel of the embodiment of FIG. 3A of the present invention. schematic diagram. In this embodiment, the display panel 310 may divide the display area in a vertical manner, and the display panel 310 is divided into a first display area 311a, a second display area 312a, and a third display area 313a. The method of dividing the display area is not limited, and the size of the divided area is not limited. That is, those with ordinary knowledge in the art can adjust the first display area 311a, the second display area 312a, and the first display area according to the actual application. The shape and size of the three display areas 313a. In addition, the display panel 310 of this embodiment is coupled to a plurality of driving lines, and a gate driving line or a source driving line may be selected according to the division manner of the display area. Electrical characteristics of the first driving signal, the plurality of second driving signals provided to the second display area 312a, and the plurality of third driving signals provided to the third display area 313a are set.

To explain in detail, the embodiment of the present invention can be set by driving lines (for example, driving lines LIN1 ~ LINn) that extend in the same direction as the display area. For example, when the driving lines LIN1 ~ LINn are gate driving lines, they can be set. The gate driving signals transmitted to the first display area 311a, the second display area 312a, and the third display area 313a are set to set the display image brightness of each display area. In contrast, when the driving lines LIN1 to LINn are source driving lines, the source driving signals transmitted to the first display area 311a, the second display area 312a, and the third display area 313a can be set, thereby setting each The brightness of the display image in the display area. That is, the driving lines LIN1 to LINn in this embodiment may be gate driving lines or source driving lines. Those with ordinary knowledge in the art may adjust according to actual application conditions, which is not limited in the present invention.

On the other hand, the implementation of the set gate driving signal implementation of the embodiment of FIG. 2A and FIG. 2B of the present invention can be applied to the display device 300 of the embodiment of FIG. 3A and FIG. 3B, and its operation principle and operation mode are similar to the embodiment of FIG. 1 described above. I will not repeat them here.

Please refer to FIG. 1 and FIG. 4A simultaneously. FIG. 4A is a schematic diagram of driving signal waveforms in the implementation manner of setting the gate driving signal enable time in the embodiment of FIG. 1 of the present invention. In this embodiment, the gate driving circuit 130 sets the gate driving signals VG (eg, the gate driving signals VG3 to VGn) transmitted to the first display area 111 according to the magnitude of the first load and the second load, and An enabling time transmitted to at least one of the gate driving signals VG (eg, the gate driving signals VG1 and VG2) in the second display area 112 to set a plurality of first pixels in the first display area 111 and Charging time of a plurality of second pixels in the second display area 112.

In detail, the gate driving circuit 130 of this embodiment sets the gate driving signals VG1 and VG2 coupled to the second display area 112 according to the magnitude of the first load and the second load, so that each gate The enabling time of the pole driving signals VG1 and VG2 is shortened by a time TSDT1, thereby reducing the charging time of each second pixel to receive the data voltage VS (for example, the source driving signals VS1, VS2, VSn-1, VSn) to The brightness of the displayed image of the second display area 112 is reduced, so that the brightness of the displayed images of the first display area 111 and the second display area 112 are substantially the same, and the purpose of making the brightness of the displayed image of the display panel 110 uniform is achieved.

It is worth mentioning that the present invention further mentions that, while setting the gate driving signals VG1 and VG2 of the second display area 112, the gate driving circuit 130 may also be based on the magnitude of the first load and the second load. The gate driving signals VG3 to VGn coupled to the first display area 111 are set to shorten the enabling time of the gate driving signals VG3 to VGn by a time TSDT2, so that each first pixel receives the data voltage VS (For example, the source driving signals VS1 to VSn), the charging time is reduced, so that the display image brightness of the first display area 111 and the second display area 112 can be set at the same time. The time TSDT1 will be greater than the time TSDT2, that is, In this embodiment, the second display area 112 with a relatively high brightness (ie, a smaller load) is shortened to enable more time, so that the brightness of the second display area 112 is reduced by a larger amount, and That is, the first display area 111 is shortened by a short time TSDT2, and the brightness of the first display area 111 is reduced by a small amount. In this way, the second display area 112 and the first display area 111 can be reduced. Brightness uniformity is improved to achieve The purpose of uniformizing the brightness of the display image of the display panel 110.

In addition, please refer to FIG. 3A and FIG. 4B simultaneously. FIG. 4B is a schematic diagram of driving signal waveforms of the implementation method of setting the gate driving signal enable time in the embodiment of FIG. 3A of the present invention. The difference from the embodiment in FIG. 1 lies in that the gate driving circuit 330 in this embodiment sets the gate driving signal VG (for example, the gate driving signal VG in the first display area 311 according to the magnitude of the first load, the second load, and the third load), for example, Are gate driving signals VG3 to VGn-2), gate driving signals VG in the second display area 312 (eg, gate driving signals VG1, VG2), and gate driving signals VG in the third display area 313 (eg, It is the enabling time of at least one of the gate driving signals VGn-1, VGn). In other words, the gate driving circuit 330 can set the gate driving signals VGn-1, VGn according to the magnitude of the first load, the second load, and the third load, so that the gate driving signals VGn-1, The enabling time of VGn is shortened by a time TSDT3 to set the charging time of the plurality of third pixels in the third display area 313 to receive the data voltage VS (for example, the source driving signals VS1, VS2, VSn-1, VSn). That is, in this embodiment, the charging time of each first pixel, each second pixel, and each third pixel can be set at the same time, or only the charging time of each second pixel and each third pixel can be set at the same time. It is also possible to set only the charging voltage of each second pixel or only the charging voltage of each third pixel. Those skilled in the art can determine the first pixel, the second pixel, and each of the present invention according to the actual application. The charging time of the third pixel is set, which is not limited in the present invention.

In addition, it should be noted that the present invention does not limit the size of the third load and the second load. Those skilled in the art can determine whether the time TSDT3 is greater than the time according to the size of the third load and the second load in actual application. TSDT1 is used to control the brightness of the displayed images of the third display area 313 and the second display area 312 so as to improve the brightness uniformity of the first display area 311, the second display area 312 and the third display area 313, so as to achieve The purpose of uniform display brightness of the display image of the display panel 110.

Please refer to FIG. 1 and FIG. 5A simultaneously. FIG. 5A is a schematic diagram of a driving signal waveform of the implementation of setting the switch control signal enable time in the embodiment of FIG. 1 of the present invention. In this embodiment, the display panel 110 in the display device 100 further includes a plurality of first multiplexers and a plurality of second multiplexers. The plurality of first multiplexers include a plurality of first switches to receive a plurality of first switch control signals (for example, the first switch control signals VMR1, VMG1, and VMB1), and each first multiplexer corresponds to a second Display area 112. The plurality of second multiplexers include a plurality of second switches to respectively receive a plurality of second switch control signals (for example, the second switch control signals VMR2, VMG2, and VMB2), and each second multiplexer corresponds to the first A display area 111. In addition, the source driving circuit 120 includes a timing controller, which is coupled to each of the first multiplexers and each of the second multiplexers, and is used to provide each of the first switch control signals VMR1, VMG1, VMB1, and each of the second switches. The control signals VMR2, VMG2, and VMB2 go to each of the first switches and each of the second switches.

The source driving circuit 120 sets the first switching control signals VMR1, VMG1, VMB1 and the settings in the first display area 111 according to the magnitude of the first load and the second load. The enabling time of at least one of the second switch control signals VMR2, VMG2, and VMB2 is used to set the charging of the plurality of first pixels in the first display area 111 and the plurality of second pixels in the second display area 112. time. To explain in detail, the source driving circuit 120 in this embodiment sets the first switch control signals VMR1, VMG1, and VMB1 according to the magnitude of the first load and the second load, so that the first switch control signals VMR1, The enabling time of VMG1 and VMB1 is shortened by one time TRGB1, thereby reducing the time that each first switch in each first multiplexer is turned on to reduce the data voltage VS (for example, the source driving signals VS1, VS2, VSn -1, VSn) (for example, the data Rdata, Gdata, Bdata) charging time for each second pixel, thereby reducing the brightness of the image displayed in the second display area 112, so that the first display area 111 and the first The brightness of the displayed images in the two display areas 112 is substantially the same, and the purpose of making the brightness of the displayed images of the display panel 110 uniform is achieved.

It is worth mentioning that the present invention further mentions that while the source driving circuit 120 sets each of the first switch control signals VMR1, VMG1, and VMB1 transmitted to the second display area 112, the source driving circuit 120 may also be based on The size of the first load and the second load sets the second switch control signals VMR2, VMG2, and VMB2 transmitted to the first display area 111, so that the enable times of the second switch control signals VMR2, VMG2, and VMB2 are enabled. Each time is shortened by TRGB2, so that the charging time of the data Rdata, Gdata, and Bdata in each of the first pixels receiving the data voltage VS (for example, the source driving signals VS1 to VSn) is shortened, thereby setting the first display area 111 and The brightness of the display image in the second display area 112, wherein the time TRGB1 will be greater than the time TRGB2, that is, each of the first switch control signals VMR1 in the second display area 112 that originally had a higher brightness (ie, a smaller load) is used. The enabling time of VMG1 and VMB1 is shortened by a longer time TRGB1 to reduce a larger brightness, and the second switch control signals VMR2 and VMG2 in the first display area 111 with lower brightness (that is, a larger load) are reduced. The enabling time of VMB2 is shortened by a shorter time TRGB2, so as to reduce the brightness to a smaller extent, thereby improving the brightness uniformity of the second display area 112 and the first display area 111, so as to achieve the purpose of uniformly emitting light from the display panel 110.

In addition, please refer to FIG. 3A and FIG. 5B simultaneously. FIG. 5B is a schematic diagram of driving signal waveforms of the implementation of setting the switch control signal enable time in the embodiment of FIG. 3A according to the present invention. The difference from the embodiment in FIG. 1 lies in that the display panel 310 in the display device 300 of this embodiment further includes a plurality of third multiplexers. The plurality of third multiplexers include a plurality of third switches to receive a plurality of third switch control signals (for example, the third switch control signals VMR3, VMG3, VMB3), and each third multiplexer corresponds to the third Display area 313. The source driving circuit 320 sets each of the first switching control signals VMR1, VMG1, VMB1, and the first display area 311 transmitted to the second display area 312 according to the sizes of the first load, the second load, and the third load. The enabling time of each of the second switch control signals VMR2, VMG2, VMB2 and at least one of the third switch control signals VMR3, VMG3, VMB3 transmitted to the third display area 313. In other words, the source driving circuit 320 can set the third switching control signals VMR3, VMG3, and VMB3 according to the magnitudes of the first load, the second load, and the third load, so that the third switching control signals VMR3, The enabling time of VMG3 and VMB3 is shortened by a time TRGB3, so as to reduce the data Rdata in the third display area 313 receiving data voltage VS (for example, source drive signals VS1, VS2, VSn-1, VSn) of the third pixels , Gdata, Bdata charging time, that is, in this embodiment, the charging time of each first pixel, each second pixel, and each third pixel can be set at the same time, or only each second pixel and each third pixel can be set at the same time. The charging time of three pixels can also be set separately for each second pixel or only the charging voltage for each third pixel. Those with ordinary knowledge in the art can determine the first pixels, The charging time of each second pixel and each third pixel is set, which is not limited in the present invention.

In addition, it should be noted that the present invention does not limit the size of the third load and the second load. Those skilled in the art can determine whether the time TRGB3 is greater than the time according to the size of the third load and the second load in actual application. TRGB1, to control the display image brightness of the third display area 313 and the second display area 312, thereby improving the uniformity of the brightness of the first display area 311, the second display area 312, and the third display area 313 to achieve a display panel The purpose of 110 display image brightness uniformity.

Please refer to FIG. 1 and FIG. 6A at the same time. FIG. 6A is a schematic diagram of a waveform of a source driving signal according to the embodiment of FIG. In this embodiment, each source driving signal VS (for example, source driving signals VS1 to VSn) will correspondingly drive the second display area 112 in the first time interval, and correspondingly drive the first display area in the second time interval. 111. The source driving circuit 120 sets the source driving signals VS1 to VSn as the voltage level Vp- in the first time interval according to the first load of the first display area 111 and the second load of the second display area 112. DV1, and setting each source driving signal VS1 ~ VSn as the voltage level Vp in the second time interval, wherein the voltage level Vp-DV1 and the voltage level Vp have an offset value DV1.

To explain in detail, during a screen period of this embodiment, the gate driving lines DL1 and DL2 provide the gate driving signals VG1, VG2 to the second display area 112 in the first time interval, and the gate The time interval from when the driving lines DL3 to DLn provide the gate driving signals VG3 to VGn to the first display area 111 is the second time interval. The source driving circuit 120 sets the voltage level of the data voltage (ie, the source driving signals VS1 to VSn) to charge each first pixel and each second pixel according to the magnitude of the first load and the second load. For example, the source driving circuit 120 sets the source driving signals VS1 ~ VSn to the voltage level Vp-DV1 in the first time interval, so that the source driving signals VS1 ~ VSn are no longer in the first time interval. The original normal voltage level Vp reduces the charging voltage of the second pixels by the source driving signals VS1 to VSn. Next, in a second time interval after the first time interval, the source driving circuit 120 will set each of the source driving signals VS1 to VSn to the normal voltage level Vp in the second time interval. Each first pixel is charged at a voltage level Vp. In this way, the image display brightness of the second display area 112 can be reduced to be substantially equal to the image display brightness of the first display area 111, and the reduction of the image display brightness of the second display area 112 can be transmitted through The offset value DV1 is set for control. Those skilled in the art can set the magnitude of the offset value DV1 between the voltage level Vp-DV1 and the voltage level Vp according to the actual application situation, which is not limited in the present invention. .

It should be noted that, when the polarities of the first pixels and the second pixels are reversed, the source driving circuit 120 sets the source driving signals VS1 to VSn to the voltage level Vn + DV3 in the first time interval. So that each source driving signal VS1 ~ VSn is no longer the normal voltage level Vn in the first time interval, thereby reducing the charging voltage of each source driving signal VS1 ~ VSn to each second pixel, And in a second time interval after the first time interval, the source driving circuit 120 sets each of the source driving signals VS1 to VSn to the normal voltage level Vn in the second time interval. Level Vn to charge each first pixel. Since the voltage level Vn is a negative voltage, the absolute value of the voltage level Vn will be greater than the absolute value of the voltage level Vn + DV3, which is the The charging voltage will be greater than the charging voltage of each second pixel, thereby reducing the image display brightness of the second display area 112 and substantially lower than the image display brightness of the first display area 111. The offset can be set by setting Value DV3 to control the image display of the second display area 112 Reduced amplitude, present with ordinary knowledge in the art can be based on the actual application, the voltage level Vn is set an offset value between DV3 size Vn and the voltage level of the + DV3, this invention is not to be defined. In addition, the magnitudes of the offset value DV3 and the offset value DV1 may be the same or different. Those skilled in the art can also adjust according to the actual application situation, which is not limited in the present invention.

In this way, in this embodiment, by setting the voltage level of the data voltage (ie, the source driving signal VS) received by each second pixel in the second display area 112, the charging voltage of each second pixel is set. The absolute value of the voltage level is smaller than the absolute value of the voltage level of the charging voltage of each first pixel, thereby reducing the brightness of the image displayed on the second display area 112, and further allowing the second display area 112 and the first display area 111 to The brightness uniformity is improved to achieve the purpose of uniformly emitting light from the display panel 110.

Please refer to FIG. 3A and FIG. 6B simultaneously. FIG. 6B is a schematic diagram of driving signal waveforms of the data voltage setting method according to the embodiment of FIG. 3A of the present invention. The difference from the foregoing embodiment of FIG. 1 lies in that each source driving signal VS (for example, source driving signals VS1 to VSn) in this embodiment will correspondingly drive the second display area 312 in the first time interval, and in the second time The interval will correspondingly drive the first display area 311 and the third time interval will drive the third display area 313 correspondingly. The source driving circuit 320 sets the source driving signals VS1 to VSn to the voltage level Vp-DV1 in the first time interval according to the magnitude of the first load, the second load, and the third load, and sets each source driving signal VS1. ~ VSn is the voltage level Vp in the second time interval, and each source drive signal VS1 ~ VSn is set in the third time interval as the voltage level Vp-DV2, where the voltage level Vp-DV1 and the voltage level Vp have a The offset value DV1, and the voltage level Vp-DV2 and the voltage level Vp have an offset value DV2.

To explain in detail, during a screen period of this embodiment, the gate driving lines DL1 and DL2 provide the gate driving signals VG1, VG2 to the second display area 312. The time interval is the first time interval, and the gate Drive lines DL3 to DLn-2 provide the gate drive signals from VG3 to VGn-2 to the first display area 311. The second time interval is provided by the gate drive lines DLn-1 to DLn. The time interval from VGn-1 to VGn to the third display area 313 is the third time interval. The source driving circuit 320 sets the data voltages (i.e. source driving) for charging the first pixels, the second pixels, and the third pixels according to the magnitudes of the first load, the second load, and the third load. Signal VS1 ~ VSn), for example, in this embodiment, the source driving circuit 320 sets the source driving signals VS1 ~ VSn at the third time interval in the third time interval after the second time interval. The time interval is the voltage level Vp-DV2, so that the source driving signals VS1 ~ VSn are no longer the normal voltage level Vp in the third time interval, thereby reducing the source driving signals VS1 ~ VSn to each The charging voltage of the third pixel.

In this way, the third pixel can be charged with the voltage level Vp-DV2 in the third time interval, so as to reduce the image display brightness of the third display area 313 to substantially equal to that of the first display area 311. The purpose of image display brightness, and the reduction of the image display brightness of the third display area 313 can be controlled by setting the offset value DV2. Those skilled in the art can set the voltage level Vp-DV2 according to the actual application. The magnitude of the offset value DV2 between the voltage level Vp and the present invention is not limited thereto.

It should be noted that, when the polarities of the first pixels, the second pixels, and the third pixels are reversed, the source driving circuit 320 sets the source driving signals VS1 to VSn in the third time interval as Voltage level Vn + DV4, so that each source driving signal VS1 ~ VSn is no longer the normal voltage level Vn in the third time interval, thereby reducing each source driving signal VS1 ~ VSn to each third picture Since the voltage level Vn is negative, the absolute value of the voltage level Vn will be greater than the absolute value of the voltage level Vn + DV4, that is, the charging voltage of each first pixel will be greater than that of each third pixel. The charging voltage of the element reduces the image display brightness of the third display area 313 accordingly, and decreases to substantially equal to the image display brightness of the first display area 111. The third display area can be controlled by setting the offset value DV4. The image 313 shows a reduction in brightness. Those skilled in the art can set the magnitude of the voltage level Vn + DV4 and the offset value DV4 between the voltage level Vn according to the actual application situation. The present invention does not address this. limited. In addition, the sizes of the offset value DV4 and the offset value DV2 may be the same or different. Those skilled in the art can also set the values according to the actual application situation, which is not limited in the present invention.

On the other hand, the operation mode of the source driving circuit 320 for setting the voltage levels of the source driving signals VS1 to VSn in the first time interval and the second time interval is similar to the embodiment of FIG. 1 described above, and is not repeated here. .

Please refer to FIG. 1 and FIG. 7A at the same time. FIG. 7A is a schematic diagram of a driving signal waveform according to the embodiment of FIG. In this embodiment, each source driving signal VS (for example, source driving signals VS1 to VSn) will correspondingly drive the second display area 112 in the first time interval, and correspondingly drive the first display area in the second time interval. 111. The source driving circuit 120 sets the common voltage VCOM to the voltage level VCOM1 + DVa in the first time interval according to the magnitude of the first load in the first display area 111 and the second load in the second display area 112, and sets the common voltage VCOM1 + DVa. The voltage VCOM is the voltage level VCOM1 in the second time interval, wherein the voltage levels VCOM1 + DVa and VCOM1 have an offset value D Va.

To explain in detail, during a screen period of this embodiment, the gate driving lines DL1 and DL2 provide the gate driving signals VG1, VG2 to the second display area 112 in the first time interval, and the gate The time interval from when the driving lines DL3 to DLn provide the gate driving signals VG3 to VGn to the first display area 111 is the second time interval. The source driving circuit 120 sets the voltage level of the common voltage VCOM when charging the first pixels and the second pixels according to the magnitude of the first load and the second load. For example, the source driving circuit 120 Set the voltage level of the common voltage VCOM to the voltage level VCOM1 + DVa in the first time interval, so that the voltage level of the common voltage VCOM is no longer the normal voltage level VCOM1 in the first time interval, thereby reducing The charging voltage of each source driving signal VS1 ~ VSn for each second pixel (the voltage value of the charging voltage at this time is the voltage level Vp minus the voltage level VCOM1 + DVa). Then, in a second time interval after the first time interval, the source driving circuit 120 sets the voltage level of the common voltage VCOM to the voltage level VCOM1 in the second time interval. In this way, in the second time interval, each first pixel will have a higher voltage value of the charging voltage (the voltage value of the charging voltage at this time is the voltage level Vp minus the voltage level VCOM1). The purpose of reducing the image display brightness of the second display area 112 to be substantially equal to the image display brightness of the first display area 111, and the reduction of the image display brightness of the second display area 112 can be controlled by setting the offset value DVa A person with ordinary knowledge in the art can set the magnitude of the offset value D Va between the voltage level VCOM1 + DVa and the voltage level VCOM1 according to the actual application situation, which is not limited in the present invention.

It should be noted that when the polarities of each first pixel and each second pixel are reversed, the source driving circuit 120 sets the voltage level of the common voltage VCOM to the voltage level VCOM1-DVc in the first time interval, so that The voltage level of the common voltage VCOM is no longer the original normal voltage level VCOM1 in the first time interval, thereby reducing the charging voltage of each source pixel driving signals VS1 to VSn for each second pixel (the charging voltage at this time) The voltage value is the absolute value of the voltage level Vn minus the voltage level VCOM1-DVc).

Then, in a second time interval after the first time interval, the source driving circuit 120 will set the voltage level of the common voltage VCOM to the voltage level VCOM1 in the second time interval. The high charging voltage voltage value (the voltage value of the charging voltage at this time is the voltage level Vn minus the absolute value of the voltage level VCOM1) to charge each first pixel. Since the voltage level Vn is a negative voltage, the voltage The absolute value of the level VCOM1-DVc will be greater than the absolute value of the voltage level VCOM1, that is, the charging voltage of each first pixel will be greater than the charging voltage of each second pixel, so that the image of the second display area 112 is displayed. The brightness is reduced and can be reduced to be substantially equal to the image display brightness of the first display area 111. Among them, the reduction of the image display brightness of the second display area 112 can be controlled by setting the offset value DVc. The magnitude of the offset value DVc between the voltage level VCOM1-DVc and the voltage level VCOM1 can be set according to the actual application situation, which is not limited in the present invention. In addition, the magnitudes of the offset value DVc and the offset value DKa may be the same or different. Those skilled in the art can also set the values according to the actual application situation, which is not limited in the present invention.

In this way, the voltage value of the charging voltage received by each second pixel in the second display area 112 can be reduced, and each of the first pixels in the first display area 111 can receive a higher charging voltage voltage. Value, since the source driving circuit 120 reduces the charging voltage of each second pixel, the brightness of the second display area 112 is reduced, thereby achieving the purpose of setting the brightness uniformity of the display image of the display panel 110.

Please refer to FIG. 3A and FIG. 7B simultaneously. FIG. 7B is a schematic diagram of driving signal waveforms of the embodiment of FIG. 3A of the present invention for setting a common voltage. The difference from the foregoing embodiment of FIG. 1 lies in that each source driving signal VS (for example, source driving signals VS1 to VSn) in this embodiment will correspondingly drive the second display area 312 in the first time interval, and in the second time The interval will correspondingly drive the first display area 311 and the third time interval will drive the third display area 313 correspondingly. The source driving circuit 320 sets the voltage level of the common voltage VCOM in the first time interval as the voltage level VCOM1 + DVa according to the size of the first load, the second load, and the third load, and sets the voltage level of the common voltage VCOM. The voltage level VCOM1 is set in the second time interval, and the voltage level of the set common voltage VCOM is set in the third time interval as the voltage level VCOM1 + DVb. The voltage level VCOM1 + DVa and the voltage level VCOM1 have an offset value. DVa, and the voltage level VCOM1 + DVb and the voltage level VCOM1 have an offset value DVb.

To explain in detail, during a screen period of this embodiment, the gate driving lines DL1 and DL2 provide the gate driving signals VG1, VG2 to the second display area 312. The time interval is the first time interval, and the gate Drive lines DL3 to DLn-2 provide the gate drive signals from VG3 to VGn-2 to the first display area 311. The second time interval is provided by the gate drive lines DLn-1 to DLn. The time interval from VGn-1 to VGn to the third display area 313 is the third time interval. The source driving circuit 320 sets the voltage level of the common voltage VCOM when charging the first pixels, the second pixels, and the third pixels according to the magnitudes of the first load, the second load, and the third load. For example, in this embodiment, in the third time interval after the second time interval, the source driving circuit 320 sets the voltage level of the common voltage VCOM to the voltage level VCOM1 + DVb, so that the common voltage VCOM The voltage level in the third time interval is no longer the original normal voltage level VCOM1, thereby reducing the charging voltage of each source by the source driving signals VS1 ~ VSn (the voltage value of the charging voltage at this time) The voltage level Vp minus the voltage level VCOM1 + DVb).

In this way, each third pixel can be charged with a lower charging voltage in the third time interval, and the image display brightness of the third display area 313 can be reduced to substantially equal to the first display area. The purpose of the image display brightness of 311, and the reduction of the image display brightness of the third display area 313 can be controlled by setting the offset value DVb. Those skilled in the art can set the voltage level VCOM1 according to the actual application. The magnitude of the offset value DVb between + DVb and the voltage level VCOM1 is not limited in the present invention.

It should be noted that when the polarity of each of the first pixel, the second pixel, and the third pixel is reversed, the source driving circuit 320 sets the voltage level of the common voltage VCOM as the voltage in the third time interval. Levels VCOM1-DVd, so that the voltage level of the common voltage VCOM is no longer the normal voltage level VCOM1 in the third time interval, thereby reducing the effect of each source driving signal VS1 ~ VSn on each third pixel. Charging voltage (the voltage value of the charging voltage at this time is the absolute value of the voltage level Vn minus the voltage level VCOM1-DVd). Since the voltage level Vn is a negative voltage, the absolute value of the voltage level VCOM1 will be less than the voltage level The absolute value of VCOM1-DVd, that is, the charging voltage of each third pixel will be smaller than the charging voltage of each first pixel, thereby reducing the image display brightness of the third display area 313, and can be reduced to substantially equal to the first pixel. The brightness of the image display of a display area 311 can be controlled by setting the offset value DVd to reduce the brightness of the image display brightness of the third display area 313. Those skilled in the art can set the voltage level VCOM1 according to the actual application. -DVd and voltage DVd offset between the bit size VCOM1, this invention is not to be defined.

In addition, the source driving circuit 320 sets the operation mode of the voltage level of the common voltage VCOM in the first time interval and the second time interval, which is similar to the embodiment of FIG. 1 described above, and is not repeated here.

Please refer to FIG. 1 and FIG. 8 at the same time. FIG. 8 is a schematic diagram of an embodiment of setting the gamma curve information according to the embodiment of FIG. 1 of the present invention. In this embodiment, each source driving signal VS (for example, source driving signals VS1 to VSn) will correspondingly drive the second display area 112 in the first time interval, and correspondingly drive the first display area in the second time interval. 111. The source driving circuit 120 has reference gamma curve information GamC1 and at least one adjusted gamma curve information (for example, adjusted gamma curve information GamC2), wherein the reference gamma curve information GamC1 (that is, adjusted gamma curve information) The dotted line of the GamC2 waveform corresponds to the first display area 111, and the adjusted gamma curve information GamC2 corresponds to the second display area 112.

The source driving circuit 120 generates each source driving signal VS1 ~ VSn according to the reference gamma curve information GamC1 and provides it to the first display area 111, and generates each source driving signal VS1 ~ VSn according to the adjusted gamma curve information GamC2. To provide to the second display area 112. To explain in detail, the horizontal axis of the reference gamma curve information GamC1 and the adjusted gamma curve information GamC2 is grayscale G, and the vertical axis is the brightness L. The curvature of the reference gamma curve information GamC1 and the adjusted gamma curve information GamC2 is different. That is, the brightness voltage corresponding to the brightness L of the reference gamma curve information GamC1 will be greater than the brightness voltage corresponding to the brightness L of the adjusted gamma curve information GamC2. It should be noted that in order to simplify the description, this embodiment only shows one adjusted gamma curve information GamC2, but those skilled in the art can adjust the amount of adjusted gamma curve information according to the actual application situation. The present invention It is not limited.

The source driving circuit 120 will be set according to the magnitude of the first load and the second load. Since the first load is greater than the second load, the source driving circuit 120 will generate according to the reference gamma curve information GamC1 in the second time interval. Each source driving signal VS1 ~ VSn is provided to provide each source driving signal VS1 ~ VSn to each first pixel in the first display area 111, and the source driving circuit 120 will adjust the gamma in the first time interval according to the adjusted gamma. The Mach information GamC2 generates each source driving signal VS1 ~ VSn to provide each second pixel in the second display area 112 of each source driving signal VS1 ~ VSn.

In this way, since the curvature of the adjusted gamma curve information GamC2 is greater than the curvature of the reference gamma curve information GamC1, that is, the brightness voltage of the adjusted gamma curve information GamC2 is smaller than the brightness voltage of the reference gamma curve information GamC1, this embodiment It is possible to reduce the brightness of the second display area 112 to substantially equal to the brightness of the first display area 111 by providing the brightness voltage of the adjusted gamma curve information GamC2 with a large curvature to the second display area 112. The purpose of improving the uniformity of light emission of the display panel 110 as a whole.

Please refer to FIG. 1 and FIG. 9A simultaneously. FIG. 9A is a schematic diagram illustrating another embodiment of setting the gamma curve information according to the embodiment of FIG. 1 of the present invention. In this embodiment, each source driving signal VS (for example, source driving signals VS1 to VSn) will correspondingly drive the second display area 112 in the first time interval, and correspondingly drive the first display area in the second time interval. 111, and the source driving circuit 120 has reference gamma curve information IDGam and at least one adjusted gamma curve information (for example, adjusted gamma curve information ADGam), where the dotted line in the adjusted gamma curve information ADGam is The waveform of the reference gamma curve information IDGam.

The reference gamma curve information IDGam has multiple grayscale intervals, each of which corresponds to multiple reference brightness intervals, and the multiple grayscale intervals of the adjusted gamma curve information ADGam respectively correspond to multiple adjusted brightness intervals, where The voltage value corresponding to each adjusted brightness interval (ie, the voltage values off1 to offK) will be less than or equal to the voltage value corresponding to each reference brightness interval (ie, the voltage value at the dotted line of the waveform in FIG. 9A). The source driving circuit 120 generates each source driving signal VS1 ~ VSn according to the reference gamma curve information IDGam and provides it to the first display area 111, and generates each source driving signal VS1 ~ VSn according to the adjusted gamma curve information ADGam. And provided to the second display area 112.

To explain in detail, the horizontal axis of the reference gamma curve information IDGam and the adjusted gamma curve information ADGam is grayscale G and the vertical axis is brightness L. The source driving circuit 120 of this embodiment changes the reference gamma curve information IDGam. The gray scale G is divided into K gray scale intervals (for example, gray scale intervals S1 to SK), and the K gray scale intervals S1 to SK correspond to K reference brightness intervals, respectively, and the adjusted gamma curve information ADGam K gray scales The intervals S1 ~ SK will correspond to K adjusted brightness intervals respectively, where the reference gamma curve information IDGam and the adjusted gamma curve information ADGam are different curves, and K is an integer not less than 1.

The voltage value corresponding to each adjusted brightness interval (that is, the voltage values off1 to offK) will be less than or equal to the voltage value corresponding to each reference brightness interval (that is, the dotted line of the waveform in FIG. 9A). For example, adjust in the grayscale interval S1 The voltage value Off1 corresponding to the rear luminance interval is equal to the voltage value corresponding to the reference luminance interval. The voltage value Off2 corresponding to the adjusted luminance interval in the grayscale interval S2 will be smaller than the voltage value corresponding to the reference luminance interval. In the grayscale interval SK-1 The voltage value OffK-1 corresponding to the adjusted brightness interval will be smaller than the voltage value corresponding to the reference brightness interval, and the voltage value OffK corresponding to the adjusted brightness interval in the grayscale interval SK will be equal to the voltage value corresponding to the reference brightness interval. It should be noted that the sizes of the K gray-level intervals in this embodiment may be the same or different. Those with ordinary knowledge in the present invention may adjust the number of gray-level intervals and adjust the corresponding value of each brightness interval according to the actual application situation. The voltage value is not limited by the present invention.

In this way, in this embodiment, the voltage values Off1 to OffK corresponding to the adjusted brightness interval in the adjusted gamma curve information ADGam are set, so that the source driving circuit 120 generates a corresponding second display area according to the adjusted gamma curve information ADGam. The source driving signals VS1 to VSn of 112 and the source driving circuit 120 are configured to generate the source driving signals VS1 to VSn corresponding to the first display area 111 according to the reference gamma curve information IDGam. This is set so that the second display area 112 has a lower brightness, and the brightness uniformity of the second display area 112 and the first display area 111 is improved, so as to achieve the purpose of making the display panel 110 emit light uniformly.

Please refer to FIG. 3A and FIG. 9B simultaneously. FIG. 9B is a schematic diagram illustrating another embodiment of setting the gamma curve information in the embodiment of FIG. 3A of the present invention. The difference from the embodiment shown in FIG. 1 is that the source driving circuit 320 of this embodiment can set and provide the third pixels in the third display area 313 according to the sizes of the first load, the second load, and the third load. And the magnitude of the brightness voltage provided to each second pixel in the second display area 312. To explain in detail, the source driving circuit 320 sets the adjusted gamma curve information ADGam according to the size of the first load, the second load, and the third load, and generates each source driving signal VS1 according to the adjusted gamma curve information ADGam. ~ VSn, and provided to the third display area 313 to reduce the charging voltage of each third pixel and reduce the charging voltage of each third pixel, thereby making the first display area 311, the second display area 312, and the The brightness of the three display areas 313 is uniform, and the adjusted gamma curve information ADGam corresponding to the third display area 313 may be the same as the adjusted gamma curve information ADGam corresponding to the second display area 312, or it may be a different adjusted gamma. The Markov curve information can be adjusted by a person having ordinary knowledge in the art according to the size of the second load and the third load during actual application, which is not limited in the present invention.

In addition, in this embodiment, an operation method of setting the gamma curve information for each of the first pixels and each of the second pixels is similar to that of the embodiment in FIG. 1, and details are not described herein again.

Please refer to FIG. 1 and FIG. 10 at the same time. FIG. 10 is a schematic diagram of another embodiment of setting a common voltage according to the embodiment of FIG. 1 of the present invention. In this embodiment, the source driving circuit 120 provides each of the first common voltage VCOMDC1 to the first display area 111 according to the magnitude of the first load of the first display area 111 and the second load of the second display area 112. The first pixel and each second pixel in the second display area 112 are provided with the second common voltage VCOMDC2, wherein the voltage level of the first common voltage VCOMDC1 is lower than the voltage level of the second common voltage VCOMDC2. To explain in detail, the source driving circuit 120 of this embodiment sets a common voltage having different voltage levels (ie, the first common voltage VCOMDC1 and the second common voltage VCOMDC2) according to the magnitude of the first load and the second load, so that The charging voltage of each first pixel and each second pixel is set.

For example, the source driving circuit 120 may set the first common voltage VCOMDC1 having a lower voltage level as the common voltage of each first pixel in the first display area 111 according to the size of the first load and the second load. A higher charging voltage is set, and a second common voltage VCOMDC2 with a higher setting voltage level is a common voltage of each second pixel in the second display area 112 to set a lower charging voltage. In this way, the charging voltage provided by the source driving circuit 120 to the second pixels of the second display area 112 is low, and the charging voltage provided to the first pixels of the first display area 111 is high. The brightness of the display image in the second display area 112 is reduced to be substantially equal to the brightness of the display image in the first display area 111, so as to improve the uniformity of the overall brightness of the display panel 110 and achieve the purpose of making the brightness of the display image of the display panel 110 uniform.

It is worth mentioning that the embodiments of FIG. 8 and FIG. 10 of the present invention can also be applied to the display device 300 having the first display area 311, the first display area 312, and the third display area 313 in the embodiment of FIG. 3A. The operation mode is similar to the embodiment in FIG. 1 described above, and is not repeated here.

Please refer to FIG. 1, FIG. 3A and FIG. 11A to FIG. 11C simultaneously. FIGS. 11A to 11C are schematic diagrams of different embodiments of the display panel according to the embodiment of the present invention. The shape of the display panel (for example, the display panels 110, 310) in the display device (for example, the display devices 100, 300) in this embodiment may have many different implementations. For example, the display panels 110, 310 may be shown in FIG. 11A The embodiment of the display panel 1110a shown is an L-shape with one bend. The display panel 1110b shown in FIG. 11B may also have a shape in which the panel edge has two rounded corners (ie, rounded corners CV1, CV2) and two right angles. The display panel 1110c shown in FIG. 11C may also have a shape in which the panel edge has rounded corners CV3, a notch area LR, and two right angles, and a shape in which the display panel 1110c has a hollowed-out area HOL. In other words, the present invention does not limit the positions and numbers of the notch shape, rounded corner shape, right-angled shape, notch area, and hollowed-out area in the display panels 110 and 310, that is, the display panel 110 of the present invention , 310 can be any shape.

In summary, the driving circuit of the present invention will be based on the magnitudes of the first loads provided by the plurality of first pixels in the first display area and the second loads provided by the plurality of second pixels in the second display area. Setting the electrical characteristics of each first driving signal and each second driving signal to set the brightness of the first display area and the second display area, thereby improving the uniformity of the brightness of the second display area and the first display area on the display panel, In order to make the display image brightness of the display panel uniform, the display quality is further increased.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

100, 300‧‧‧ display devices

110, 310, 1110a, 1110b, 1110c‧‧‧ display panel

120, 320‧‧‧ source drive circuit

130, 330‧‧‧Gate driving circuit

111, 311, 311a‧‧‧ first display area

112, 312, 312a‧‧‧Second display area

313, 313a‧‧‧ Third display area

CV1, CV2, CV3‧‧‧ rounded corners

DL1 ~ DLn‧‧‧Gate driving line

G‧‧‧Grayscale

HOL‧‧‧Knock Out Area

IDGam, ADGam, GamC1, GamC2 ‧‧‧ Gamma Curve Information

L‧‧‧ Brightness

LIN1 ~ LINn‧‧‧Drive line

LR‧‧‧Notch area

Off1 ~ OffK‧‧‧Voltage

Rdata, Gdata, Bdata

S1 ~ SK‧‧‧Grayscale interval

SL1 ~ SLn‧‧‧Source Drive Line

T1 ~ T5‧‧‧Time interval

TSDT1 ~ TSDT3, TRGB1 ~ TRGB3‧‧‧Time

VCOM‧‧‧ Common Voltage

VDis‧‧‧ Disabled Voltage Level

VEn‧‧‧Enable voltage level

VG, VG1 ~ VGn‧‧‧Gate driving signal

VMR1 ~ VMR3, VMG1 ~ VMG3, VMB1 ~ VMB3‧‧‧ Switch control signal

VS, VS1 ~ VSn‧‧‧Source drive signal

VSSp, VSSn, VGND, Vp, Vp-DV1, Vp-DV2, Vn, Vn + DV3, Vn + DV4, VCOM1, VCOM1 + DVa, VCOM1 + DVb, VCOM1-DVc, VCOM1-DVd, VCOMDC1, VCOMDC2‧‧‧‧ Voltage level

FIG. 1 is a schematic circuit block diagram of a display device according to an embodiment of the invention. FIG. 2A is a schematic diagram of a gate driving signal waveform of the implementation of the slew rate setting method in the embodiment of FIG. 1 according to the present invention. FIG. 2B is a schematic diagram of a waveform of a gate driving signal according to the embodiment of FIG. 1 for setting a voltage level. 3A is a schematic circuit block diagram of a display device according to another embodiment of the present invention. FIG. 3B is a schematic diagram of another embodiment of the display panel according to the embodiment of FIG. 3A of the present invention. FIG. 4A is a schematic diagram of a driving signal waveform in the implementation manner of setting a gate driving signal enable time in the embodiment of FIG. 1 of the present invention. FIG. 4B is a schematic diagram of a driving signal waveform of the implementation of setting the gate driving signal enable time in the embodiment of FIG. 3A according to the present invention. FIG. 5A is a schematic diagram of a driving signal waveform of the implementation of setting the switch control signal enable time in the embodiment of FIG. 1 of the present invention. FIG. 5B is a schematic diagram of a driving signal waveform of the implementation of setting the switch control signal enable time in the embodiment of FIG. 3A according to the present invention. FIG. 6A is a schematic diagram of a waveform of a source driving signal according to the embodiment of FIG. 1 in which a data voltage is set. FIG. 6B is a schematic diagram of a driving signal waveform of the data voltage setting method according to the embodiment of FIG. 3A of the present invention. FIG. 7A is a schematic diagram of a driving signal waveform according to the embodiment of FIG. 1 for setting a common voltage. FIG. 7B is a schematic diagram of a driving signal waveform according to the embodiment of FIG. 3A of the present invention for setting a common voltage. FIG. 8 is a schematic diagram of an embodiment of setting gamma curve information according to the embodiment shown in FIG. 1 of the present invention. FIG. 9A is a schematic diagram of another embodiment of setting gamma curve information according to the embodiment shown in FIG. 1 of the present invention. FIG. 9B is a schematic diagram of another embodiment of setting gamma curve information in the embodiment of FIG. 3A according to the present invention. FIG. 10 is a schematic diagram of another embodiment of setting a common voltage according to the embodiment of FIG. 1 of the present invention. 11A to 11C are schematic diagrams illustrating different embodiments of a display panel according to an embodiment of the present invention.

Claims (16)

A display device includes: a display panel including a first display area and a second display area, the first display area is coupled to a plurality of first drive lines, and the second display area is coupled to a plurality of second drive lines Wherein a first load provided by a plurality of first pixels corresponding to each of the first driving lines is greater than a second load provided by a plurality of second pixels corresponding to each of the second driving lines; and a driving circuit, Coupled to the first driving lines and the second driving lines, for providing a plurality of first driving signals to the first driving lines, and respectively providing a plurality of second driving signals to the second driving lines; Wherein, the driving circuit sets the electrical characteristics of the first driving signals and the second driving signals respectively according to the magnitude of the first load and the second load. The display device according to item 1 of the scope of patent application, wherein the first driving lines and the second driving lines are gate driving lines, and the first driving signals and the second driving signals are gate driving. signal. The display device according to item 2 of the scope of patent application, wherein the driving circuit sets the slew rates of the second driving signals according to the magnitude of the first load and the second load. The display device according to item 2 of the scope of patent application, wherein the driving circuit divides each of the second driving signals into a plurality of time intervals, and sets a plurality of voltage levels so that each of the second driving signals is in the The time intervals are respectively maintained at the corresponding voltage levels, wherein the driving circuit sets at least one of the voltage levels and the time intervals according to the magnitude of the first load and the second load. The display device according to item 2 of the scope of patent application, wherein the driving circuit sets at least one of the first driving signals and the second driving signals according to the magnitude of the first load and the second load. Can time. The display device according to item 1 of the scope of patent application, wherein the first driving lines and the second driving lines are source driving lines, and the first driving signals and the second driving signals are source electrodes The driving signals, wherein each of the first driving signals and each of the second driving signals drive the second display area correspondingly in a first time interval, and drive the first display area correspondingly in a second time interval. The display device according to item 6 of the scope of patent application, wherein the display panel further comprises: a plurality of first multiplexers, including a plurality of first switches respectively receiving a plurality of first switch control signals, and the first multiplexers A second multiplexer corresponding to the second display area; a plurality of second multiplexers including a plurality of second switches respectively receiving a plurality of second switch control signals, the second multiplexers corresponding to the first display area, wherein, The driving circuit sets an enabling time of at least one of each of the first switch control signals and each of the second switch control signals according to the magnitude of the first load and the second load. The display device according to item 6 of the scope of patent application, wherein the driving circuit sets each of the first driving signals and each of the second driving signals in the first time interval according to the magnitude of the first load and the second load. Is a first voltage level, and each of the first driving signal and each of the second driving signals is set to a second voltage level in the second time interval, wherein the first voltage level and the second voltage level The bit has an offset value. The display device according to item 6 of the scope of patent application, wherein the driving circuit sets a common voltage to a first voltage level in the first time interval according to the size of the first load and the second load, and sets The common voltage is a second voltage level in the second time interval, wherein the first voltage level and the second voltage level have an offset value. The display device according to item 6 of the scope of patent application, wherein the driving circuit has a reference gamma curve information and at least one adjusted gamma curve information, and the reference gamma curve information corresponds to the first display area. At least one adjusted gamma curve information corresponds to the second display area. The display device according to item 10 of the patent application scope, wherein the driving circuit generates the first driving signals according to the reference gamma curve information, and generates the second driving signals according to the at least one adjusted gamma curve information. The curvature of the reference gamma curve information is different from the curvature of the at least one adjusted gamma curve information. The display device according to item 10 of the scope of patent application, wherein the reference gamma curve information has a plurality of grayscale intervals, and the grayscale intervals respectively correspond to a plurality of reference brightness intervals, and the at least one adjusted gamma curve information is The grayscale intervals correspond to a plurality of adjusted brightness intervals, and the voltage values corresponding to the adjusted brightness intervals are less than or equal to the voltage values corresponding to the reference brightness intervals. The display device according to item 12 of the scope of patent application, wherein the driving circuit generates the first driving signals according to the reference gamma curve information, and generates the second driving signals according to the at least one adjusted gamma curve information. . The display device according to item 6 of the scope of patent application, wherein the driving circuit provides a first common voltage to each of the first pixels in the first display area according to the size of the first load and the second load. And providing a second common voltage to each of the second pixels in the second display area, wherein a voltage level of the first common voltage is lower than a voltage level of the second common voltage. The display device according to item 1 of the scope of patent application, wherein the display panel further comprises: a third display area, the third display area is coupled to a plurality of third driving lines, and each of the third driving lines corresponds to The plurality of third pixels provide a third load, and the driving circuit is further coupled to the third driving lines to provide a plurality of third driving signals to the third driving lines. The display device according to item 1 of the scope of patent application, wherein the display panel has a notch shape, a rounded corner shape, a right-angled shape, a notched area, or a hollowed-out area.