TWI693515B - Testing method for motherboard and testing system for motherboard - Google Patents

Abstract

A testing method for motherboard is performed by a motherboard testing system, that is electrically connected to a power supply, the motherboard testing system includes a motherboard, and an auxiliary unit, the motherboard includes a central processing unit and a platform controller hub, a first memory, a second memory, and a first network interface, when the platform controller hub selects the first memory, the central processing unit executes a first system image file, and then sending a notification to the first network interface, the auxiliary unit controls the power supply not output power by the platform controller hub, and controls the platform controller hub to select the second memory, and then controls the platform controller hub, the power supply is output by the power supply to cause the central processing unit to execute a second system image file.

Description

Motherboard testing method and motherboard testing system

The invention relates to a test method and a test system with an internal control program, in particular to a micro-command control or micro-program control test method and test system.

Referring to FIG. 1, the existing motherboard a1 loads different settings according to different combinations of pins set on the motherboard by a jumper a2 during boot test. Generally speaking, the jumper a2 It is manually set on the pins to make them conductive.

However, it is limited by the need to manually set jumper caps to perform relevant tests on the motherboard, which will waste a lot of human resources and not in line with economic benefits. Therefore, how to automatically test the motherboard is the future research direction.

Therefore, an object of the present invention is to provide a control board The platform path controller allows the central processor to automatically switch to read the relevant system image file, without the need for manual control of the motherboard test method.

Therefore, the motherboard testing method of the present invention is executed by a motherboard testing system for receiving operating power provided by a power supply and operating in one of a disabled state and a consistent energy state. The motherboard testing system Contains a motherboard and an auxiliary unit.

The motherboard includes a central processor, a platform path controller electrically connecting the central processor and the power supply, a first memory electrically connecting the platform path controller and storing a first system image file, a A second memory electrically connected to the platform path controller and storing a second system image file.

The auxiliary unit is electrically connected to the platform path controller, and the auxiliary unit includes a jig network interface port, a microcontroller, a first relay module, and a second relay module, the jig network The interface port is used to receive a notification signal sent by the central processor. The microcontroller includes a logic operation unit electrically connected to the jig network interface port to receive the notification signal sent by the central processor. A relay module and the second relay module are electrically connected to the logic operation unit and the platform path controller.

The motherboard testing method includes one step (B3), one step (B7), one step (B8), one step (B9), and one step (B10).

The step (B3) is that when the platform path controller selects the first memory according to the setting of the auxiliary unit, the central processing unit passes the platform path controller Read and execute the first system image file.

The step (B7) is that the auxiliary unit sends a shutdown signal to the power supply via the platform path controller according to a notification signal sent by the central processor, so that the power supply does not provide operating power to the motherboard To enable the motherboard to operate in the disabled state.

The step (B8) sets the platform path controller for the auxiliary unit to switch to selecting the second memory, wherein the logic operation unit controls the second relay module to generate a boot setting to the platform path controller, Switching an image file setting corresponding to the platform path controller to select the second memory.

The step (B9) is that the auxiliary unit sends a power-on signal to the power supply via the platform path controller according to the notification signal, and the power supply provides operating power to the motherboard to enable the motherboard to operate at the enabling status.

In this step (B10), the central processor reads and executes the second system image file via the platform path controller.

In addition, another object of the present invention is to provide a system for testing a motherboard by controlling the platform path controller of the motherboard so that the central processor can automatically switch to read the relevant system image file without manual control.

Therefore, the present invention is a motherboard testing system for receiving power provided by a power supply and operating in one of a disabled state and a consistent energy state, which includes a motherboard and an auxiliary unit.

The motherboard includes a central processor, a platform path controller, a first memory, and a second memory.

The platform path controller electrically connects the central processor and the power supply.

The first memory is electrically connected to the platform path controller and stores a first system image file.

The second memory is electrically connected to the platform path controller and stores a second system image file.

The auxiliary unit is electrically connected to the platform path controller, and the auxiliary unit includes a jig network interface port, a microcontroller, a first relay module, and a second relay module, the jig network The interface port is used to receive a notification signal sent by the central processor. The microcontroller includes a logic operation unit electrically connected to the jig network interface port to receive the notification signal sent by the central processor. A relay module and the second relay module are electrically connected to the logic operation unit and the platform path controller.

When the auxiliary unit sets the platform path controller to select the first memory, the central processor reads and executes the first system image file through the platform path controller, and the auxiliary unit sends Notification signal to send a shutdown signal to the power supply via the platform path controller, so that the power supply does not provide operating power to the motherboard, and then the motherboard operates in the disabled state, the auxiliary unit according to The notification signal controls to set the platform path controller to switch to select Select the second memory, wherein the logic operation unit controls the second relay module to generate a boot setting to the platform path controller to switch an image file setting corresponding to the platform path controller to select the second memory Two memories, the auxiliary unit controls the platform path controller to send a power-on signal to the power supply according to the notification signal, so that the power supply provides operating power to the motherboard, and then the motherboard operates again in the And the central processor reads and executes the second system image file via the platform path controller.

The effect of the present invention is that the auxiliary unit controls the power supply to provide/not provide operating power to the motherboard through the platform path controller according to the notification signal, so that the motherboard switches between the disabled state and the enabled state, and During the board switching, the auxiliary unit controls the setting of the platform path controller according to the notification signal to switch the image file settings to select different memories to enable the central processor to read and execute different systems after the motherboard is switched on and turned on. Image file.

a1: motherboard

a2: jumper cap

1: Power supply

2: motherboard

20: System memory

21: CPU

22: Hard disk module

23: platform path controller

34: Second relay module

4: Test the server

(A): Step of sending trigger signal

(B): Steps to run the test program

(B3): Main system image test substep

(B4): Send notification substep

(B5): Read the batch file substep

(B6): Wait for substep

24: First memory

25: second memory

28: The first network interface port

29: Second network interface port

3: auxiliary unit

31: Fixture network interface port

32: Microcontroller

321: Logic operation unit

322: Memory

33: The first relay module

331: Signal input terminal

332: Control terminal

333: The first signal output

334: Second signal output

(B7): Control shutdown substep

(B8): Control switching substep

(B9): Control boot substep

(B10): Backup system image test substep

(C): trigger test program steps

(D): Steps to execute the test program

(D3): Main system image test substep

(D4): Send notification substep

(D5): Read the batch file substep

(D6): Wait for substep

(D7): control shutdown substep

(D8): Control switching substep

(D9): Control boot substep

(D10): Sub-step of testing the backup system image file

Other features and functions of the present invention will be clearly presented in the embodiments with reference to the drawings, in which: FIG. 1 is a partial schematic diagram illustrating the existing motherboard; FIG. 2 is a schematic diagram illustrating the motherboard testing system of the present invention A first embodiment of FIG. 3 is a partial schematic diagram to help explain a first and second relay of this embodiment The operation mechanism of the module; FIG. 4 is a flowchart illustrating the motherboard testing method performed by the embodiment; FIG. 5 is a flowchart illustrating the operation test program steps of the motherboard testing method; FIG. 6 is a schematic diagram , Illustrating a second embodiment of the motherboard testing system of the present invention; FIG. 7 is a flowchart illustrating the motherboard testing method performed by this embodiment; and FIG. 8 is a flowchart illustrating the first of the motherboard testing methods Run the test program steps.

First embodiment

Referring to FIG. 2, a first embodiment of a motherboard testing system for receiving power provided by a power supply 1 and operating in one of a disabled state and a consistent energy state according to the present invention includes a motherboard 2 , An auxiliary unit 3, and a test server 4.

The motherboard 2 includes a central processing unit 21, a hard disk module 22, a platform path controller 23, a first memory 24, a second memory 25, a first network interface port 28, and a Second network interface port 29.

The hard disk module 22 is connected to the central processing unit 21 via the platform path controller, and stores a test corresponding to a trigger signal for the central processing unit 21 to execute Program.

The platform path controller 23 (PCH: Platform Controller Hub) electrically connects the central processor 21 and the power supply 1 to receive and transmit the trigger signal to the central processor 21.

It should be noted that when the power supply 1 receives external AC power (eg, commercial power), the power supply 1 will provide power for the motherboard to start operation and standby when the motherboard is turned on. When the motherboard is shut down, the power supply 1 does not provide the power required for the motherboard to start up, but it will continue to provide standby power to the platform path controller 23 of the motherboard. Therefore, the platform path controller 23 In the system shutdown state, it can detect the power-on control signal generated by a user pressing the power-on button.

In addition, the central processing unit 21 and the platform path controller 23 are electrically connected to each other through a direct media interface (DMI), that is, a bus. The central processing unit 21 receives the platform path controller 23 according to The trigger signal is used to read and execute the test program stored in the hard disk module 22.

Generally speaking, the motherboard is usually equipped with two chips used to establish data transmission channels between the central processing unit and peripheral devices: Southbridge and Northbridge; Southbridge is mainly responsible for low-speed data bus transmission, such as serial high-end technology attachment (Serial ATA: Serial Advanced Technology Attachment) bus and local area network (LAN: Local Area Natwork); Northbridge is responsible for the interconnection of higher-speed peripheral components Quasi (PCI-E: Peripheral Component Interconnect Express) bus and random access memory (RAM: Random Access Memory) read, but because the speed of the central processor continues to increase today, but the bandwidth of the front-end bus is not Change, (that is, the connection between the central processing unit and the north bridge), and the platform path controller redistributes various data bus input/output functions, which integrates the memory controller and peripheral components interconnection standard controller and the central processing unit It is a chipset and replaces some of the original feature sets of the South Bridge and North Bridge and connects to other data bus input/output, such as: audio devices, serial high-end technology attached bus, universal serial bus (USB: Universal Serial) Bus), and local area network.

The first memory 24 is electrically connected to the platform path controller 23 and stores a first system image file related to the test program.

The second memory 25 is electrically connected to the platform path controller 23 and stores a second system image file related to the test program.

Wherein, the first and second memories 24 and 25 are non-volatile memory (NVM: Non-Volatile memory) types of flash memory (Flash memory), and the first and second system image files are Basic input output system image file (BIOS: Basic Input Output System).

The platform path controller 23 is electrically connected to the auxiliary unit 3 and is controlled by the setting of the auxiliary unit 3 to select one of the first and second memories 24 and 25.

The first network interface port 28 is electrically connected to the platform path controller 23 and used To receive the trigger signal transmitted externally.

The second network interface port 29 is electrically connected to the platform path controller 23 and receives a notification signal sent by the central processor 21 via the platform path controller 23.

The auxiliary unit 3 includes a jig network interface port 31, a microcontroller 32, a first relay module 33, and a second relay module 34.

The jig network interface port 31 is electrically connected to the second network interface port 29 and receives the notification sent from the central processor 21 and transmitted to the second network interface port 29 via the platform path controller 23 signal.

The microcontroller 32 includes a logic operation unit 321 electrically connected to the jig network interface port 31 to receive the notification signal sent by the central processor 21, and an external form electrically connected to the logic operation unit 321 and stores related information The memory 322 of the batch file of the notification signal.

The first relay module 33 is electrically connected to the logic operation unit 321 and the platform path controller 23, and when executing the batch file according to the logic operation unit 321, transmits an on/off analog signal to the platform path Controller 23, and the platform path controller 23 controls the power supply 1 to provide/not provide operating power to the motherboard 2 according to the received on/off analog signal, so that the motherboard 2 operates in the enabled state and This disabled state is one of two. It should be further explained that the first relay module 33 is directly electrically connected to the general purpose input output pin (GPIO pin: General Purpose Input Output pin) of the platform path controller 23 to transmit the on/off analog signal Signal to the platform path controller 23, and the platform path controller 23 controls the power supply 1 according to the on/off analog signal, correspondingly enabling the power supply 1 to provide/not provide power to the motherboard 2 .

In this embodiment, for the switching mechanism of the power supply 1 to control the supply/non-operation power supply, the microcontroller 32 of the auxiliary unit 3 controls the first relay module 33 to quickly switch from a high potential ( pull high) to switch to the low potential (pull low), and then switch back to the high potential (pull high) to simulate and replace the conventional action of the user pressing the power button to generate a power-on control signal, refer to FIG. 3 for further details on this The detailed operation mechanism of the first relay module 33, the first relay module 33 has a signal input terminal 331, a control terminal 332, a first signal output terminal 333, and a second signal output terminal 334, the The mechanism of the first relay module 33 simulating a pulse signal output is as follows: the signal input terminal 331 is grounded, and is electrically connected to the second signal output terminal 334 by default, and the first signal output terminal 333 is electrically connected to the platform path controller A power switch control pin of 23 is electrically connected to a resistor R1 that receives a voltage source V _CC . Therefore, the voltage level of the first signal output terminal 333 is preset to a high potential, and the second signal output terminal 334 floats Then, the control terminal 332 controls the signal input terminal 331 to be electrically connected to the universal input and output pins of the platform path controller 23 to input a low potential to the platform path controller 23, after a first pulse Switch back after a period of time (about 0.3 seconds to 0.5 seconds), that is, disconnect the first relay module 33 from the first signal output terminal 333 and the grounded signal input terminal 331 that are electrically connected to a high potential Connect so that a low voltage pulse can be generated.

The second relay module 34 is electrically connected to the logic operation unit 321 and electrically connected to the two general-purpose input and output pins of the platform path controller 23 to transmit a boot setting to the platform path controller 23, the The boot setting corresponds to the first and second system image files stored in the first and second memories 24 and 25, respectively. When the second relay module 34 executes the batch file according to the logical operation unit 321, the The second relay module 34 provides the boot setting to the platform path controller 23 in a controlled manner, and the platform path controller 23 selects one of the first and second memories 24 and 25 according to the boot setting As the target basic input and output system image file to be executed during the boot.

On the other hand, the platform path controller 23 selecting the first and second image files of the first and second memories 24 and 25 can be divided into the following three modes for implementation:

1. The two universal input and output pins of the platform path controller 23 correspond to the first and second system image files stored in the first and second memories 24 and 25, respectively, and The voltage level received by the I/O pin is used as the boot setting, and the internal image file setting is correspondingly switched to correspondingly select one of the first and second memories 24, 25, and then set to select the The target basic input/output system image file to be executed during the second boot, for example, when one of the general-purpose input/output pins receives a high potential, the platform path controller 23 selects the first memory 24 to select the corresponding setting The first system image file is used as the target basic input and output system image file to be executed during the boot.

2. The platform path controller 23 uses the voltage level received by a specific universal input and output pin of its own as the boot setting, and switches its internal image file setting to correspondingly select the first and second memories One of 24 and 25, to set the target basic input/output system image file to be selected for this boot. For example, when the voltage level received by the specific general-purpose input/output pin is high, then the The platform path controller 23 is electrically connected to the first memory 24, so as to select and set the corresponding first system image file as the target basic input/output system image file to be executed during the boot, otherwise, select and set the corresponding The second system image file.

It should be further explained that the implementation mode of the platform path controller 23 selecting one of the first and second memories 24 and 25 is as follows: two sets of busbars of the platform path controller 23 are connected to the first 1. The second memory 24, 25, and the platform path controller 23 switches its internal image file setting according to the boot setting control to select one of the first and second memory 24, 25.

3. Another implementation mode is that the platform path controller 23 controls the switching of a switch module (not shown) electrically connected to the first and second memories 24 and 25 according to the boot setting, so as to communicate with the One of the first and second memories 24 and 25 is electrically conductive.

The test server 4 is electrically connected to the first network interface port 28, and sends an address to the first network interface port 28 via the Dynamic Host Configuration Protocol (DHCP), and is used to determine the address Send the trigger Signal to the first network interface port 28. In addition, the test server 4 can search for a computer device with a fixed address within its local network connection range through a dynamic host setting protocol, and the auxiliary unit 3 The jig network interface port 31 has a fixed address, so the test server 4 can search for the fixed address through a dynamic host setting protocol and send the fixed address to the second network of the motherboard 2 The interface port 29 allows the CPU 21 of the motherboard 2 to send the notification signal to the auxiliary unit 3 via the platform path controller 23 and the second network interface port 29 via the fixed address It has a network interface port 31. In addition, the test server 4 can transmit the address assigned to the first network interface port 28 to the jig network interface port 31 of the auxiliary unit 3.

Referring to FIG. 4, a motherboard testing method performed in this embodiment includes a step (A) of sending a trigger command and a step (B) of an operation test program.

The step of sending the trigger signal is (A): the test server 4 sends the trigger signal to the first network interface port 28 according to the address assigned to the first network interface port 28, and passes through the platform The path controller 23 transmits to the central processor 21.

The operation test program step is (B): the central processing unit 21 executes the test program stored in the hard disk module 22 according to the trigger signal.

Referring to FIG. 5, in detail, the operation test program step (B) further includes a main system image file test substep (B3), a send notification substep (B4), a batch file read substep (B5), One wait substep (B6), one control shutdown substep (B7), one control switching substep (B8), one control boot Sub-step (B9), and a backup system image test sub-step (B10).

. The main system image file test substep (B3) is: the central processing unit 21 executes the selected target basic input/output system image file, for example, the second relay module 34 is controlled according to the preset operation of the logic operation unit 321, Then, the second relay module 34 provides the preset boot setting to the platform path controller 23, and the platform path controller 23 selects the first memory 24 as the second boot according to the preset boot setting The target basic input/output system image file to be executed, so that the central processing unit 21 executes the first system image file stored in the first memory 24 to perform system hardware configuration related to the first system image file Testing, that is, performing a power-on self-test (POST: Power-on Self-test) related to hardware configuration.

The sending notification sub-step (B4) is: when the central processing unit 21 executes the first system image file and then sends the notification signal to the platform path controller 23 and transmits it to the second via the platform path controller 23 Network interface port 29.

The substep (B5) of reading the batch file is: the jig network interface port 31 receives the notification signal from the second network interface port 29, and the logic operation unit 321 receives the notification signal from the jig network interface port 31 The notification signal reads and executes the batch file stored in the memory 322.

The waiting sub-step (B6) is to make the logic operation unit 321 wait for a predetermined time (for example, any one of 1 to 60 seconds) by executing the batch file.

The control shutdown sub-step (B7) is that the logic operation unit 321 is based on The test server 4 is assigned to the address of the motherboard 2 to control the first relay module 33 to generate an on/off analog signal to the platform path controller 23, so that the platform path controller 23 Switch the power supply 1 to the disabled state.

It should be further explained that in the control shutdown sub-step (B7), the first relay module 33 generates the ON/OFF analog signal through its pin electrically connected to the platform path controller 23 A high/low peak pulse signal is simulated and transmitted to the platform path controller 23 to control the power supply to turn off the power.

The control switching sub-step (B8) is: the logic operation unit 321 controls the second relay module 34 to generate the boot setting to the platform path controller 23 to switch the image file setting of the platform path controller 23 to Select the second memory 25.

The control boot sub-step (B9) is: the logic operation unit 321 controls the first relay module 33 to generate another boot analog signal to the platform path controller 23 to switch the power supply to the enabled state .

The sub-step (B10) of the backup system image file test is: when the power supply 1 operates in the enabled state and outputs operating power to the motherboard for the CPU 21 to operate, the CPU 21 then passes the The platform path controller 23 reads the second system image file stored in the second memory 25 according to the selected second memory 25 to execute the hardware configuration related to the second system image file.

The above process can be further integrated and divided into two approaches:

1. The platform path controller 23 receives the trigger message of the test server 4 Number, which in turn causes the central processor 21 to execute the test program stored in the hard disk module 22, and then executes the test program by the central processor 21, and sends a batch file to the microcontroller 32 of the auxiliary unit 3, At the same time, the central processing unit 21 loads the basic input/output system selected according to the power-on setting via the platform path controller 23, and the microcontroller 32 receives and stores the batch file and executes the batch file. After counting a preset time (after waiting for the CPU 21 to execute the basic input/output system and the power-on self-test procedure is completed), the microcontroller 32 controls the first relay module 33 to send on/off An analog signal (high/low peak pulse signal) causes the platform path controller 23 to perform a shutdown procedure, and the microcontroller 32 then switches the second relay module to enable the platform path controller 23 to select another basic after the next boot Input and output system. Then the microcontroller 32 again controls the first relay module 33 to send an on/off analog signal to cause the platform path controller 23 to notify the central processor 21 to start up, and the central processor 21 is then loaded and Another basic input/output system selected by the platform path controller 23 is executed.

2. The platform path controller 23 receives the trigger signal of the test server 4, and then causes the central processor 21 to execute the test program stored in the hard disk module 22, and then causes the central processor 21 to execute the platform path controller 23 selected target basic input output system. After the target basic input and output system is executed to complete the power-on self-test, the central processing unit 21 executes the test program again and sends a batch file to the microcontroller 32 of the auxiliary unit 3 to store the microcontroller 32 And execute the batch file, The microcontroller 32 controls the first relay module 33 to send an on/off/machine simulation signal to the platform path controller 23 by executing the batch file, and the platform path controller 23 according to the on/off simulation signal A shutdown procedure is performed, and then the microcontroller 32 controls the second relay module 34 to send the boot setting to the platform path controller 23 and execute subsequent related procedures.

It should be further explained that the first and second memories 24 and 25 that store the first system image file and the second system image file respectively also store a first label code and a second label code to When the central processor 21 of the mainboard 2 executes the system image file, it can distinguish which system image file is currently executed, to avoid repeated execution and wasting test time.

In addition, the following further supplements the detailed method for selecting one of the first and second memories 24, 25 regarding the platform path controller 23: When booting, the platform path controller 23 is based on the current basic input The output system image file selects the relevant general purpose input output (GPIO: General purpose input output) pin to select a target basic input and output system, and the central processing unit 21 starts to execute the target basic input and output system image file for power-on. After the POST (Power on Self Test) procedure, the platform path controller 23 sends a notification to start the power-on self-test to the auxiliary unit 3, and the auxiliary unit 3 receives the notification to start the power-on self-test After that, the microcontroller 32 of the auxiliary unit 3 starts to execute its batch file according to the notification, and the microcontroller 32 waits for a preset time by executing the batch file After that, an on/off analog signal simulating a low peak pulse signal is output to the platform path controller 23, so that the platform path controller 23 receives the on/off analog signal of the low peak pulse signal for shutdown action. The preset time will be greater than or equal to the time required to complete the power-on self-test, and then the platform path controller 23 selects the second relay module 34 before sending it through the first relay module 33 It is equivalent to the on/off analog signal generated when the physical button is pressed. The platform path controller 23 performs off/on based on the received on/off analog signal and the current system is on or off. Therefore, the platform path The controller 23 will start the system for the second time according to the received on/off analog signal, and select another basic input/output system according to the switched general-purpose input/output pin, and perform subsequent related procedures.

In the first embodiment of the motherboard testing system of the present invention described above, the test server sends a trigger signal to the first network interface port according to the address assigned to the first network interface port and passes through the platform The path controller transmits to the central processor, so that the central processor executes the test program in the hard disk module according to the trigger signal, and after executing the first system image file according to the content of the test program, then sends a notification signal Through the platform path controller to the second network interface port, in addition, the test server finds a fixed address of the jig network interface face through the dynamic host setting protocol, the second network interface The port can transmit the notification signal to the jig network interface port according to the fixed address, and then to the logic operation unit through the jig network interface port, and the logic operation unit executes the memory according to the notification signal store Batch file based on the address assigned to the first network interface port by the test server, and then the first relay module and the platform path controller to control the power supply to operate in the disabled The state does not output operating power, and then the setting of the second relay module causes the platform path controller to select the second memory, and does not select the first memory, for example, the platform path controller, root The setting of the second relay module allows the central processor to be electrically connected to the second memory through the platform path controller, but the central processor and the first memory are disconnected by the internal circuit of the platform path controller An electrical connection to a memory, and then the logic operation unit controls the first relay module and the platform path controller according to the content of the batch file to switch the power supply to operate in the enabled state to output electrical energy, The central processor executes the second system image file stored in the second memory through the platform path controller and the selected second memory, so there is no need to control the central processor and The setting selection state of the first and second memories and the switch of the power supply provided by the power supply to meet the requirements of saving manpower.

Second embodiment

Referring to FIG. 6, a second embodiment of the motherboard testing system of the present invention differs from the first embodiment in that the motherboard 2 includes a system memory 20 electrically connected to the central processing unit 21, and the system memory 20 A batch file with a trigger signal is stored to replace the test server 4 of the first embodiment.

It should be further explained that the jig network interface port 31 has a fixed address, And an external address can be assigned to the second network interface port 29 by DHCP (Dynamic Host Configuration Protocol), and according to the external address, the logic operation unit 321 can pass the first, The second relay modules 33 and 34 control the motherboard to switch to one of a uniform energy state and a disabled state in a controlled manner.

Referring to FIG. 7, a motherboard testing method executed by the second embodiment includes a trigger test procedure step (C) and a test procedure execution step (D).

The step of the trigger test program is (C) and the step of sending the trigger signal of the first embodiment is (A) The difference is that the central processor 21 reads 20 the batch file with the trigger signal from the system memory 20 .

The step of executing the test program is (D): the central processor 21 executes the test program stored in the hard disk module 22 according to the trigger signal.

Referring to FIG. 8, the step (D) of executing the test program further includes a main system image file testing substep (D3), a sending notification substep (D4), a reading batch file substep (D5), and a waiting substep Step (D6), a control shutdown substep (D7), a control switching substep (D8), a control startup substep (D9), and a backup system image file test substep (D10).

The difference between the sub-steps of the step (D) of the execution test program and the sub-steps of the step (B) of the operation test program of the first embodiment is that the sub-step of sending the notification (D4) and the control shutdown Substep (D7), the control The control switching sub-step (D8), and the control starting sub-step (D9), will be described in further detail below.

The sending notification sub-step (D4) is: when the central processing unit 21 executes the first system image file and then sends a notification signal to the platform path controller 23 and transmits it to the second via the platform path controller 23 The network interface port 29, and then the second network interface port 29 obtains the fixed address of the jig network interface port 31 through search or user designation, and transmits the notification signal to the fixed address according to the fixed address Fixture network interface port 31.

The control shutdown sub-step (D7) is: the logic operation unit 321 controls the first relay module 33 to switch the power supply 1 after 0.3 seconds according to the external address assigned by the jig network interface port 31 To this disabled state.

The control switching sub-step (D8) is: the logic operation unit 321 controls the second relay module 34 according to the external address assigned by the jig network interface port 31, so that the platform path controller 23 is set and selected The second memory 25.

The control boot substep (D9) is: the logic operation unit 321 controls the first relay module 33 to control the power supply 1 after 0.3 seconds according to the external address assigned by the jig network interface port 31 Switch to this enabled state.

It should be further explained that the first and second memories 24 and 25 that store the first system image file and the second system image file respectively also store a first label code and a second label code to Make the central processor 21 of the motherboard 2 execute The system image file can distinguish which system image file is currently executed, to avoid repeated execution and wasting test time.

In the second embodiment of the motherboard testing system of the present invention described above, the central processor of the motherboard executes the test program in the hard disk module according to the batch file built in the system memory, and according to the test After the execution of the first system image file is completed, the program content is then sent a notification signal to the first network interface port via the platform path controller, the first network interface port and the fixed address of the jig network interface port Send the notification signal to the jig network interface port, and then send it to the logic operation unit through the jig network interface port, the logic operation unit executes the batch file stored in the memory according to the notification, and according to The jig network interface port is assigned to the address of the first network interface port through a dynamic host configuration protocol, and then the first power supply module is used to control the power supply to operate in the disabled state without output Operate the power, and then use the second neutral module control setting to make the platform path controller select the second memory, and not select the first memory, and then the logic operation unit is controlled according to the content of the batch file The first relay module controls the power supply to switch to the enabled state through the platform path controller to output electrical energy, so that when the central processor is turned on again, the platform path controller executes the storage in the first The second system image file of the second memory does not require manual operation to control the selection state of the central processor and the first and second memories and the switch of the power supply, which meets the requirement of saving manpower.

In summary, the present invention mainly provides a method to automatically trigger Control the on/off of the power supply and set the platform path controller to automatically switch between one of the first and second memory. Compared with the existing manual operation method, the present invention is based on the storage of the auxiliary unit itself and the motherboard Batch file related to the test program, when the central processor of the motherboard completes the execution of the first system image file according to the test program, it then sends a notification to the auxiliary unit, and the auxiliary unit controls the corresponding to the motherboard according to the notification The on/off of the power supply and the switching of the setting of the image file are controlled by the power-on setting without the need of manual operation and switching, so the purpose of the invention can be achieved.

However, the above are only examples of the present invention, and the scope of implementation of the present invention cannot be limited by this, any simple equivalent changes and modifications made according to the scope of the patent application of the present invention and the content of the patent specification are still classified as Within the scope of the invention patent.

1: Power supply

2: motherboard

21: CPU

22: Hard disk module

23: platform path controller

24: First memory

25: second memory

28: The first network interface port

29: Second network interface port

3: auxiliary unit

31: Fixture network interface port

32: Microcontroller

321: Logic operation unit

322: Memory

33: The first relay module

34: Second relay module

4: Test the server

Claims (10)

A motherboard testing method is performed by a motherboard testing system for receiving operating power provided by a power supply and operating in one of a disabled state and a consistent energy state. The motherboard testing system includes a host Board and an auxiliary unit, the motherboard includes a central processor, a platform path controller electrically connecting the central processor and the power supply, an electrical path connecting the platform path controller and storing a first system image file First memory, and a second memory electrically connected to the platform path controller and storing a second system image file, the auxiliary unit is electrically connected to the platform path controller, and the auxiliary unit includes a jig network Interface port, a microcontroller, a first relay module, and a second relay module, the fixture network interface port is used to receive a notification signal from the central processor, the microcontroller It includes a logic operation unit electrically connected to the jig network interface port to receive the notification signal sent by the central processor, and the first relay module and the second relay module are electrically connected to the logic operation unit and the Platform path controller, the motherboard test method includes: (B3) When the platform path controller selects the first memory according to the setting of the auxiliary unit, the central processor reads and executes through the platform path controller The first system image file; (B7) the auxiliary unit sends a shutdown signal to the power supply via the platform path controller according to a notification signal sent by the central processor, so that the power supply does not provide operating power To the motherboard, so that the motherboard operates in the disabled state; (B8) The auxiliary unit sets the platform path controller to switch to select the second memory, wherein the logic operation unit controls the second relay module to generate a boot setting to the platform path controller to control the platform An image file setting corresponding to the path controller is switched to select the second memory; (B9) the auxiliary unit sends a power-on signal to the power supply via the platform path controller according to the notification signal, and the power supply provides operation Power is supplied to the motherboard to enable the motherboard to operate in the enabled state; and (B10) the central processor reads and executes the second system image file via the platform path controller. According to the motherboard testing method of claim 1, the motherboard testing system further includes a test server electrically connected to the motherboard, and the motherboard further includes an electrical connection between the test server and the platform path controller A first network interface port and a hard disk module electrically connected to the central processor and storing a test program, wherein the motherboard test method further includes a step (A), the test server sends a test The program-related trigger signal is sent to the first network interface port and sent to the central processor via the platform path controller. According to the motherboard testing method of claim 2, the auxiliary unit stores a batch file, wherein the motherboard testing method further includes a step (B4) and a step (B5), the step (B4) is the The central processor sends the notification signal to the auxiliary unit according to the test program, the step (B5) is that the auxiliary unit executes the batch file according to the notification signal, the batch file is related to the execution of the step (B7) to the step (B9). The motherboard testing method as described in claim 3, the motherboard further includes a power A second network interface port connected to the platform path controller to receive the notification signal sent by the central processor via the platform path device, the auxiliary unit is electrically connected to the second network interface port, wherein, in this step ( In B4), the central processor sends the notification signal to the second network interface port through the platform path controller, the batch file also performs a step (B6), and the auxiliary unit passes the second network interface When the port receives the notification signal and executes the batch file, it waits for a preset time before proceeding to this step (B7). A motherboard testing system for receiving operating power provided by a power supply and operating in one of a disabled state and a consistent energy state. The motherboard testing system includes: a motherboard including a central processor , A platform path controller electrically connected to the central processor and the power supply, a first memory electrically connected to the platform path controller and storing a first system image file, and an electrically connected to the platform path controller And stores a second memory of a second system image file; and an auxiliary unit electrically connected to the platform path controller, and the auxiliary unit includes a jig network interface port, a microcontroller, and a first relay Module, and a second relay module, the jig network interface port is used to receive a notification signal sent by the central processor, the microcontroller includes an electrical connection to the jig network interface port to receive The logic operation unit of the notification signal sent by the central processor, the first relay module and the second relay module are electrically connected to the logic operation unit and the platform path controller, and when the auxiliary unit setting indicates the platform When the path controller selects the first memory, the central processor reads and executes via the platform path controller Execute the first system image file, the auxiliary unit sends a shutdown signal to the power supply via the platform path controller according to a notification signal sent by the central processor, the power supply does not provide operating power to the host To enable the motherboard to operate in the disabled state, the auxiliary unit controls the platform path controller to switch the second memory according to the notification signal, wherein the logic operation unit controls the second relay module Generate a boot setting to the platform path controller to switch an image file setting corresponding to the platform path controller to select the second memory, and the auxiliary unit sends a boot signal through the platform path controller according to the notification signal To the power supply, the power supply provides operating power to the motherboard, the motherboard operates in the enabled state, and the central processor reads and executes the second system image file via the platform path controller. The motherboard test system of claim 5, further comprising a test server electrically connected to the motherboard, wherein the motherboard further comprises a first network electrically connected to the test server and the platform path controller Interface port, and a hard disk module electrically connected to the central processor and storing a test program, the test server sends a trigger signal related to the test program to the first network interface port, and passes through the platform path The controller transmits to the central processor. The motherboard test system according to claim 6, wherein the auxiliary unit stores a batch file related to the test program, and after the central processor reads and executes the first system image through the platform path controller, The central processor sends the notification signal to the auxiliary unit according to the test program, the auxiliary unit executes the batch file according to the notification signal, the batch file is related to the auxiliary The auxiliary unit sends the shutdown signal to the platform path controller according to the notification signal, and the platform path controller controls the power supply not to provide operating power to the motherboard, so that the motherboard shuts down and controls the setting of the platform The path controller switches to electrically connect to the second memory, and then sends the power-on signal to the platform path controller, so that the platform path controller controls the power supply to provide operating power to the motherboard to enable the motherboard to perform Turn on. The motherboard test system of claim 7, wherein the auxiliary unit sends the shutdown simulation signal so that the power supply does not provide operating power to the motherboard and waits for a predetermined time. The motherboard test system according to claim 8, wherein the test server assigns an address to the first network interface port through a dynamic host setting protocol, and sends the trigger signal to the first network interface according to the address A network interface port, the first network interface port receives the address and the trigger signal, and the central processor receives the trigger signal through the platform path controller to read and execute the test program. The motherboard test system according to claim 9, further comprising a second network interface port electrically connected to the platform path controller to receive a notification signal sent by the central processor via the platform path controller, wherein the auxiliary The jig network interface port of the unit is electrically connected to the second network interface port and has an address, the microcontroller stores the batch file, and the first relay module is electrically connected to the microcontroller and the platform A path controller, the second relay module is electrically connected to the microcontroller, the central processor transmits the notification signal to the second network interface port via the platform path controller, and the second network interface port is based on The The address sends the notification signal to the jig network interface port, the microcontroller receives the notification signal through the jig network interface port to execute the batch file, and sends it through the first relay module One of the shutdown signal and the startup signal is to the platform path controller to control the power supply, and the setting is controlled by the second relay module.

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