CN118675602B - A memory testing system and a memory testing method - Google Patents
A memory testing system and a memory testing method Download PDFInfo
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- CN118675602B CN118675602B CN202411162174.8A CN202411162174A CN118675602B CN 118675602 B CN118675602 B CN 118675602B CN 202411162174 A CN202411162174 A CN 202411162174A CN 118675602 B CN118675602 B CN 118675602B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5004—Voltage
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- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
The invention provides a test system and a test method of a memory, wherein the test system comprises a processing unit and a monitoring unit, wherein the processing unit is used for configuring different low-power modes and corresponding overtime time thresholds and sending the different low-power modes and the corresponding overtime time thresholds to the memory, the monitoring unit is used for monitoring states of a core power pin and an input/output power pin of the memory, the processing unit is used for setting up a test environment and performing pressure test on the memory under different low-power modes, when the upper power and the lower power of the core power pin and the input/output power pin of the memory are complete, the processing unit is used for reading address data corresponding to main machine data written into the memory before power failure, and the processing unit is also used for comparing the main machine data written into the memory before power failure with the main machine data read after power failure to generate a test result. The system and the method for testing the memory can be used for comprehensively testing the pressure of the firmware of the memory.
Description
Technical Field
The present invention relates to the field of storage, and in particular, to a system and method for testing a memory.
Background
With the mass application of electronic products such as mobile phones and tablets, the low power consumption requirement on a memory is higher and higher. The power off notification (Power Off Notification, PON) is an important function in memory that can significantly reduce the power consumption of the electronic product. The firmware of the memory must be able to properly handle normal PON operation while ensuring that the electronic product is restored to normal condition in various power-off and power-on combinations. Different application scenarios require different processing capabilities of the firmware, so that it is necessary to perform a stress test on the processing capabilities of the firmware.
The existing pressure test of the firmware is mostly based on a white box test in the firmware, and the test method has single condition and insufficient complexity and cannot comprehensively cover various power-off and power-on combined problems in a real use scene of a customer. This test limitation results in insufficient verification of the firmware interior. Therefore, there is a need for improvement.
Disclosure of Invention
The invention aims to provide a test system and a test method of a memory, which are used for carrying out comprehensive pressure test on firmware of the memory.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the invention provides a memory test system, comprising:
the processing unit is used for configuring different low-power consumption modes and corresponding timeout time thresholds and sending the timeout time thresholds to the memory, wherein the timeout time thresholds represent the time length required for completely storing data before the memory is powered off;
A power management unit electrically connected to the processing unit and the memory, the power management unit for controlling the power on/off of the input/output power pins of the memory, and
The monitoring unit is electrically connected with the processing unit and the memory and is used for monitoring the states of a core power supply pin and an input/output power supply pin of the memory;
the processing unit is used for building a test environment and performing pressure test on the memory under different low-power consumption modes;
when the processing unit determines that the upper power and the lower power of the core power supply pin and the input/output power supply pin of the memory are complete, address data corresponding to the main machine data written into the memory before the power failure of the memory are read;
the processing unit is further configured to compare host data written into the memory before power failure with host data read after power failure to generate a test result.
In an embodiment of the present invention, the low power mode includes a short power mode, the timeout period threshold includes a short duration threshold, and the short power mode corresponds to the short duration threshold;
In the short power mode, the processing unit is used for issuing an immediate power-off instruction to the power management unit so as to enable the memory to enter a power-off state;
The processing unit is also used for issuing a time-delay power-off instruction to the power management unit, and enabling the memory to enter a power-off state after the memory sends out a completion signal;
the processing unit is further configured to issue a power-off waiting instruction to the memory, and before the memory issues a completion signal, and after a duration of issuing the power-off waiting instruction reaches a first delay duration, so that the memory enters a power-off state, where the first delay duration is less than a short duration threshold;
after the memory enters a power-down state, the processing unit is further configured to perform different combination tests on power-up and power-down of a core power pin and power-up and power-down of an input/output power pin of the memory, and record a response result of the memory.
In an embodiment of the present invention, the low power mode further includes a long power mode, the timeout period threshold further includes a long duration threshold, and the long power mode corresponds to the long duration threshold;
In the long power mode, the processing unit is used for issuing an immediate power-off instruction to the power management unit so as to enable the memory to enter a power-off state;
The processing unit is also used for issuing a time-delay power-off instruction to the power management unit, and enabling the memory to enter a power-off state after the memory sends out a completion signal;
The processing unit is further configured to issue a power-off waiting instruction to the memory, and before the memory issues a completion signal, and after a duration of issuing the power-off waiting instruction reaches a second delay duration, so that the memory enters a power-off state, where the second delay duration is less than a long duration threshold;
after the memory enters a power-down state, the processing unit is further configured to perform different combination tests on power-up and power-down of a core power pin and power-up and power-down of an input/output power pin of the memory, and record a response result of the memory.
In an embodiment of the present invention, the low power mode further includes a sleep mode, the timeout period threshold further includes a sleep duration threshold, and the sleep mode corresponds to the sleep duration threshold;
In the sleep mode, the processing unit is used for issuing an immediate power-off instruction to the power management unit so as to enable the memory to enter a power-off state;
The processing unit is also used for issuing a time-delay power-off instruction to the power management unit, and enabling the memory to enter a power-off state after the memory sends out a completion signal;
the processing unit is further configured to issue a power-off waiting instruction to the memory, before the memory issues a completion signal, and after a duration of issuing the power-off waiting instruction reaches a third delay duration, so that the memory enters a power-off state, where the third delay duration is less than a sleep duration threshold;
after the memory enters a power-down state, the processing unit is further configured to perform different combination tests on power-up and power-down of a core power pin and power-up and power-down of an input/output power pin of the memory, and record a response result of the memory.
In one embodiment of the present invention, the test of the memory by the processing unit in the short power mode and the long power mode includes at least one combination of powering up the core power pin and powering up the input/output power pin, powering up the core power pin and powering down the input/output power pin, powering down the core power pin and powering up the input/output power pin, powering down the core power pin and powering down the input/output power pin.
In one embodiment of the present invention, the test of the memory by the processing unit in the sleep mode includes at least one combination of powering up the core power pin and powering up the input/output power pin, powering down the core power pin and powering up the input/output power pin.
In an embodiment of the present invention, when the processing unit determines that the power up and power down of the core power pin and the input/output power pin of the memory are incomplete, the pressure test is repeated on the memory until the power up and power down of the core power pin and the input/output power pin of the memory are complete.
In an embodiment of the present invention, the processing unit generates the test result when determining that host data written by the memory before power failure is the same as host data read after power failure;
and when the processing unit determines that the host data written into the memory before power failure is different from the host data read after power failure, generating the test result and optimizing the firmware of the memory.
The invention also provides a method for testing the memory, which comprises the following steps:
Acquiring a memory and building a test environment of the memory;
Different low power consumption modes and corresponding timeout time thresholds are configured and sent to the memory, wherein the timeout time thresholds represent the time required for completely storing data before the memory is powered off;
performing pressure test on the memory under different low power consumption modes;
judging whether the upper power and the lower power of a core power pin and an input/output power pin of the memory are complete;
Repeating the pressure test on the memory when the upper and lower electricity of the core power supply pin and the input/output power supply pin of the memory is incomplete;
When the upper power and the lower power of the core power supply pin and the input/output power supply pin of the memory are complete, comparing the host data written in the memory before power failure with the host data read after power failure to generate a test result.
In an embodiment of the present invention, the low power consumption mode includes a short power supply mode, a long power supply mode, and a sleep mode, the timeout period threshold includes a short duration threshold, a long duration threshold, and a sleep duration threshold, the short power supply mode corresponds to the short duration threshold, the long power supply mode corresponds to the long duration threshold, the sleep mode corresponds to the sleep duration threshold, and the step of performing a pressure test on the memory in different low power consumption modes includes:
In the short power mode, the long power mode and the sleep mode, the processing unit is used for issuing an immediate power-off instruction to the power management unit so as to enable the memory to enter a power-off state;
The processing unit is used for issuing a delayed power-off instruction to the power management unit in the short power mode, the long power mode and the sleep mode, and enabling the memory to enter a power-off state after the memory sends out a completion signal;
The processing unit is configured to issue a power-off waiting instruction to the memory in the short power mode, the long power mode and the sleep mode, and before the memory issues a completion signal and after a duration issued by the power-off waiting instruction reaches a preset delay duration, to enable the memory to enter a power-off state, where the preset delay duration includes a first delay duration corresponding to the short power mode, a second delay duration corresponding to the long power mode and a third delay duration corresponding to the sleep mode, the first delay duration is less than a short duration threshold, the second delay duration is less than a long duration threshold, and the third delay duration is less than a sleep duration threshold;
after the memory enters a power-down state, the processing unit is further configured to perform different combination tests on power-up and power-down of a core power pin and power-up and power-down of an input/output power pin of the memory, and record a response result of the memory.
As described above, the present invention provides a system and a method for testing a memory, which can test response time and processing capacity of the memory in various PON modes by performing detailed tests in different modes, including situations of a PON busy for a short time, a busy for a long time, and a busy sleep, and different scenarios of powering off immediately after command execution, powering off after waiting for completion of the memory, powering off during operation of the memory, etc., and can discover potential risks and defects of firmware in PON mode in time. Through detailed test and verification, the firmware can be ensured to run stably under different power modes and operation conditions, and the risk of data loss or equipment damage is reduced.
Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a memory testing system according to an embodiment of the invention;
FIG. 2 is a flow chart of a method for testing a memory according to an embodiment of the invention;
FIG. 3 is a flowchart of step S30 in FIG. 2;
fig. 4 is a flowchart of step S31 in fig. 3;
FIG. 5 is a flowchart of step S32 in FIG. 3;
FIG. 6 is a flowchart of step S33 in FIG. 3;
fig. 7 is a flowchart of step S60 in fig. 2.
In the figure, 100 parts of processing unit, 200 parts of power management unit, 300 parts of monitoring unit, 400 parts of storage unit, 500 parts of power unit, 600 parts of peripheral interface unit, 700 parts of memory unit, 800 parts of first serial interface unit, 900 parts of memory, 1000 parts of second serial interface unit.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, the present invention provides a testing system for a memory, which can perform a stress test on firmware of the memory 900. The test system may include a processing unit (CPU) 100, a Power management unit (Power MANAGEMENT INTEGRATED Circuit, PMIC) 200, a monitoring unit (VM) 300, a storage unit (SD) 400, a Power unit (Power) 500, a peripheral interface Unit (USB) 600, a memory unit (DRAM) 700, and a first serial interface Unit (UART) 800. The processing unit 100, the power management unit 200, the monitoring unit 300, the storage unit 400, the power unit 500, the peripheral interface unit 600, the memory unit 700, and the first serial interface unit 800 may be mounted on the same test board.
In one embodiment, the processing unit 100 may be responsible for executing instructions in a computer program and controlling the other hardware devices to work in concert. Processing unit 100 may retrieve instructions from storage unit 400, decode the instructions, and execute the instructions to perform their primary functions.
In one embodiment, the power management unit 200 may be electrically connected to the processing unit 100, the memory 900, respectively. The power management unit 200 may be used to manage and control power distribution in the device. The power management unit 200 can sequentially turn on or off the core power (Voltage Common Collector, VCC) pin and the input/output power (Voltage Common Collector for I/O, VCCQ) pin of the memory 900 according to a specific timing requirement, so as to ensure that the memory 900 is normally turned on and off.
The VCC pin may provide power to, among other things, the core circuitry (e.g., memory cells, control logic, etc.) of the memory 900. The VCCQ pins may provide power to the I/O circuitry of memory 900, including providing the necessary operating voltages for input/output buffers, data bus drivers, and other peripheral circuitry to ensure efficient data communication with processing unit 100.
In one embodiment, the monitoring unit 300 may be electrically connected to the processing unit 100, the memory 900, respectively. The monitoring unit 300 can monitor the voltages of the VCC pin and the VCCQ pin in real time, and control the power-on and power-off sequences of the power supply, so as to ensure that the system components start and stop in the correct sequence, and avoid faults caused by timing errors.
In one embodiment, the memory unit 400 may be electrically connected with the processing unit 100. The storage unit 400 may be a storage device in which an operating system (or a boot program) is preset, and is capable of loading and starting the operating system or the boot program.
In one embodiment, the power supply unit 500 may supply power to the processing unit 100, the power management unit 200, and the like.
In one embodiment, the peripheral interface unit 600 may be electrically connected with the processing unit 100. The peripheral interface unit 600 is a standardized interface for connecting various peripheral devices (e.g., keyboard, mouse, printer, storage device, etc.) to a computer or host device.
In one embodiment, memory unit 700 may be electrically coupled to processing unit 100. Memory unit 700 may be used to temporarily store programs and data currently being run. The processing unit 100 may quickly access these data to improve computing performance.
In one embodiment, the first serial interface unit 800 may be electrically connected with the processing unit 100. The first serial interface unit 800 may be an interface for serial communication. The processing unit 100 may perform serial communication with an external device through the first serial interface unit 800.
In one embodiment, the memory 900 may also have a second serial interface unit 1000 disposed thereon. The second serial interface unit 1000 may be an interface for performing serial communication. Memory 900 and processing unit 100 may communicate with DATA 0-7 lines via the CMD line. Wherein the CMD line may be used to transmit commands and responses, which are unidirectional, the processing unit 100 may send commands, and the memory 900 may receive commands. The DATA 0-7 lines may be used for DATA transmission.
In one embodiment, processing unit 100 may first build a test environment for memory 900 when performing a stress test on the firmware of memory 900.
Specifically, memory 900 may be communicatively coupled to a test board. Thereafter, the power supply unit 500 may supply power to the test board, causing the processing unit 100 and other units thereon to start operating. The test board can then be communicatively coupled to a host computer via the peripheral interface unit 600, which can select a particular firmware or operating system Image (SOC Image) and burn it onto the test board's memory unit 400 via the peripheral interface unit 600. After the burning is finished, the test board is electrified again, and the mirror image of the new burning is started. The host computer can check whether the connection with the test board is normal through the peripheral interface unit 600, and confirm whether the test board is properly started and responded. The test board may generate Random test files (Random TEST PATTERN) according to the configuration, which may be used for stress testing of the memory 900 to build a test environment for the memory 900.
In one embodiment, processing unit 100 may also configure different low power modes and corresponding timeout time thresholds and send to memory 900. The low power consumption mode may include a short power mode, a long power mode, and a sleep mode. The timeout threshold includes a short duration threshold, a long duration threshold, and a sleep duration threshold. The short power mode may correspond to a short duration threshold. The long power mode may correspond to a long duration threshold. The sleep mode may correspond to a sleep duration threshold.
Specifically, PON is a Power management mechanism involving notification and handling at Power On (Power On) and Power Off (Power Off) of a device. Different power states (e.g., short power up, long power up, sleep state) require different treatments. When the firmware of the memory 900 is pressure tested, the processing unit 100 may be configured with different low power modes.
Further, the short power mode may be represented as a case where the memory 900 has a power interruption in a short time. The long power mode may be represented as a case where the memory 900 has a power interruption for a long time. Sleep mode may be indicated as memory 900 entering sleep mode.
Still further, the memory 900 may need to wait a period of time before powering down to complete certain operations or to save data. Therefore, in different low power modes, different timeout thresholds need to be preset to enable the memory 900 to completely save data.
Still further, in the short power mode, when the operation time of the memory 900 is less than the short length threshold, the test is passed, otherwise, the test of the memory 900 fails. In the long power mode, when the operation time of the memory 900 is less than the long duration threshold, the test is passed, otherwise, the test of the memory 900 fails. In sleep mode, when the operation time of the memory 900 is less than the sleep duration threshold, the test is passed, otherwise, the test of the memory 900 fails. The short-time length threshold may be in a range of 200ms to 400ms, for example, 200ms, 300ms, 400ms, or the like, without limitation. The size of the long duration threshold may be in the range of 900ms to 1100ms, for example 900ms, 1000ms, 1100ms, or the like, without limitation. The size of the sleep duration threshold may not be limited, and may be in a range of 600ms to 700ms, for example, 600ms, 655.36ms, 700ms, and the like.
In one embodiment, after processing unit 100 builds a test environment, the firmware of memory 900 may be stress tested in a short power mode, a long power mode, and a sleep mode, respectively. Wherein the test sequence of the different low power modes may not be limited. For example, the test may be performed in the order of the short power mode, the long power mode, and the sleep mode, or may be performed in the order of the long power mode, the short power mode, and the sleep mode. The specific test sequence can be set according to the actual requirement, and in this embodiment, the test sequence of the short power mode, the long power mode and the sleep mode is taken as an example for illustration.
In one embodiment, in the short power mode, processing unit 100 may issue an immediate power down instruction to power management unit 200 to bring memory 900 into a power down state. After the memory 900 enters the power-down state, the processing unit 100 is further configured to perform different combinations of testing on powering up and powering down of the core power pins and powering up and powering down of the input/output power pins of the memory 900, and record the response result of the memory 900.
After the processing unit 100 issues the immediate power-off instruction to the power management unit 200, the power management unit 200 may immediately cut off the power supply to the memory 900, so that the memory 900 enters the power-down state. By setting such a policy, the response of the memory 900 without preparation time can be tested.
Further, in the short power mode, the processing unit 100 may also issue a delayed power-off instruction to the memory 900, and after the memory 900 issues a completion signal, the memory 900 enters a power-down state.
After the processing unit 100 issues a delayed power-off instruction to the power management unit 200, it needs to wait for the memory 900 to complete a current busy state (busy), which may be indicated as that the memory 900 is processing some critical operations, such as data writing or state saving. After the memory 900 completes the current operation, at this point, the power management unit 200 may cut off the power supply to the memory 900 to put the memory 900 into a power-down state. By setting such a policy, it is possible to test the response of the memory 900 to be powered down again after the current operation is completed.
Still further, in the short power mode, the processing unit 100 may also issue a power-down wait instruction to the memory 900 after a first delay period before the memory 900 issues a completion signal to put the memory 900 into a power-down state. The first delay period is less than a short duration threshold.
After the processing unit 100 issues the power-off waiting instruction to the power management unit 200, the power-off can be performed during the working process of the memory 900 without waiting for the memory 900 to complete the current busy state. That is, in the process of completing the current operation of the memory 900, after the duration of the power-off wait instruction reaches the first delay duration, at this time, the power management unit 200 may cut off the power supply to the memory 900, so that the memory 900 enters the power-off state. By setting such a policy, the response of the memory 900 when the current operation is not completed can be tested.
In one embodiment, in the short power mode, after the memory 900 enters a power down state, different combinations of powering up and powering down the core power (VCC) pins and powering up and powering down the input/output power (VCCQ) pins of the memory 900 are required to fully complete the pressure test of the firmware. The combination may include at least one of power-up of the VCC pin and power-up of the VCCQ pin, power-up of the VCC pin and power-down of the VCCQ pin, power-down of the VCC pin and power-up of the VCCQ pin, and power-down of the VCC pin and power-down of the VCCQ pin.
Specifically, when the power up and down of the VCC pin and the power up and down of the VCCQ pin are monitored, it is indicated that the device has completed normal and complete power up only when the voltages of the VCC pin and the VCCQ pin must be above their minimum operating voltages. The monitoring unit 300 may determine whether it is powered up by monitoring the voltage levels of the VCC pin and the VCCQ pin.
In one embodiment, in a long power mode, processing unit 100 may issue an immediate power down instruction to power management unit 200 to bring memory 900 into a power down state. After the memory 900 enters the power-down state, the processing unit 100 is further configured to perform different combinations of testing on powering up and powering down of the core power pins and powering up and powering down of the input/output power pins of the memory 900, and record the response result of the memory 900.
After the processing unit 100 issues the immediate power-off instruction to the power management unit 200, the power management unit 200 may immediately cut off the power supply to the memory 900, so that the memory 900 enters the power-down state. By setting such a policy, the response of the memory 900 without preparation time can be tested.
Further, in the long power mode, the processing unit 100 may also issue a delayed power-off instruction to the memory 900, and after the memory 900 issues a completion signal, the memory 900 enters a power-down state.
After the processing unit 100 issues a delayed power-off instruction to the power management unit 200, it needs to wait for the memory 900 to complete a current busy state (busy), which may be indicated as that the memory 900 is processing some critical operations, such as data writing or state saving. After the memory 900 completes the current operation, at this point, the power management unit 200 may cut off the power supply to the memory 900 to put the memory 900 into a power-down state. By setting such a policy, it is possible to test the response of the memory 900 to be powered down again after the current operation is completed.
Still further, in the long power mode, the processing unit 100 may also issue a power-down wait instruction to the memory 900, after a second delay period before the memory 900 issues the completion signal, to put the memory 900 into a power-down state. The second delay period is less than the long period threshold.
After the processing unit 100 issues the power-off waiting instruction to the power management unit 200, the power-off can be performed during the working process of the memory 900 without waiting for the memory 900 to complete the current busy state. That is, in the process of completing the current operation of the memory 900, after the duration of the power-off wait instruction reaches the second delay duration, at this time, the power management unit 200 may cut off the power supply to the memory 900, so that the memory 900 enters the power-off state. By setting such a policy, the response of the memory 900 when the current operation is not completed can be tested.
In one embodiment, in the long power mode, after the memory 900 enters a power down state, different combinations of powering up and powering down the core power (VCC) pins and powering up and powering down the input/output power (VCCQ) pins of the memory 900 are required to fully complete the pressure test of the firmware. The combination may include at least one of power-up of the VCC pin and power-up of the VCCQ pin, power-up of the VCC pin and power-down of the VCCQ pin, power-down of the VCC pin and power-up of the VCCQ pin, and power-down of the VCC pin and power-down of the VCCQ pin.
In one embodiment, in sleep mode, processing unit 100 may issue an immediate power down instruction to power management unit 200 to cause memory 900 to enter a power down state. After the memory 900 enters the power-down state, the processing unit 100 is further configured to perform different combinations of testing on powering up and powering down of the core power pins and powering up of the input/output power pins of the memory 900, and record the response result of the memory 900.
After the processing unit 100 issues the immediate power-off instruction to the power management unit 200, the power management unit 200 may immediately cut off the power supply to the memory 900, so that the memory 900 enters the power-down state. By setting such a policy, the response of the memory 900 without preparation time can be tested.
Further, in the sleep mode, the processing unit 100 may also issue a delayed power-off instruction to the memory 900, and after the memory 900 issues a completion signal, the memory 900 enters a power-off state.
After the processing unit 100 issues a delayed power-off instruction to the power management unit 200, it is necessary to wait for the memory 900 to complete the current busy state (busy). A busy state may be indicated as memory 900 is handling certain critical operations, such as data writing or state saving. After the memory 900 completes the current operation, at this point, the power management unit 200 may cut off the power supply to the memory 900 to put the memory 900 into a power-down state. By setting such a policy, it is possible to test the response of the memory 900 to be powered down again after the current operation is completed.
Still further, in the sleep mode, the processing unit 100 may further issue a power-down wait instruction to the memory 900, after a second delay period before the memory 900 issues the completion signal, to put the memory 900 into the power-down state. The third delay period is less than the sleep period threshold.
After the processing unit 100 issues the power-off waiting instruction to the power management unit 200, the power-off can be performed during the working process of the memory 900 without waiting for the memory 900 to complete the current busy state. That is, in the process of completing the current operation of the memory 900, after the duration of the power-off wait instruction reaches the third delay duration, at this time, the power management unit 200 may cut off the power supply to the memory 900, so that the memory 900 enters the power-off state. By setting such a policy, the response of the memory 900 when the current operation is not completed can be tested.
In one embodiment, in sleep mode, after memory 900 enters a power down state, different combinations of powering up and powering down core power (VCC) pins and powering up input/output power (VCCQ) pins of memory 900 are required to fully complete the pressure test of the firmware. The combination may include at least one of power-up of the VCC pins and power-up of the VCCQ pins, power-down of the VCC pins and power-up of the VCCQ pins.
In one embodiment, after the monitoring unit 300 monitors the power up and power down of the VCC pin and the VCCQ pin in different low power modes, the processing unit 100 needs to determine, by the monitoring unit 300, whether the power up and power down of the VCC pin and the VCCQ pin of the memory 900 is complete in different low power modes.
Specifically, in a certain low power mode, when the power up and power down of the VCC pin and the VCCQ pin are incomplete, the processing unit 100 may repeatedly perform the stress test on the memory 900 until the power up and power down of the VCC pin and the VCCQ pin are complete in all modes. When the power up and power down of the VCC pin and the VCCQ pin are complete, the processing unit 100 may read address data corresponding to the host data written before the power down of the memory, and obtain the corresponding host data according to the address data.
In one embodiment, after processing unit 100 reads the host data, the host data written by memory 900 before the power failure may be compared with the host data read after the power failure to generate a test result.
Specifically, when the host data written into the memory 900 before the power failure is the same as the host data read after the power failure, it may be indicated that the memory 900 passes the test and a test result is generated. When the host data written into the memory 900 before power failure is different from the host data read after power failure, it may be indicated that the memory 900 fails the test, and a certain defect exists. At this time, the firmware of the memory 900 may be optimized to some extent according to the location of the defect. Meanwhile, the test result can be uploaded to the host.
It can be seen that, in the above scheme, by performing detailed tests in different modes, including situations of short busy, long busy and busy sleeping of the PON, and different scenarios of power-off immediately after command execution, power-off after waiting for completion of the memory, power-off in memory operation, etc., the response time and processing capability of the memory in various PON modes can be tested, and potential risks and defects of the firmware in PON mode can be found in time. Through detailed test and verification, the firmware can be ensured to run stably under different power modes and operation conditions, and the risk of data loss or equipment damage is reduced.
Referring to fig. 2, the present invention further provides a testing method of a memory, which can be applied to the testing system to perform a pressure test on firmware of the memory 900. The steps of the test method are in one-to-one correspondence with the test systems. The test method may include the steps of:
S10, acquiring a memory, and building a test environment of the memory;
step S20, configuring different low-power consumption modes and corresponding timeout time thresholds, and sending the different low-power consumption modes and the timeout time thresholds to a memory, wherein the low-power consumption modes comprise a short power supply mode, a long power supply mode and a sleep mode, and the timeout time thresholds comprise a short time length threshold, a long time length threshold and a sleep time length threshold;
Step S30, performing pressure test on the memory under different low-power consumption modes;
step S40, judging whether the upper power supply pin and the lower power supply pin of the core power supply pin of the memory are complete;
Step S50, when the upper and lower electricity of the core power supply pin and the input/output power supply pin of the memory is incomplete, repeating the pressure test on the memory;
And step S60, when the upper power supply pin and the lower power supply pin of the memory are complete, comparing the host data written in the memory before power failure with the host data read after power failure to generate a test result.
Referring to fig. 3, in one embodiment, when step S30 is performed, the step S30 may include the following steps:
step S31, in a short power mode, performing pressure test on the memory;
step S32, in a long power supply mode, performing pressure test on the memory;
step S33, in the sleep mode, the pressure test is performed on the memory.
In one embodiment, different preset delay durations may be set in different modes. The preset delay period may include a first delay period corresponding to the short power mode, a second delay period corresponding to the long power mode, and a third delay period corresponding to the sleep mode.
Referring to fig. 4, in one embodiment, when step S31 is performed, step S31 may include the following steps:
Step S311, under the short power mode, the processor issues an immediate power-off instruction to enable the memory to enter a power-off state, and tests different combinations of power-on and power-off of a core power pin of the memory and power-on and power-off of an input/output power pin of the memory are performed, and response results of the memory are recorded;
step S312, in the short power mode, the processor issues a time-delay power-off instruction, and after the memory sends out a completion signal, the memory enters a power-off state, and tests of different combinations of power-on and power-off of a core power pin of the memory and power-on and power-off of an input/output power pin of the memory are performed, and a response result of the memory is recorded;
Step S313, in the short power mode, the processor issues a power-off waiting instruction, after a first preset time period before the memory sends out a completion signal, the memory is enabled to enter a power-down state, different combinations of test on power-on and power-off of a core power pin of the memory and power-on and power-off of an input/output power pin are carried out, and a response result of the memory is recorded, wherein the first delay time period is smaller than a short time length threshold value.
Referring to fig. 5, in one embodiment, when step S32 is performed, step S32 may include the following steps:
Step S321, under the long power mode, the processor issues an immediate power-off instruction to enable the memory to enter a power-off state, tests on different combinations of power-on and power-off of a core power pin of the memory and power-on and power-off of an input/output power pin of the memory are performed, and response results of the memory are recorded;
Step S322, in the long power mode, the processor issues a time-delay power-off instruction, after the memory sends out a completion signal, the memory enters a power-off state, and tests of different combinations of power-on and power-off of a core power pin of the memory and power-on and power-off of an input/output power pin of the memory are performed, and a response result of the memory is recorded;
Step S323, in the long power mode, the processor issues a power-off waiting instruction, before the memory sends out a completion signal, after a second delay time, the memory is enabled to enter a power-down state, and tests of different combinations are carried out on the power-on and power-off of a core power pin of the memory and the power-on and power-off of an input/output power pin of the memory, and a response result of the memory is recorded, wherein the second delay time is smaller than a long time threshold.
Referring to fig. 6, in one embodiment, when step S33 is performed, specifically, step S33 may include the following steps:
step S331, in the sleep mode, the processor issues an immediate power-off instruction to enable the memory to enter a power-off state, tests different combinations of power-on and power-off of a core power pin and power-on of an input/output power pin of the memory are performed, and response results of the memory are recorded;
Step S332, in the sleep mode, the processor issues a time-delay power-off instruction, and after the memory sends out a completion signal, the memory enters a power-off state, and tests on different combinations of power-on and power-off of a core power pin and power-on of an input/output power pin of the memory are performed, and the response result of the memory is recorded;
Step S333, in the sleep mode, the processor issues a power-off waiting instruction, and after a third delay time period, the memory enters a power-down state before the memory sends out a completion signal, and tests on different combinations of power-on and power-off of a core power pin and power-on of an input/output power pin of the memory are performed, and a response result of the memory is recorded, wherein the third delay time period is smaller than a sleep time period threshold value.
Referring to fig. 7, in one embodiment, when step S60 is performed, specifically, step S60 may include the following steps:
step S61, judging whether the host data written in the memory before power failure is the same as the host data read after power failure;
step S62, if the test results are the same, a test result is generated;
And step S63, if the test results are different, generating test results, and optimizing the firmware of the memory.
The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (10)
1. A memory testing system, comprising:
the processing unit is used for configuring different low-power consumption modes and corresponding timeout time thresholds and sending the timeout time thresholds to the memory, wherein the timeout time thresholds represent the time length required for completely storing data before the memory is powered off;
A power management unit electrically connected to the processing unit and the memory, the power management unit for controlling the power on/off of the input/output power pins of the memory, and
The monitoring unit is electrically connected with the processing unit and the memory and is used for monitoring the states of a core power supply pin and an input/output power supply pin of the memory;
the processing unit is used for building a test environment and performing pressure test on the memory under different low-power consumption modes;
when the processing unit determines that the upper power and the lower power of the core power supply pin and the input/output power supply pin of the memory are complete, address data corresponding to the main machine data written into the memory before the power failure of the memory are read;
the processing unit is further configured to compare host data written into the memory before power failure with host data read after power failure to generate a test result.
2. The memory test system of claim 1, wherein the low power mode comprises a short power mode, the timeout period threshold comprises a short duration threshold, the short power mode corresponds to the short duration threshold;
In the short power mode, the processing unit is used for issuing an immediate power-off instruction to the power management unit so as to enable the memory to enter a power-off state;
The processing unit is also used for issuing a time-delay power-off instruction to the power management unit, and enabling the memory to enter a power-off state after the memory sends out a completion signal;
the processing unit is further configured to issue a power-off waiting instruction to the memory, and before the memory issues a completion signal, and after a duration of issuing the power-off waiting instruction reaches a first delay duration, so that the memory enters a power-off state, where the first delay duration is less than a short duration threshold;
after the memory enters a power-down state, the processing unit is further configured to perform different combination tests on power-up and power-down of a core power pin and power-up and power-down of an input/output power pin of the memory, and record a response result of the memory.
3. The memory test system of claim 2, wherein the low power mode further comprises a long power mode, the timeout period threshold further comprises a long duration threshold, the long power mode corresponding to the long duration threshold;
In the long power mode, the processing unit is used for issuing an immediate power-off instruction to the power management unit so as to enable the memory to enter a power-off state;
The processing unit is also used for issuing a time-delay power-off instruction to the power management unit, and enabling the memory to enter a power-off state after the memory sends out a completion signal;
The processing unit is further configured to issue a power-off waiting instruction to the memory, and before the memory issues a completion signal, and after a duration of issuing the power-off waiting instruction reaches a second delay duration, so that the memory enters a power-off state, where the second delay duration is less than a long duration threshold;
after the memory enters a power-down state, the processing unit is further configured to perform different combination tests on power-up and power-down of a core power pin and power-up and power-down of an input/output power pin of the memory, and record a response result of the memory.
4. The memory testing system of claim 3, wherein the low power mode further comprises a sleep mode, the timeout period threshold further comprises a sleep period threshold, the sleep mode corresponding to the sleep period threshold;
In the sleep mode, the processing unit is used for issuing an immediate power-off instruction to the power management unit so as to enable the memory to enter a power-off state;
The processing unit is also used for issuing a time-delay power-off instruction to the power management unit, and enabling the memory to enter a power-off state after the memory sends out a completion signal;
the processing unit is further configured to issue a power-off waiting instruction to the memory, before the memory issues a completion signal, and after a duration of issuing the power-off waiting instruction reaches a third delay duration, so that the memory enters a power-off state, where the third delay duration is less than a sleep duration threshold;
after the memory enters a power-down state, the processing unit is further configured to perform different combination tests on power-up and power-down of a core power pin and power-up and power-down of an input/output power pin of the memory, and record a response result of the memory.
5. The memory test system of claim 3, wherein in the short power mode and the long power mode, the processing unit tests the memory including at least one of core power pin power up and input/output power pin power up, core power pin power down and input/output power pin power down.
6. The memory test system of claim 4, wherein in the sleep mode, the processing unit testing the memory includes at least one of core power pin power up and input/output power pin power up, core power pin power down and input/output power pin power up.
7. The system of claim 1, wherein the processing unit repeatedly performs the pressure test on the memory until the core power pin and the input/output power pin of the memory are powered up and down completely when it is determined that the core power pin and the input/output power pin of the memory are powered up and down incompletely.
8. The system for testing a memory according to claim 1, wherein the processing unit generates the test result when it is determined that host data written by the memory before power failure is identical to host data read after power failure;
and when the processing unit determines that the host data written into the memory before power failure is different from the host data read after power failure, generating the test result and optimizing the firmware of the memory.
9. A method for testing a memory, comprising:
Acquiring a memory and building a test environment of the memory;
Different low power consumption modes and corresponding timeout time thresholds are configured and sent to the memory, wherein the timeout time thresholds represent the time required for completely storing data before the memory is powered off;
performing pressure test on the memory under different low power consumption modes;
judging whether the upper power and the lower power of a core power pin and an input/output power pin of the memory are complete;
Repeating the pressure test on the memory when the upper and lower electricity of the core power supply pin and the input/output power supply pin of the memory is incomplete;
When the upper power and the lower power of the core power supply pin and the input/output power supply pin of the memory are complete, comparing the host data written in the memory before power failure with the host data read after power failure to generate a test result.
10. The method for testing a memory according to claim 9, wherein the low power consumption mode includes a short power supply mode, a long power supply mode, and a sleep mode, the timeout period threshold includes a short duration threshold, a long duration threshold, and a sleep duration threshold, the short power supply mode corresponds to the short duration threshold, the long power supply mode corresponds to the long duration threshold, and the sleep mode corresponds to the sleep duration threshold, and the step of performing the pressure test on the memory in different low power consumption modes includes:
In the short power mode, the long power mode and the sleep mode, the processing unit is used for issuing an immediate power-off instruction to the power management unit so as to enable the memory to enter a power-off state;
The processing unit is used for issuing a delayed power-off instruction to the power management unit in the short power mode, the long power mode and the sleep mode, and enabling the memory to enter a power-off state after the memory sends out a completion signal;
The processing unit is configured to issue a power-off waiting instruction to the memory in the short power mode, the long power mode and the sleep mode, and before the memory issues a completion signal and after a duration issued by the power-off waiting instruction reaches a preset delay duration, to enable the memory to enter a power-off state, where the preset delay duration includes a first delay duration corresponding to the short power mode, a second delay duration corresponding to the long power mode and a third delay duration corresponding to the sleep mode, the first delay duration is less than a short duration threshold, the second delay duration is less than a long duration threshold, and the third delay duration is less than a sleep duration threshold;
after the memory enters a power-down state, the processing unit is further configured to perform different combination tests on power-up and power-down of a core power pin and power-up and power-down of an input/output power pin of the memory, and record a response result of the memory.
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| CN117219148A (en) * | 2023-09-13 | 2023-12-12 | 苏州忆联信息系统有限公司 | Solid state disk power consumption state transition test method, device, equipment and storage medium |
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