CN113470730B - Method and device for improving storage performance of Nor Flash memory - Google Patents
Method and device for improving storage performance of Nor Flash memory Download PDFInfo
- Publication number
- CN113470730B CN113470730B CN202110738997.0A CN202110738997A CN113470730B CN 113470730 B CN113470730 B CN 113470730B CN 202110738997 A CN202110738997 A CN 202110738997A CN 113470730 B CN113470730 B CN 113470730B
- Authority
- CN
- China
- Prior art keywords
- repair
- voltage
- area
- threshold voltage
- preset
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
- G11C29/4401—Indication or identification of errors, e.g. for repair for self repair
Landscapes
- Read Only Memory (AREA)
Abstract
The invention relates to the technical field of memories and discloses a method and a device for improving the storage performance of a Nor Flash memory, wherein the method comprises the steps of detecting the current on a read bit line for a storage array region after receiving a power-on operation command and converting the current into voltage delta Vt, alternately carrying out threshold voltage repair operation and repair verification operation on a region with the highest repair level, waiting for the next power-on operation command to be sent and repeatedly executing until all region repair operations are completed, and directly recognizing that the region where the erase operation is executed when the power-off or illegal reset operation occurs is the region with the highest repair level; the invention performs the repairing action by combining the power-on operation matching, does not increase excessive useless time in the power-on process, balances the relation between the repairing time and the total power-on duration, effectively achieves the aim of improving the threshold voltage of a problem unit, effectively prevents the problem of electric leakage of a storage unit, ensures the stability and reliability of storage, saves a large amount of time and power consumption, and has practical value in practical sense.
Description
Technical Field
The invention relates to the field of memory technology, in particular to a method and a device for improving storage performance of a Nor Flash memory.
Background
As shown in FIG. 1, for Nor Flash chips, the erase process is a process of lowering the threshold voltage of the memory cell, treating the data in the erased memory cell as "1", while the write programming process is a process of raising the threshold voltage of the memory cell, programmingThe data in the memory cell after success is considered to be "0". The threshold voltage DeltaVt corresponding to a cell storing a data of "0" is seen 0 Is higher than the threshold voltage DeltaVt corresponding to a cell storing data of "1 1 。
When the erasing operation is executed, for the memory cell, negative high voltage is applied to the control grid electrode of the memory cell connected with the memory cell through a Word line, positive high voltage is applied to the P-type substrate, electrons in the floating gate layer can penetrate into the substrate through the tunnel oxide layer under the action of an internal electric field, and finally the threshold voltage of the memory cell is greatly reduced. Assume for example that the threshold voltage DeltaVt of the cell that is not erased 0 After the memory cell is erased by the erase process, the corresponding threshold voltage is assumed to be Δvt 1 The erasure from "0" to "1" can be achieved by =2v.
However, in actual operation, the threshold voltage value of the cell with the stored data of 1 is lower than the safe voltage due to the reasons of process defect, repair operation uncomfortableness and the like, namely, the abnormal leakage problem is caused in the cell, in addition, the threshold voltage of the cell which is excessively erased due to the illegal operations such as abnormal power-off and power-off of a memory chip, forced reset and the like is also abnormally reduced in the process of erasing, so that the large-area leakage is caused, the phenomenon of misreading and misreading is increased due to the occurrence of the problems, the storage stability and the reliability of the memory are seriously influenced, and the problem is urgently needed to be solved.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides the method and the device for improving the storage performance of the Nor Flash memory, which can rapidly detect the problem storage unit, effectively improve the threshold voltage of the problem storage unit and achieve the effect of improving the overall storage data stability of the memory and simultaneously considering the comprehensive performance of the memory.
The invention solves the technical problems by adopting the following technical scheme:
the invention provides a method for improving storage performance of a Nor Flash memory, which comprises the following steps:
after the Nor Flash memory receives a power-on operation command, detecting and reading current on a bit line in a subarea manner of the memory array and converting the current into voltage delta Vt;
recording the area address with the voltage delta Vt lower than the verification voltage in the storage array, and carrying out repair grade identification on the area address according to the reverse order of the voltage delta Vt;
performing power-on operation of the Nor Flash memory, and synchronously alternately performing threshold voltage repair operation and repair verification operation on the area with the highest repair level, wherein the threshold voltage repair operation is sequentially performed until the repair verification is passed according to the preset number of times of repetition and the increment of the word line pressurization value by delta V;
repeating the steps when the next power-on operation command is sent;
if the Nor Flash memory is subjected to power-off or illegal reset operation when the Nor Flash memory is subjected to erase operation, the address of the target area of the erase operation is recorded, and when a next power-on operation command is sent, the area is directly determined to be the highest repair grade and the subsequent repair step is executed.
Preferably, the detecting the current on the read bit line and converting to the voltage Δvt for the memory array in the divided regions specifically includes:
dividing the storage array into areas;
sequentially performing the following steps on the divided areas:
setting all word line voltages in the area part as preset detection voltages;
the current on the selected bit line is sequentially read and converted to the threshold voltage DeltaVt corresponding to the memory cell on the bit line.
Preferably, the area division of the storage array is specifically performed according to the internal physical wiring of the storage array;
the following operations are also performed on the divided regions:
comparing the current on the bit line selected by reading with a preset reference current in sequence;
if the difference value of the two is not more than the preset value, the rest bit lines in the area are continuously detected,
otherwise, judging the area as an abnormal area, and executing detailed detection on the area according to pages, wherein the detection is carried out on the inside of the pages in a unit of one byte, and locating to obtain a specific address corresponding to a memory cell with abnormally low threshold voltage.
Preferably, the threshold voltage repair operation includes selecting to perform one of sequential repair, local repair or accurate repair according to the number and distribution of memory cells with abnormally low threshold voltages, and specifically includes:
if a memory cell to be repaired exists on each bit line in the area to be repaired, pressurizing all word lines in the area to be repaired to a preset repair voltage, and sequentially completing the repair operation of bit line gating on all pages by taking bytes as a unit based on address self-increasing;
if the number of the memory cells with abnormally low threshold voltages in the area to be repaired exceeds a preset value, pressurizing word lines of the page where the abnormal memory cells are located to a preset repair voltage, and executing local repair according to the page, wherein the local repair comprises bit line gating of the page by taking bytes as units;
otherwise, the single word line in the area to be repaired is pressurized to a preset repair voltage, and the specific address gating corresponding bit line corresponding to the memory cell with the abnormally low threshold voltage is obtained according to positioning, so that accurate repair is performed.
Preferably, the directly recognizing the region as the highest repair level and performing the threshold voltage repair operation in the subsequent step repair operation as sequential repair.
Preferably, the values of the preset detection voltage and the verification voltage are configured according to the memory cells which enable the threshold voltage to be reduced below the safety voltage to be detected and judged as the memory cells with abnormally low threshold voltage;
and configuring the value of the preset repair voltage according to the threshold voltage of the memory cell which is enabled to reach the threshold voltage for normally storing 1 data after the repair verification is passed.
The invention also provides a device for improving the storage performance of the Nor Flash memory, which comprises a detection module, an address cache module, a repair data storage module, a counter module and a repair control module, wherein,
the detection module is configured to detect and read the current on the bit line for each storage array region after the Nor Flash memory receives the power-on operation command, convert the current into voltage delta Vt, send the address of the abnormal region with the voltage delta Vt lower than the verification voltage in the storage array into the address cache module for storage, and carry out repair grade identification on the abnormal region according to the reverse order of the voltage delta Vt;
the address cache module is configured to store addresses of various abnormal areas in the storage array and clear address data after the power-on operation is completed;
the repair data storage module is configured to dynamically store the area address which is operated at the highest repair level or in the power-off or illegal reset operation in real time, a preset number of times, a single pressurization increment to delta V and a preset repair voltage;
a counter module configured to count in real time the number of threshold voltage repair operations and repair verification operations;
the repair control module is configured to read the storage data in the repair data storage module, and synchronously and alternately perform threshold voltage repair operation and repair verification operation on the area with the highest repair level when the Nor Flash memory performs power-on operation, wherein the threshold voltage repair operation is sequentially performed until the repair verification passes after the preset times are repeated each time according to the alternation times and the word line pressurization value is increased by delta V.
Preferably, the detection module is further configured to set all bit line voltages in each region in the memory array to a preset detection voltage, sequentially read the current on the selected bit line and convert the current into a threshold voltage Δvt corresponding to the memory cell on the bit line;
and comparing the internally set reference current with the current on the selected bit, if the difference value of the reference current and the current does not exceed a preset value, continuing to detect the rest bit lines in the area, otherwise judging the area as an abnormal area, and performing detailed detection on the area according to pages, wherein the detection is performed on the page interior in a unit of one byte, and the specific address corresponding to the memory cell with the abnormally low threshold voltage is obtained through positioning.
Preferably, the repair control module is further configured to selectively perform one of sequential repair, local repair or precise repair according to the number and distribution of memory cells with abnormally low threshold voltages, and specifically includes:
if a memory cell to be repaired exists on each bit line in the area to be repaired, pressurizing all word lines in the area to be repaired to a preset repair voltage, and sequentially completing the repair operation of bit line gating on all pages by taking bytes as a unit based on address self-increasing;
if the number of the memory cells with abnormally low threshold voltages in the area to be repaired exceeds a preset value, pressurizing word lines of the page where the abnormal memory cells are located to a preset repair voltage, and executing local repair according to the page, wherein the local repair comprises bit line gating of the page by taking bytes as units;
otherwise, pressurizing the single word line of the area to be repaired to a preset repair voltage, and accurately repairing the corresponding bit line according to the specific address strobe corresponding to the memory cell with the abnormally low threshold voltage obtained by positioning;
the repair verification operation specifically comprises the steps of controlling the detection module to repeatedly execute the detection action of the threshold voltage of each storage unit, comparing the detected threshold voltage with the value of the safety voltage, and judging whether the repair verification is passed or not.
The invention also provides a NOR Flash memory, which comprises the device for improving the storage performance of the Nor Flash memory.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a method for improving the storage performance of a Nor Flash memory, which not only repairs and improves the problem that the delta Vt1 value of a unit with the storage data of 1 caused by normal erasure operation is too low, but also repairs and improves the threshold voltage delta Vt1 value of a unit with the over erasure caused by illegal operations such as abnormal power failure, forced reset and the like of a memory chip in the erasure process (applying positive high voltage to WL), thereby effectively preventing and solving the problem of large-area electric leakage caused by over erasure, greatly reducing the possibility of misread and misread, simultaneously creatively matching the repair process and the power-on operation process, leading the unit with the storage data of 1 in part of array areas to carry out the repair operation of 1, not only improving the threshold voltage of the unit with the storage data of 1, but also avoiding the problem of greatly increasing the power consumption of the chip caused by blind repair without causing excessive power-on time, and achieving the effect of improving the comprehensive performance of the chip while improving the whole storage data stability of the chip;
the device for improving the storage performance of the Nor Flash memory is designed in the chip at the cost of slightly increasing the area of the memory chip, so that the phenomenon that the threshold voltage delta Vt1 of a cell with stored data of 1 is too low due to normal erasing operation is repaired in the power-on process of the Nor Flash memory, and the problem that the threshold voltage is too low due to illegal operations such as abnormal power-off and power-down of the memory chip, forced resetting and the like in the erasing process is solved, thereby improving the stability and reliability of the stored data of the Nor Flash memory and prolonging the service life of the Nor Flash memory.
Other prominent substantial features and significant advances of the invention relative to the prior art are described in further detail in the examples section.
Drawings
Other features, objects and advantages of the present invention will become more apparent upon reading of the detailed description of non-limiting embodiments, given with reference to the accompanying drawings in which:
FIG. 1 is a diagram illustrating the change in Nor Flash erase and program threshold voltages;
FIG. 2 is a schematic diagram of a Nor Flash memory cell structure;
FIG. 3 is a schematic diagram of a Nor Flash memory array;
FIG. 4 is a flow chart of a method for improving the storage performance of the Nor Flash memory in embodiment 1;
FIG. 5 is a schematic diagram of a device for improving storage performance of a Nor Flash memory in embodiment 2;
fig. 6 is a schematic diagram of a structure of a lifting Nor Flash memory in embodiment 3.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that certain names are used throughout the specification and claims to refer to particular components. It should be appreciated that one of ordinary skill in the art may refer to the same component by different names. The description and claims do not identify differences in names as a way of distinguishing components, but rather are identified as a way of distinguishing components. As used in the specification and claims of this application, the terms "comprising" or "including" are to be construed as "including but not limited to" or "including but not limited to". The embodiments described in the detailed description are preferred embodiments of the invention and are not intended to limit the scope of the invention.
Example 1
Before describing the embodiment, the problems of the existing memory array, such as abnormal leakage, abnormal data reading, etc., need to be further described in detail, and referring to fig. 2, a main NOR flash memory cell structure mainly includes a control gate (control gate), a floating gate (floating gate), a source (source), and a drain (drain). And whether the data stored therein is a "0" or a "1" depends on whether there are electrons in the floating gate. For example, after erasing data from a Flash memory array, electrons can escape from the floating gate, and if the floating gate is successfully erased, a large number of electrons can be lost, so that the memory cell is successfully erased.
Fig. 3 is a schematic diagram of a main flow nors Flash chip Flash array structure, which mainly includes Word Lines (WL) connected to control gates in a lateral direction, bit lines (Bit lines, BL) connected to drain terminals of memory cells in a longitudinal direction, and ground lines and P-type substrates connected to source terminals.
Each column of vertical memory cells in the array is connected to the same BL, assuming that the memory on a BL is simply due to the erase operation resulting in a threshold voltage that is too low ΔVt 1 When the abnormal leakage occurs in the memory cell of the adjacent area (the adjacent area is the sector if the sector erase is performed, and the adjacent area is the block if the block erase is performed), the problem of misreading and misreading is likely to occur.
Assuming that, when the memory cells connected to WL512 and BL1 in fig. 3 perform the sector erase operation, the chip fails to perform the repair operation after the erase due to abnormal power failure or illegal reset, and finally an over-erase phenomenon occurs, the sector area and the area nearby the sector area will be likely to have an abnormal leakage phenomenon, which finally results in the problems of bad data stability, such as misreading and misreading, when the data of the cells in the sector adjacent to the leakage cell on BL1 is read.
The reason for this problem is that when the memory array is erased, the lateral WL is turned on to the same negative high voltage, the chip will apply a positive voltage to the P-substrate in the erase region, the negative voltage acts on the control gate connected to WL, electrons in the floating gate of the memory cell will escape from the floating gate, and finally the threshold voltage of the erased memory cell is reduced to realize the erase function. On the one hand, during normal operation, due to the characteristic that the cells in one array share the WELL, when the erase process is performed, since the whole WELL is applied with positive high voltage, the adjacent area (such as adjacent sector and block area) with the erase area is affected by a certain degree even if the erase operation is not performed, so that the delta Vt of the cell pair with the data stored in the adjacent area as 0 is achieved 0 The value is reduced, and the over-erase phenomenon may occur when the cells perform the erase operation in the future, but the over-erase problem is more likely to occur in the current operation cell than in the surrounding memory cells, i.e., the repair of "1" has a higher priority than the repair of "0".
In the abnormal erasing operation, on the other hand, during the period from the process of erasing (applying negative high voltage WELL to WL), the chip is abnormally powered off and powered down or is subjected to illegal reset, so that the subsequent electric leakage repairing work cannot be completed, and the phenomenon of over-erasing of part of memory cells may be caused. Over-erase problems are more likely to occur in the current operation unit than in the surrounding memory units, i.e., repair "1" has a higher priority than repair "0".
In view of this, referring to fig. 4, the present embodiment provides a method for improving storage performance of a Nor Flash memory, which includes:
after the Nor Flash memory receives a power-on operation command, detecting and reading current on a bit line in a subarea manner of the memory array and converting the current into voltage delta Vt; the method comprises the steps of dividing a storage array into areas, specifically dividing the storage array according to physical wiring in the storage array, and setting all word line voltages in the area as preset detection voltages;
sequentially reading the current on the selected bit line and converting the current to the threshold voltage DeltaVt corresponding to the memory cell on the bit line
Recording the area address with the voltage delta Vt lower than the verification voltage in the storage array, and carrying out repair grade identification on the area address according to the reverse order of the voltage delta Vt, namely comparing the current on the bit line selected by reading with the preset reference current in sequence;
if the difference value of the two is not more than the preset value, the rest bit lines in the area are continuously detected,
otherwise, judging the area as an abnormal area, and performing detailed detection on the area according to pages, wherein the detection is performed on the inside of the pages in sequence by taking one byte as a unit, and positioning to obtain a specific address corresponding to a storage unit with abnormally low threshold voltage;
the lower the DeltaVt, the higher the area repair level;
further illustrated is:
let us assume that fig. 3 is an inter-connection relationship of a region a, for example, BL0 to BLn in fig. 3 connect 8 pages in total, i.e., 8 pages are arranged in a row in the lateral direction. The voltage of all WL in the area is uniformly set as a voltage, the voltage is generally set within 0-1V, the voltage is typically set at 0.5V, the substrate of the area is connected with 0, then each BL in the area A is detected and compared one by utilizing the characteristic that BL in the memory array is longitudinally and through connected with all memory cells, a bit line is connected with a comparison module, the voltage is set within 0.5-1V, whether the detected current on the BL is excessively large compared with the current on the selected BL is judged, the phenomenon that whether large-area electric leakage exists in the area can be judged, the current on the BL is converted into the threshold voltage corresponding to the memory cell on the BL through the comparison module, and whether the memory cell connected with the BL needs to be repaired by 1 is judged. If the difference value is small, which indicates no leakage phenomenon, that is, the memory cell has no abnormality, the rest BL in the memory array area A is sequentially detected, if the abnormality exists, the area is supposed to be detected in detail by taking page as a unit, and the inside of the page is detected by taking one byte (byte) as a unit, so that the leakage range in the area A can be obtained by detecting the page where the abnormality BL is located, and the specific address corresponding to the memory cell with excessively low threshold voltage is finally obtained;
through the steps, the memory cells with the leakage problem caused by over-erasure in the memory array can be detected and found, and the memory cells with the threshold voltages reduced below the safety range caused by the escape of electrons from the floating gate, the technological defects, the magnetic field, the temperature and the humidity and the like can be found out by comparing the threshold voltages.
Further illustrative is provided that there are N blocks in a memory cell, each 16 blocks being partitioned into one region. When the chip executes the erasing operation, the detection module starts to detect the memory array, and after detection, the threshold voltage of the unit with the data of 1 stored in the block area of the area A (0-15) is delta Vta, and the lowest value of the threshold voltage is 0.3v. The threshold voltage of the cell storing data "1" in the block area of the area B (16-31) is Δvtb, and its minimum value is 1.6v. The threshold voltage of the cell storing data "1" in the block area of the area C (32-47) is Δvtc, and its minimum value is 2.0v. The threshold voltage of the cell storing data "1" in the block area of the area D (48-63) is Δvtd, and its minimum value is 2.0v. And so on, finally marking the block area [ N (-15) -N ] as a Z area through the detection, and obtaining the threshold voltage delta Vtz of the Z area and the lowest value thereof;
the threshold voltage of the area A in the areas is the lowest, so that the possibility of abnormal power failure and leakage of the area is larger than that of other areas, the area needs to be repaired by '1' preferentially, the address range corresponding to the storage area is recorded, namely the physical area mapped in the chip can be known, the area is repaired for the current power-on operation, after the repair of the area A is finished, the area which is needed to repair '1' most in all areas is preferentially selected and repaired according to the latest threshold voltage detected next time when the next time of software hardware reset or re-power-on of the memory is carried out.
Performing power-on operation of the Nor Flash memory, and synchronously alternately performing threshold voltage repair operation and repair verification operation on the area with the highest repair level, wherein the threshold voltage repair operation is sequentially performed until the repair verification is passed according to the preset number of times of repetition and the increment of the word line pressurization value by delta V;
the threshold voltage repair operation includes selecting to perform one of sequential repair, local repair or accurate repair according to the number and distribution of memory cells with abnormally low threshold voltages, and specifically includes:
if a memory cell to be repaired exists on each bit line in the area to be repaired, pressurizing all word lines in the area to be repaired to a preset repair voltage, and sequentially completing the repair operation of bit line gating on all pages by taking bytes as a unit based on address self-increasing;
if the number of the memory cells with abnormally low threshold voltages in the area to be repaired exceeds a preset value, pressurizing word lines of the page where the abnormal memory cells are located to a preset repair voltage, and executing local repair according to the page, wherein the local repair comprises bit line gating of the page by taking bytes as units;
otherwise, the single word line in the area to be repaired is pressurized to a preset repair voltage, and the specific address gating corresponding bit line corresponding to the memory cell with the abnormally low threshold voltage is obtained according to positioning, so that accurate repair is performed.
Further illustrated is:
based on the above examples, during the power-on operation, all the problem units in the area a are selected for repair according to the address data given by the positioning.
When the repair operation is performed, since the address corresponding to the specific area of the repair operation is known, WL corresponding to the area to be repaired is turned on to a preset voltage, for example, 0.1V, the substrate voltage is still set to 0, and then BL in the page corresponding to the address is gated, and at this time, the BL access voltage value is typically 3V, so that the repair of the cell storing the data "1" with the threshold voltage of negative value can be performed.
If the unit to be repaired exists on each BL in the whole area, the characteristic that all storage units in the array are conducted by the longitudinal BL can be utilized, and when repairing '1', the whole area can be repaired once by selecting all BL, so that the purpose of repairing '1' is achieved.
Assuming that the connection relationship in the area a is shown in fig. 3, for example, BL0 to BLn in fig. 3 assume that 8 pages are connected together, that is, 8 pages are arranged in a row in the lateral direction, and a large number of memory cells with negative threshold voltages occur in the area a due to over-erase, the area a needs to be repaired by "1". All WL in the repair area A are connected to a preset repair voltage, for example, the preset repair voltage is 0.1V, but can be selected according to the situation within 0.1-1V, which is not repeated herein, and then repair work of the whole area A can be completed only by repairing addresses corresponding to 8 pages by utilizing the characteristic that BL is longitudinally penetrated.
For the above page, each page includes 256 bytes (byte), the repair "1" process repairs each page in units of bytes (byte), each byte (byte) includes 8 bits of data corresponding to 8 storage units (the data in the storage units is random, may be all "0", may be all "1", or may be "0" and "1"), and if 1 bit (bit) data in 1 byte (byte) needs to be repaired (i.e. 1 unit with 1 stored data is "1" needs to be repaired, "1" operation), the BL corresponding to the byte (byte) where the leakage unit is selected to repair operation, so that the 1 problem unit can be repaired. And the like, when the 256 th byte (byte) is repaired, all the leakage units in the current page are repaired. And then repairing the next page, and finally repairing 8 transverse pages by the same method, namely finishing the electric leakage repairing work of the whole area A. The whole repairing process only needs to perform one-time pressurizing operation on all WL in the area A, and compared with the traditional scheme, the repairing process omits a large amount of operation time for boosting and reducing the voltage of the WL selected.
Therefore, the design scheme saves a large amount of repair time, does not increase excessive useless time in the power-on process, balances the relation between the repair time and the total power-on duration, finally achieves the purpose of improving the threshold voltage of a problem unit, effectively prevents the problem of leakage of the storage unit, and ensures the stability of data in the storage. Compared with the traditional repair scheme for the memory, the method saves a great deal of time and power consumption.
After the primary repair process is finished, threshold voltage judgment is carried out again on the repaired area A, if abnormal electricity leakage still exists after detection, namely that primary threshold voltage repair fails, threshold voltage repair is carried out again, a repair result is judged, and the repair times are counted. Assuming that after the repair times reach the designed maximum repair times 16 times, the failure of repairing the threshold voltage of the area can still be detected, when abnormal electric leakage exists, the voltage of the corresponding WL (WL) is linearly increased in each 16 times as a unit in the chip, for example, the voltage of the WL is increased by 0.1V, so that the capacity of repairing the threshold voltage is enhanced, and finally, the purpose of successful repair is achieved. After the power-on is finished, the chip enters a normal standby state, and a user can perform normal operation, so that the whole repair process can be seen without adding any additional operation. The method and the device achieve the effect of achieving the purpose of restoration and considering the actual operation experience of the user group.
Repeating the steps when the next power-on operation command is sent;
along with the continuous power-on of the memory, the repairing step is also repeated, after repeated power-on repairing, the memory array units possibly having abnormal electric leakage in the whole Flash memory can be effectively repaired, and the threshold voltage of the units with the whole memory data of 1 can enter a safety range. And further, the integrity and stability of the whole stored data of the memory are improved, the probability of misreading and misreading is effectively reduced, the performance of the memory chip is enhanced, and the service life of the chip is prolonged.
If the Nor Flash memory is subjected to power-off or illegal reset operation when the Nor Flash memory executes the erase operation, the address of the target area of the erase operation is recorded, the area is directly determined to be the highest repair grade when the next power-on operation command is sent, and the subsequent repair steps are executed, wherein the repair operation of the threshold voltage repair operation in the subsequent steps is sequential repair.
Further illustrated is:
it is assumed that during the process of erasing the memory array area a (applying a negative high voltage to WL) in the memory, abnormal power-off and illegal reset operations occur, which results in that the memory cannot complete the repairing procedure step of the leakage after the original erasing is completed. At this time, when the chip detects abnormal power-down or reset, the counting module records the address corresponding to the stored array area A of the erasing operation, and when the memory performs the next power-up operation, the memory array area corresponding to the address is directly subjected to the power-up repair operation. The scheme solves the problems of over-erasure, abnormal electric leakage and the like caused by similar illegal power-off and reset operations.
In this embodiment, the values of the preset detection voltage and the verification voltage are configured according to the memory cells for which the threshold voltage is reduced below the safety voltage are detected and judged as the memory cells with abnormally low threshold voltage;
and configuring the value of the preset repair voltage according to the threshold voltage of the memory cell which is enabled to reach the threshold voltage for normally storing 1 data after the repair verification is passed.
Example 2
Referring to fig. 5 and 6, a device for improving storage performance of a Nor Flash memory according to the present embodiment includes a detection module, an address buffer module, a repair data storage module, a counter module and a repair control module, wherein,
the detection module is configured to detect and read the current on the bit line for each storage array region after the Nor Flash memory receives the power-on operation command, convert the current into voltage delta Vt, send the address of the abnormal region with the voltage delta Vt lower than the verification voltage in the storage array into the address cache module for storage, and carry out repair grade identification on the abnormal region according to the reverse order of the voltage delta Vt;
the address cache module is configured to store addresses of various abnormal areas in the storage array and clear address data after the power-on operation is completed;
the repair data storage module is configured to dynamically store the area address which is operated at the highest repair level or in the power-off or illegal reset operation, a preset number of times, a single pressurization increment delta V and a preset repair voltage in real time;
a counter module configured to count in real time the number of threshold voltage repair operations and repair verification operations;
the repair control module is configured to read the storage data in the repair data storage module, and synchronously and alternately perform threshold voltage repair operation and repair verification operation on the area with the highest repair level when the Nor Flash memory performs power-on operation, wherein the threshold voltage repair operation is sequentially performed until the repair verification passes after the preset times are repeated each time according to the alternation times and the word line pressurization value is increased by delta V.
The detection module in this embodiment is further configured to set all bit line voltages in each region in the memory array to a preset detection voltage, sequentially read the current on the selected bit line and convert the current to a threshold voltage Δvt corresponding to the memory cell on the bit line;
and comparing the internally set reference current with the current on the selected bit, if the difference value of the reference current and the current does not exceed a preset value, continuing to detect the rest bit lines in the area, otherwise judging the area as an abnormal area, and performing detailed detection on the area according to pages, wherein the detection is performed on the page interior in a unit of one byte, and the specific address corresponding to the memory cell with the abnormally low threshold voltage is obtained through positioning.
The repair control module in this embodiment is further configured to selectively perform one of sequential repair, local repair or precise repair according to the number and distribution of memory cells with abnormally low threshold voltages, and specifically includes:
if a memory cell to be repaired exists on each bit line in the area to be repaired, pressurizing all word lines in the area to be repaired to a preset repair voltage, and sequentially completing the repair operation of bit line gating on all pages by taking bytes as a unit based on address self-increasing;
if the number of the memory cells with abnormally low threshold voltages in the area to be repaired exceeds a preset value, pressurizing word lines of the page where the abnormal memory cells are located to a preset repair voltage, and executing local repair according to the page, wherein the local repair comprises bit line gating of the page by taking bytes as units;
otherwise, pressurizing the single word line of the area to be repaired to a preset repair voltage, and accurately repairing the corresponding bit line according to the specific address strobe corresponding to the memory cell with the abnormally low threshold voltage obtained by positioning;
the repair verification operation specifically comprises the steps of controlling the detection module to repeatedly execute the detection action of the threshold voltage of each storage unit, comparing the detected threshold voltage with the value of the safety voltage, and judging whether the repair verification is passed or not.
Example 3
Referring to fig. 6, the present embodiment provides a NOR Flash memory, which includes a device for improving storage performance of the NOR Flash memory as described in embodiment 2.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art.
Claims (8)
1. The method for improving the storage performance of the Nor Flash memory is characterized by comprising the following steps:
after the Nor Flash memory receives a power-on operation command, detecting and reading current on a bit line in a subarea manner of the memory array and converting the current into voltage delta Vt;
recording the area address with the voltage delta Vt lower than the verification voltage in the storage array, and carrying out repair grade identification on the area address according to the reverse order of the voltage delta Vt;
performing power-on operation of the Nor Flash memory, and synchronously alternately performing threshold voltage repair operation and repair verification operation on the area with the highest repair level, wherein the threshold voltage repair operation is sequentially performed until the repair verification is passed according to the preset number of times of repetition and the increment of the word line pressurization value by delta V;
repeating the steps when the next power-on operation command is sent;
if the Nor Flash memory is subjected to power-off or illegal reset operation when the Nor Flash memory is subjected to erase operation, recording the address of the target area of the erase operation at the moment, directly recognizing the area as the highest repair grade when a next power-on operation command is sent, and executing a subsequent repair step;
the threshold voltage repair operation includes selectively performing one of sequential repair, local repair or precise repair according to the number and distribution of memory cells with abnormally low threshold voltages, and specifically includes:
if a memory cell to be repaired exists on each bit line in the area to be repaired, pressurizing all word lines in the area to be repaired to a preset repair voltage, and sequentially completing the repair operation of bit line gating on all pages by taking bytes as a unit based on address self-increasing;
if the number of the memory cells with abnormally low threshold voltages in the area to be repaired exceeds a preset value, pressurizing word lines of the page where the abnormal memory cells are located to a preset repair voltage, and executing local repair according to the page, wherein the local repair comprises bit line gating of the page by taking bytes as units;
otherwise, the single word line in the area to be repaired is pressurized to a preset repair voltage, and the specific address gating corresponding bit line corresponding to the memory cell with the abnormally low threshold voltage is obtained according to positioning, so that accurate repair is performed.
2. The method for improving storage performance of the Nor Flash memory according to claim 1, wherein the detecting the current on the read bit line and converting to the voltage Δvt for the storage array in the divided regions specifically comprises:
dividing the storage array into areas;
sequentially performing the following steps on the divided areas:
setting all word line voltages in the area part as preset detection voltages;
the current on the selected bit line is sequentially read and converted to the threshold voltage DeltaVt corresponding to the memory cell on the bit line.
3. The method for improving storage performance of the Nor Flash memory according to claim 2, wherein the dividing the storage array is performed in regions specifically according to physical wiring inside the storage array;
the following operations are also performed on the divided regions:
comparing the current on the bit line selected by reading with a preset reference current in sequence;
if the difference value of the two is not more than the preset value, the rest bit lines in the area are continuously detected,
otherwise, judging the area as an abnormal area, and executing detailed detection on the area according to pages, wherein the detection is carried out on the inside of the pages in a unit of one byte, and locating to obtain a specific address corresponding to a memory cell with abnormally low threshold voltage.
4. The method of claim 1, wherein the directly recognizing the region as the highest repair level and performing the threshold voltage repair operation in the subsequent step is sequential repair.
5. The method for improving storage performance of the Nor Flash memory according to claim 2, wherein the values of the preset detection voltage and the verification voltage are configured according to the memory cells for which the threshold voltage is reduced below the safety voltage, and the memory cells are detected and judged to be abnormally low in the threshold voltage;
and configuring the value of the preset repair voltage according to the threshold voltage of the memory cell which is enabled to reach the threshold voltage for normally storing 1 data after the repair verification is passed.
6. The device for improving the storage performance of the Nor Flash memory is characterized by comprising a detection module, an address cache module, a repair data storage module, a counter module and a repair control module, wherein,
the detection module is configured to detect and read the current on the bit line for each storage array region after the Nor Flash memory receives the power-on operation command, convert the current into voltage delta Vt, send the address of the abnormal region with the voltage delta Vt lower than the verification voltage in the storage array into the address cache module for storage, and carry out repair grade identification on the abnormal region according to the reverse order of the voltage delta Vt;
the address cache module is configured to store addresses of various abnormal areas in the storage array and clear address data after the power-on operation is completed;
the repair data storage module is configured to dynamically store the area address which is operated at the highest repair level or in the power-off or illegal reset operation, a preset number of times, a single pressurization increment delta V and a preset repair voltage in real time;
a counter module configured to count in real time the number of threshold voltage repair operations and repair verification operations;
the repair control module is configured to read the storage data in the repair data storage module, and synchronously and alternately perform threshold voltage repair operation and repair verification operation on the area with the highest repair level when the Nor Flash memory performs power-on operation, wherein the threshold voltage repair operation is sequentially performed until repair verification passes after the preset times are repeated each time according to the alternation times and the word line pressurization value is increased by delta V;
the repair control module is further configured to selectively perform one of sequential repair, local repair or precise repair according to the number and distribution of memory cells with abnormally low threshold voltages, and specifically includes:
if a memory cell to be repaired exists on each bit line in the area to be repaired, pressurizing all word lines in the area to be repaired to a preset repair voltage, and sequentially completing the repair operation of bit line gating on all pages by taking bytes as a unit based on address self-increasing;
if the number of the memory cells with abnormally low threshold voltages in the area to be repaired exceeds a preset value, pressurizing word lines of the page where the abnormal memory cells are located to a preset repair voltage, and executing local repair according to the page, wherein the local repair comprises bit line gating of the page by taking bytes as units;
otherwise, pressurizing the single word line of the area to be repaired to a preset repair voltage, and accurately repairing the corresponding bit line according to the specific address strobe corresponding to the memory cell with the abnormally low threshold voltage obtained by positioning;
the repair verification operation specifically comprises the steps of controlling the detection module to repeatedly execute the detection action of the threshold voltage of each storage unit, comparing the detected threshold voltage with the value of the safety voltage, and judging whether the repair verification is passed or not.
7. The device for improving storage performance of the Nor Flash memory according to claim 6, wherein the detection module is further configured to set all bit line voltages in each region in the memory array to a preset detection voltage, sequentially read a current on a selected bit line and convert the current to a threshold voltage Δvt corresponding to a memory cell on the bit line;
and comparing the internally set reference current with the current on the selected bit, if the difference value of the reference current and the current does not exceed a preset value, continuing to detect the rest bit lines in the area, otherwise judging the area as an abnormal area, and performing detailed detection on the area according to pages, wherein the detection is performed on the page interior in a unit of one byte, and the specific address corresponding to the memory cell with the abnormally low threshold voltage is obtained through positioning.
8. A NOR Flash memory comprising the device for improving storage performance of the NOR Flash memory as claimed in any one of claims 6-7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110738997.0A CN113470730B (en) | 2021-06-30 | 2021-06-30 | Method and device for improving storage performance of Nor Flash memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110738997.0A CN113470730B (en) | 2021-06-30 | 2021-06-30 | Method and device for improving storage performance of Nor Flash memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113470730A CN113470730A (en) | 2021-10-01 |
| CN113470730B true CN113470730B (en) | 2024-03-08 |
Family
ID=77876632
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110738997.0A Active CN113470730B (en) | 2021-06-30 | 2021-06-30 | Method and device for improving storage performance of Nor Flash memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113470730B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114968120B (en) * | 2022-06-01 | 2023-06-06 | 上海佳勒电子有限公司 | Data processing method and system for improving FLASH storage times of single-chip microcomputer |
| CN118675602B (en) * | 2024-08-23 | 2024-11-29 | 合肥康芯威存储技术有限公司 | A memory testing system and a memory testing method |
| CN119274640A (en) * | 2024-12-06 | 2025-01-07 | 南京优存科技有限公司 | Non-volatile memory and leakage detection and repair method and system thereof |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5822252A (en) * | 1996-03-29 | 1998-10-13 | Aplus Integrated Circuits, Inc. | Flash memory wordline decoder with overerase repair |
| KR19990042720A (en) * | 1997-11-27 | 1999-06-15 | 윤종용 | Over erase repair method of semiconductor memory device |
| US6462990B1 (en) * | 2000-12-29 | 2002-10-08 | Intel Corporation | Post erase repair to enhance performance in a flash memory |
| CN101430935A (en) * | 2007-11-08 | 2009-05-13 | 中芯国际集成电路制造(上海)有限公司 | Detection method for over-erasing memory unit in flash memory |
| CN104751885A (en) * | 2013-12-30 | 2015-07-01 | 北京兆易创新科技股份有限公司 | FLASH chip and erasure or programming method for responding to FLASH chip abnormal power-down |
| CN105283919A (en) * | 2014-03-31 | 2016-01-27 | 瑞萨电子株式会社 | Semiconductor device, pre-write program, and restoration program |
| CN109872756A (en) * | 2017-12-01 | 2019-06-11 | 北京兆易创新科技股份有限公司 | A kind of memory method for deleting and device |
| CN111192616A (en) * | 2020-04-14 | 2020-05-22 | 深圳市芯天下技术有限公司 | NOR FLASH chip and method for eliminating over-erasure in erasing process thereof |
| CN112908404A (en) * | 2021-01-22 | 2021-06-04 | 珠海创飞芯科技有限公司 | Nor flash over-erase repairing method and Nor flash memory array |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7289363B2 (en) * | 2005-05-19 | 2007-10-30 | Micron Technology, Inc. | Memory cell repair using fuse programming method in a flash memory device |
| US8462554B2 (en) * | 2011-03-03 | 2013-06-11 | Winbond Electronics Corp. | Over-erase verification and repair methods for flash memory |
-
2021
- 2021-06-30 CN CN202110738997.0A patent/CN113470730B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5822252A (en) * | 1996-03-29 | 1998-10-13 | Aplus Integrated Circuits, Inc. | Flash memory wordline decoder with overerase repair |
| KR19990042720A (en) * | 1997-11-27 | 1999-06-15 | 윤종용 | Over erase repair method of semiconductor memory device |
| US6462990B1 (en) * | 2000-12-29 | 2002-10-08 | Intel Corporation | Post erase repair to enhance performance in a flash memory |
| CN101430935A (en) * | 2007-11-08 | 2009-05-13 | 中芯国际集成电路制造(上海)有限公司 | Detection method for over-erasing memory unit in flash memory |
| CN104751885A (en) * | 2013-12-30 | 2015-07-01 | 北京兆易创新科技股份有限公司 | FLASH chip and erasure or programming method for responding to FLASH chip abnormal power-down |
| CN105283919A (en) * | 2014-03-31 | 2016-01-27 | 瑞萨电子株式会社 | Semiconductor device, pre-write program, and restoration program |
| CN109872756A (en) * | 2017-12-01 | 2019-06-11 | 北京兆易创新科技股份有限公司 | A kind of memory method for deleting and device |
| CN111192616A (en) * | 2020-04-14 | 2020-05-22 | 深圳市芯天下技术有限公司 | NOR FLASH chip and method for eliminating over-erasure in erasing process thereof |
| CN112908404A (en) * | 2021-01-22 | 2021-06-04 | 珠海创飞芯科技有限公司 | Nor flash over-erase repairing method and Nor flash memory array |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113470730A (en) | 2021-10-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN113470730B (en) | Method and device for improving storage performance of Nor Flash memory | |
| JP3189740B2 (en) | Data repair method for nonvolatile semiconductor memory | |
| US8223555B2 (en) | Multiple level program verify in a memory device | |
| US6643181B2 (en) | Method for erasing a memory cell | |
| US6553510B1 (en) | Memory device including redundancy routine for correcting random errors | |
| US8046646B2 (en) | Defective memory block identification in a memory device | |
| US8213233B2 (en) | Reduction of quick charge loss effect in a memory device | |
| US20030206435A1 (en) | Nonvolatile semiconductor storage device and data erasing method | |
| US20070183223A1 (en) | Memory block erasing in a flash memory device | |
| US5590075A (en) | Method for testing an electrically erasable and programmable memory device | |
| US6563752B2 (en) | Qualification test method and circuit for a non-volatile memory | |
| EP1206775B1 (en) | Flash memory device with externally triggered detection and repair of leaky cells | |
| CN102568594A (en) | Over-erasing processing method and system for nonvolatile memory | |
| US11373715B1 (en) | Post over-erase correction method with auto-adjusting verification and leakage degree detection | |
| CN111261213B (en) | Erasing method of NOR Flash | |
| US9378829B2 (en) | Non-volatile memory device with an EPLI comparator | |
| JP2002109892A (en) | Nonvolatile semiconductor storage device | |
| JP2006031926A (en) | Selective erase method for flash memory | |
| US7295471B2 (en) | Memory device having a virtual ground array and methods using program algorithm to improve read margin loss | |
| CN101174472A (en) | Screening method of defective memory cell | |
| CN115295056A (en) | Method and storage device for over-erase repair | |
| CN114005479A (en) | Method and device for improving NOR Flash data read-write reliability and application thereof | |
| US7233530B2 (en) | System and method for over erase reduction of nitride read only memory | |
| JPH05314783A (en) | Erasure method for nonvolatile semiconductor memory provided with erasure function and writing device | |
| US20140119129A1 (en) | Low margin read operation with crc comparision |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |