TWI685284B - Package structure and manufacturing method thereof - Google Patents

Abstract

A package structure includes a redistribution structure, a chip, one or more structural strengthening elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed on the redistribution structure and electrically connected to the second circuit layer. The one or more structural strengthening elements are disposed on the redistribution structure. The structural strengthening elements have a Young's modulus of 30 to 200GPa. The protective layer covers the chip and the sidewalls of the structural strengthening elements.

Description

Packaging structure and its manufacturing method

This disclosure relates to a packaging structure and a method of manufacturing a packaging structure.

Traditionally, the chip packaging structure includes a substrate, a wafer on the substrate, and a package material layer covering the wafer. Due to the large differences in the thermal expansion coefficients of the substrate, the wafer, and the packaging material layer, when the thermal process is performed to form the wafer and the packaging material layer on the substrate, the chip packaging structure is often severely warped. Therefore, the yield of the chip package structure mounted on the printed circuit board is reduced.

On the other hand, when a package-on-package (POP) with a package structure formed on another package structure is to be formed, the warpage phenomenon also causes difficulties in the manufacturing process.

The first embodiment of the present disclosure provides a packaging structure including a circuit redistribution structure, a chip, one or more structural strengthening elements, and a protective layer. The circuit redistribution structure includes a first circuit layer and a second circuit layer disposed on the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. Chip design It is placed on the circuit redistribution structure and electrically connected to the second circuit layer. One or more structural strengthening elements are arranged on the circuit redistribution structure. The structural strengthening element has a Young's modulus of 30~200GPa. The protective layer covers the side walls of the wafer and the structural strengthening element.

In the first embodiment of the present disclosure, the package structure includes a structure strengthening element, and the structure strengthening element surrounds the chip.

In the first embodiment of the present disclosure, the package structure includes a plurality of structural strengthening elements, and one of the plurality of structural strengthening elements is located on the first side of the chip, and the other of the plurality of structural strengthening elements is located on the chip The second side, and the second side is opposite or adjacent to the first side.

In the first embodiment of the present disclosure, the structural strengthening element and the wafer have a horizontal distance of 50 to 1000 microns.

In the first embodiment of the present disclosure, the structural strengthening element includes but is not limited to bismaleimide triazine resin, epoxy resin, solder paste or copper paste.

In the first embodiment of the present disclosure, the upper surface of the structure strengthening element and the upper surface of the protective layer are coplanar.

The second embodiment of the present disclosure provides a packaging structure including a circuit redistribution structure, a chip, an inner conductive reinforcement element, a first protective layer, and an electronic element. The circuit redistribution structure includes a first circuit layer and a second circuit layer disposed above the first circuit layer, wherein the first circuit layer is electrically connected to the second circuit layer. The chip is arranged on the circuit redistribution structure and is electrically connected to the second circuit layer. The internal conductive strengthening element is arranged on the circuit redistribution structure. The internal conductive strengthening element includes a strengthening layer and a conductive connection piece. The reinforced layer has 30~200GPa Young's modulus, and the reinforcement layer has through holes. The conductive connector is disposed in the through hole. The top and bottom of the conductive connector are exposed to the reinforcement layer, and the bottom of the conductive connector is electrically connected to the second circuit layer. The first protective layer covers the side walls of the wafer and the internal conductive strengthening element. The electronic component is disposed on the first protective layer and is electrically connected to the top of the conductive connector.

In the second embodiment of the present disclosure, the packaging structure further includes a substrate structure and a second protective layer. The substrate structure is disposed between the first protective layer and the electronic component, and the electronic component is electrically connected to the top of the conductive connector through the substrate structure. The second protective layer floods the electronic components.

In the second embodiment of the present disclosure, the inner conductive strengthening element surrounds the wafer.

In the second embodiment of the present disclosure, the inner conductive strengthening element and the wafer have a horizontal distance of 50 to 1000 microns.

In the second embodiment of the present disclosure, the reinforcement layer includes, but is not limited to, bismaleimide triazine resin, epoxy resin, glass, or ceramic.

In the second embodiment of the present disclosure, the upper surface of the inner conductive strengthening element and the upper surface of the first protective layer are coplanar.

The third embodiment of the present disclosure provides a packaging structure including a circuit redistribution structure, a chip, an internal conductive reinforcement element, a protective layer, and an antenna pattern. The circuit redistribution structure includes a first circuit layer and a second circuit layer disposed above the first circuit layer, wherein the first circuit layer is electrically connected to the second circuit layer. The chip is arranged on the circuit redistribution structure and is electrically connected to the second circuit layer. The internal conductive strengthening element is arranged on the circuit redistribution structure. The internal conductive strengthening element includes a strengthening layer and a conductive connection piece. The reinforced layer has 30~200GPa Young's Modulus, and the reinforcement layer has through holes. The conductive connection member is disposed in the through hole, wherein the top and bottom of the conductive connection member are exposed outside the reinforcement layer, and the bottom of the conductive connection member is electrically connected to the second circuit layer. The protective layer covers the side walls of the wafer and the internal conductive strengthening element. The antenna pattern is arranged on the protective layer, and is electrically connected to the top of the conductive connector.

In a third embodiment of the present disclosure, the inner conductive strengthening element surrounds the wafer.

In the third embodiment of the present disclosure, the inner conductive strengthening element and the wafer have a horizontal distance of 50 to 1000 microns.

In a third embodiment of the present disclosure, the strengthening layer includes but is not limited to bismaleimide triazine, glass, or ceramic.

In the third embodiment of the present disclosure, the upper surface of the inner conductive strengthening element and the upper surface of the protective layer are coplanar.

The fourth embodiment of the present disclosure provides a method for manufacturing a package structure, including the following operations: (i) providing a circuit redistribution structure, wherein the circuit redistribution structure includes a first circuit layer and is disposed on the first circuit layer A second circuit layer, and the first circuit layer is electrically connected to the second circuit layer; (ii) forming one or more structure strengthening elements on the circuit redistribution structure, wherein the structure strengthening elements have a Young's of 30~200GPa Module; (iii) setting a chip on the circuit redistribution structure, wherein the chip is electrically connected to the second circuit layer; and (iv) forming a protective layer to cover the chip and the structure strengthening element.

In the fourth embodiment of the present disclosure, after the operation (iv), it further includes: (v) removing a top portion of the protective layer to expose an upper surface of the structural strengthening element.

The fifth embodiment of the present disclosure provides a method for manufacturing a packaging structure, including the following operations: (i) providing a circuit redistribution structure, wherein the circuit redistribution structure includes a first circuit layer and a circuit layer disposed on the first circuit layer A second circuit layer on the top, and the first circuit layer is electrically connected to the second circuit layer; (ii) forming an internal conductive reinforcing element on the circuit redistribution structure, wherein the internal conductive reinforcing element includes: a reinforcing layer having 30~ A Young's modulus of 200GPa, in which the reinforcement layer has a through hole; and a conductive connection member, which is disposed in the through hole, wherein a top and a bottom of the conductive connection member are exposed outside the reinforcement layer, and the bottom of the conductive connection member is electrically Connect the second circuit layer; (iii) Set a chip on the circuit redistribution structure, where the chip is electrically connected to the second circuit layer; (iv) Form a first protective layer to cover the chip and the internal conductive strengthening element; and ( v) An electronic component is disposed on the first protective layer, wherein the electronic component is electrically connected to the top of the conductive connector.

In the fifth embodiment of the present disclosure, operation (ii) includes the following steps: (a) providing a substrate, wherein the substrate has a Young's modulus of 30 to 200 GPa; (b) performing a drilling process on the substrate, In order to form a strengthening layer with a through hole; (c) forming a conductive connector in the through hole to form an inner conductive strengthening element; and (d) setting an inner conductive strengthening element on the circuit redistribution structure.

In the fifth embodiment of the present disclosure, in operation (v), the electronic component is disposed on a substrate structure and is covered by a second protective layer, and the electronic component is electrically connected to the conductive connection member through the substrate structure the top of.

The sixth embodiment of the present disclosure provides a packaging junction The manufacturing method of the structure includes the following operations: (i) providing a circuit redistribution structure, wherein the circuit redistribution structure includes a first circuit layer and a second circuit layer disposed on the first circuit layer, and the first circuit The layer is electrically connected to the second circuit layer; (ii) forming an internal conductive reinforcing element on the circuit redistribution structure, wherein the internal conductive reinforcing element includes: a reinforcing layer with a Young's modulus of 30-200 GPa, wherein the reinforcing layer has A through hole; and a conductive connector disposed in the through hole, wherein a top and a bottom of the conductive connector are exposed to the reinforcement layer, and the bottom of the conductive connector is electrically connected to the second circuit layer; (iii) a The chip is on the circuit redistribution structure, wherein the chip is electrically connected to the second circuit layer; (iv) forming a protective layer to cover the chip and the internal conductive strengthening element; and (v) forming an antenna pattern on the protective layer, wherein the antenna The pattern is electrically connected to the top of the conductive connector.

The above description will be described in detail in the following embodiments, and the technical solutions of the present disclosure will be further explained.

10, 10a, 10b‧‧‧ package structure

100‧‧‧ Line redistribution structure

110‧‧‧ Redistribution layer of the first line

111‧‧‧ First circuit layer

112‧‧‧First insulation layer

112a‧‧‧via

113‧‧‧First conductive contact

120‧‧‧ Redistribution layer of the second line

121‧‧‧ Second circuit layer

122‧‧‧Second insulation layer

122a‧‧‧via

123‧‧‧Second conductive contact

130‧‧‧ Redistribution layer of the third line

131‧‧‧ Third circuit layer

132‧‧‧The third insulation layer

132a‧‧‧via

133‧‧‧third conductive contact

140‧‧‧conductive pad

200‧‧‧chip

200a‧‧‧First side

200b‧‧‧Second side

200c‧‧‧third side

210‧‧‧Metal bump

300‧‧‧Strengthening components

310‧‧‧adhesive material

400, 400"‧‧‧protection layer

410‧‧‧The first protective layer

420‧‧‧Second protective layer

500‧‧‧solder ball

510‧‧‧ welding material

600‧‧‧Internal conductive strengthening element

610‧‧‧Strengthening layer

610a‧‧‧Through hole

612‧‧‧ substrate

612a‧‧‧Through hole

613‧‧‧ substrate

620‧‧‧Conductive connector

700‧‧‧Electronic components

700c‧‧‧wire

800‧‧‧Substrate structure

810‧‧‧The first conductive pad

820‧‧‧Second conductive pad

900‧‧‧ Antenna pattern

S‧‧‧Substrate

D1‧‧‧Horizontal distance

R1‧‧‧Region

FIG. 1A is a schematic cross-sectional view of the package structure of the first embodiment of the present disclosure.

FIG. 1B is a schematic top view of a packaging structure according to an embodiment of the disclosure.

FIG. 1C is a schematic top view of a packaging structure according to an embodiment of the disclosure.

FIG. 1D is a top view of a packaging structure according to an embodiment of the disclosure intention.

FIG. 1E is a schematic top view of a packaging structure according to an embodiment of the present disclosure.

FIG. 2 is a schematic cross-sectional view of a packaging structure according to a second embodiment of the disclosure.

FIG. 3 is a schematic cross-sectional view of the package structure of the third embodiment of the present disclosure.

4 to 11 are cross-sectional schematic diagrams at various stages of the method for manufacturing a package structure according to the first embodiment of the present disclosure.

12 to 17 are cross-sectional schematic diagrams at various stages of a method of manufacturing a package structure according to a second embodiment of the present disclosure.

FIG. 18 is a schematic cross-sectional view of a stage of a method of manufacturing a package structure according to a third embodiment of the present disclosure.

19 to 22 are schematic cross-sectional views of various stages of a method of manufacturing an internal conductive strengthening element according to an embodiment of the present disclosure.

In order to make the description of this disclosure more detailed and complete, the following provides an illustrative description of the implementation and specific embodiments of this disclosure; however, this is not the only way to implement or use specific embodiments of this disclosure. The embodiments disclosed below can be combined or replaced with each other under beneficial circumstances, and other embodiments can be added to an embodiment without further description or description. In the following description, many specific details will be described in detail Section to enable the reader to fully understand the following embodiments. However, embodiments of the present disclosure may be practiced without these specific details.

Furthermore, relative spatial terms, such as "below", "below", "above", "above", etc., are for the convenience of describing the relative relationship between one element or feature and another element or feature. The true meaning of these spatial relative terms includes other orientations. For example, when the diagram is turned upside down by 180 degrees, the relationship between one component and another component may change from "below" and "below" to "above" and "above". In addition, the relative spatial description used in this article should also be interpreted in the same way.

Please refer to FIG. 1A, which is a schematic cross-sectional view of the package structure 10 according to the first embodiment of the present disclosure. The package structure 10 includes a circuit redistribution structure 100, a chip 200, one or more structural reinforcement elements 300, a protective layer 400, and a solder ball 500.

The circuit redistribution structure 100 includes a first circuit redistribution layer 110, a second circuit redistribution layer 120, a third circuit redistribution layer 130, and a conductive pad 140. Specifically, the first circuit redistribution layer 110 includes a first circuit layer 111, a first insulating layer 112, and a first conductive contact 113. In some embodiments, the first circuit layer 111 and the first conductive contact 113 include any conductive material, such as copper, nickel, or silver. In some embodiments, the line width and line spacing of the first circuit layer 111 are less than 8 microns, such as 7 microns, 6 microns, 5 microns, 4 microns, 3 microns, 2 microns, 1 microns, or 0.5 microns. The first insulating layer 112 covers the first circuit layer 111, and the first insulating layer 112 has a via 112a. In some embodiments, the first insulating layer 112 includes a photosensitive dielectric material. The via hole 112a exposes a portion of the first circuit layer 111, and the first conductive contact 113 has a total of A profile is formed in the via 112a so that the first conductive contact 113 contacts the first circuit layer 111.

The second circuit redistribution layer 120 is disposed on the first circuit redistribution layer 110. Specifically, the second circuit redistribution layer 120 includes a second circuit layer 121, a second insulating layer 122, and a second conductive contact 123. The second circuit layer 121 contacts the first conductive contact 113 so that the second circuit layer 121 is electrically connected to the first circuit layer 111. In some embodiments, the second circuit layer 121 and the second conductive contact 123 include any conductive material, such as copper, nickel, or silver. In some embodiments, the line width and line spacing of the second circuit layer 121 are less than 8 microns, such as 7 microns, 6 microns, 5 microns, 4 microns, 3 microns, 2 microns, 1 microns, or 0.5 microns. The second insulating layer 122 covers the second circuit layer 121, and the second insulating layer 122 has a via 122a. In some embodiments, the second insulating layer 122 includes a photosensitive dielectric material. The via hole 122 a exposes a portion of the second circuit layer 121, and the second conductive contact 123 is conformally formed in the via hole 122 a so that the second conductive contact 123 contacts the second circuit layer 121.

The third circuit redistribution layer 130 is disposed on the second circuit redistribution layer 120. Specifically, the third circuit redistribution layer 130 includes a third circuit layer 131, a third insulating layer 132, and a third conductive contact 133. The third circuit layer 131 contacts the second conductive contact 123 so that the third circuit layer 131 and the second circuit layer 121 are electrically connected. In some embodiments, the third circuit layer 131 and the third conductive contact 133 include any conductive material, such as copper, nickel, or silver. In some embodiments, the line width and line spacing of the third circuit layer 131 are less than 8 microns, such as 7 microns, 6 microns, 5 microns, 4 microns, 3 microns, 2 Micron, 1 micron or 0.5 microns. The third insulating layer 132 covers the third circuit layer 131, and the third insulating layer 132 has a via 132a. In some embodiments, the third insulating layer 132 includes a photosensitive dielectric material. The via hole 132 a exposes a portion of the third circuit layer 131, and the third conductive contact 133 is filled in the via hole 132 a so that the third conductive contact 133 contacts the third circuit layer 131.

The conductive pad 140 contacts the third conductive contact 133 so that the conductive pad 140 is electrically connected to the third circuit layer 131. In some embodiments, the conductive pad 140 includes any conductive material, such as copper, nickel, or silver.

The chip 200 is disposed on the circuit redistribution structure 100 and is electrically connected to the third circuit layer 131. Specifically, the lower surface of the wafer 200 is provided with a plurality of metal bumps 210 (eg, wafer pins), and the metal bumps 210 are bonded to the conductive pad 140 via a solder material, so that the wafer 200 is electrically connected to the third circuit layer 131.

One or more structure strengthening elements 300 are disposed on the circuit redistribution structure 100. Specifically, the structural reinforcement element 300 is bonded to the third circuit redistribution layer 130 through the adhesive material 310. In some embodiments, the adhesive material 310 includes silicone glue, epoxy glue, polyimide (PI) glue or polyethylene terephthalate (PET) glue, but not as such limit. It should be understood that the structural strengthening element 300 has a Young's modulus of 30 to 200 GPa, such as 100, 150, or 200. As mentioned above, conventional chip packaging structures often suffer from severe warpage due to thermal processes. In particular, when the size of the chip package structure exceeds a certain range, the warpage phenomenon is particularly serious, for example, when the chip package When the length of the structure is 15 mm or more and the width is 15 mm or more. However, due to the arrangement of the structure strengthening element 300, the package structure 10 of the present disclosure is less prone to warping.

In detail, the structural strengthening element 300 has a Young's modulus of 30 to 200 GPa, thus providing sufficient mechanical strength of the packaging structure 10. According to this, even if the coefficients of thermal expansion of each element material in the packaging structure 10 are very different, warping is unlikely to occur. In some embodiments, the structural strengthening element 300 includes, but is not limited to, bismaleimide-tirazine (BT) resin, epoxy resin, solder paste, or copper paste. Preferably, in some embodiments, the structural strengthening element 300 and the wafer 200 have a horizontal distance D1, and the horizontal distance D1 is 50-1000 microns.

For a clearer understanding of the relationship between the wafer 200 and the structural strengthening element 300, please refer to FIG. 1B. FIG. 1B is a schematic top view of a package structure 10 according to an embodiment of the disclosure. As shown in FIG. 1B, the package structure 10 includes a structure strengthening element 300, and the structure strengthening element 300 surrounds the wafer 200. Specifically, the top view outline of the structural reinforcement element 300 has a “mouth” shape.

In another embodiment, the packaging structure 10 includes a plurality of structural strengthening elements 300, as shown in FIG. 1C. FIG. 1C is a schematic top view of a package structure 10 according to an embodiment of the disclosure. A plurality of structure strengthening elements 300 are arranged around the wafer 200. Specifically, the structural reinforcement element 300 is provided on the four sides of the wafer 200.

Alternatively, the plurality of structure strengthening elements 300 may be disposed on only two sides of the wafer 200, please refer to FIGS. 1D and 1E. As 1D As shown in the figure, a plurality of structure strengthening elements 300 are disposed on the first side 200a and the second side 200b of the wafer 200, and the first side 200a is opposite to the second side 200b. Alternatively, as shown in FIG. 1E, a plurality of structure strengthening elements 300 are provided on the first side 200a and the third side 200c of the wafer 200, and the first side 200a is adjacent to the third side 200c.

Returning to FIG. 1A, the protective layer 400 covers the side walls of the wafer 200 and the structural reinforcement element 300 and fills the gap between the wafer 200 and the third circuit redistribution layer 130. Specifically, the upper surface of the structural reinforcement element 300 and the upper surface of the protective layer 400 are coplanar. The protective layer 400 can protect the bonding between the metal bumps 210 of the wafer 200 and the conductive pad 140, thereby avoiding peeling. On the other hand, the protective layer 400 can also block moisture and prevent the oxidation of the metal bump 210, the solder material, and the conductive pad 140. In some embodiments, the protective layer 400 includes resin.

The solder ball 500 is disposed under the circuit redistribution structure 100. Specifically, the solder ball 500 contacts the first circuit layer 111 so that the solder ball 500 is electrically connected to the first circuit layer 111. In some embodiments, the solder ball 500 includes lead, tin, silver, copper, bismuth, antimony, zinc, or other welding metals, but not limited thereto.

Please refer to FIG. 2, which is a schematic cross-sectional view of the package structure 10 a according to the second embodiment of the present disclosure. The package structure 10a includes a circuit redistribution structure 100, a chip 200, an internal conductive reinforcement element 600, a first protective layer 410, an electronic element 700, and a solder ball 500. For the details of the circuit redistribution structure 100, the chip 200, and the solder ball 500, please refer to the description in FIG. 1A and the corresponding relevant paragraphs, which will not be repeated here.

The internal conductive reinforcing element 600 is disposed on the circuit redistribution structure 100 The inner conductive strengthening element 600 includes a strengthening layer 610 and a conductive connection 620. In some embodiments, the conductive connector 620 includes any conductive material, such as copper, nickel, or silver. Specifically, the reinforcement layer 610 has a through hole 610a, and the conductive connection member 620 is disposed in the through hole 610a. More specifically, the top and bottom of the conductive connector 620 are exposed outside the reinforcement layer 610, and the bottom of the conductive connector 620 contacts the conductive pad 140 so that the conductive connector 620 is electrically connected to the third circuit layer 131.

It should be understood that the strengthening layer 610 has a Young's modulus of 30 to 200 GPa, thus providing sufficient mechanical strength of the packaging structure 10a. In some embodiments, the reinforcement layer 610 includes, but is not limited to, bismaleimide triazine resin, epoxy resin, glass, or ceramic. Preferably, in some embodiments, the inner conductive strengthening element 600 and the wafer 200 have a horizontal distance D1, and the horizontal distance D1 is 50-1000 microns.

The relationship between the wafer 200 and the internal conductive strengthening element 600 may correspond to the relationship between the wafer 200 and the structural strengthening element 300 in FIG. 1B. That is, the inner conductive strengthening element 600 surrounds the wafer 200.

The first protective layer 410 covers the side walls of the wafer 200 and the inner conductive strengthening element 600 and fills the gap between the wafer 200 and the third circuit redistribution layer 130. Specifically, the upper surface of the inner conductive strengthening element 600 and the upper surface of the first protective layer 410 are coplanar. The first protective layer 410 can protect the bonding between the metal bumps 210 of the wafer 200 and the conductive pad 140, so as to avoid peeling. On the other hand, the first protective layer 410 can also block moisture and prevent the oxidation of the metal bump 210, the solder material, and the conductive pad 140. In some embodiments, the first protective layer 410 includes resin.

The electronic component 700 is disposed on the first protective layer 410 and is electrically connected to the top of the conductive connector 620. Specifically, the electronic component 700 is disposed on a substrate structure 800, and is covered by a second protective layer 420. The substrate structure 800 has a first conductive pad 810, a second conductive pad 820 and an internal circuit, and the internal circuit is electrically connected to the first conductive pad 810 and the second conductive pad 820. As shown in FIG. 2, the electronic component 700 is electrically connected to the first conductive pad 810 through a wire 700c. In addition, the second conductive pad 820 is electrically connected to the top of the conductive connector 620 through a solder material 510. In some embodiments, the welding material 510 includes lead, tin, silver, copper, bismuth, antimony, zinc, or other welding metals, but not limited thereto.

The second protective layer 420 can block moisture and prevent oxidation of the wire 700c and the first conductive pad 810. In some embodiments, the second protective layer 420 includes resin. In some embodiments, the electronic component 700 is a memory.

Please refer to FIG. 3, which is a schematic cross-sectional view of a package structure 10b according to a third embodiment of the present disclosure. It should be noted that in FIG. 3, elements that are the same as or similar to FIG. 2 are given the same symbols, and related descriptions are omitted. The package structure 10b of FIG. 3 is similar to the package structure 10a of FIG. 2 except that the package structure 10b of FIG. 3 does not have components such as the electronic component 700, the substrate structure 800, and the second protective layer 420. Instead, the packaging structure 10b further includes an antenna pattern 900. The antenna pattern 900 is disposed on the first protective layer 410 and contacts the top of the conductive connector 620 to be electrically connected to the conductive connector 620.

The disclosure also provides a method of manufacturing a packaging structure. 4 to 11 are cross-sectional schematic diagrams at various stages of the manufacturing method of the package structure 10 according to the first embodiment of the present disclosure.

As shown in FIG. 4, a first circuit layer 111 is formed on a substrate S. For example, a conductive material is formed on the substrate S, and the conductive material is patterned to form the first circuit layer 111. In some embodiments, the method of forming the conductive material includes electroplating, chemical vapor deposition, physical vapor deposition, etc., but it is not limited thereto.

Next, as shown in FIG. 5, a first insulating layer 112 is formed to cover the first circuit layer 111, and the first insulating layer 112 includes a via 112 a that exposes a part of the first circuit layer 111. For example, a dielectric material is formed on the first circuit layer 111, and the dielectric material is patterned to form the via hole 112a. In some embodiments, the method for forming the dielectric material includes chemical vapor deposition, physical vapor deposition, etc., but not limited thereto. In some embodiments, the method of patterning the conductive material and the dielectric material includes depositing a photoresist on the layer to be patterned, and performing exposure and development to form a patterned photoresist layer. Next, the patterned photoresist layer is used as an etching mask to etch the layer to be patterned. Finally, the patterned photoresist layer is removed. Alternatively, in embodiments where the dielectric material is a photosensitive dielectric material, a portion of the photosensitive dielectric material can be removed by exposure and development to complete patterning.

Next, a second circuit layer 121 is formed on the first insulating layer 112, and a first conductive contact 113 is conformally formed in the via hole 112a. For example, a conductive material is formed on the first insulating layer 112 and conformally formed in the via hole 112a. Next, the conductive material is patterned to form the second circuit layer 121 and the first conductive contact 113.

Next, as shown in FIG. 6, a second insulating layer 122 is formed to cover the second wiring layer 121, and the second insulating layer 122 includes a via hole 122 a exposing a part of the second wiring layer 121. For example, a dielectric material is formed on the second circuit layer 121, and the dielectric material is patterned to form the via hole 122a.

Next, a third circuit layer 131 is formed on the second insulating layer 122, and a second conductive contact 123 is conformally formed in the via hole 122a. For example, a conductive material is formed on the second insulating layer 122 and conformally formed in the via hole 122a. Next, the conductive material is patterned to form the third circuit layer 131 and the second conductive contact 123.

Next, as shown in FIG. 7, a third insulating layer 132 is formed to cover the third circuit layer 131, and the third insulating layer 132 includes a via hole 132 a exposing a part of the third circuit layer 131. For example, a dielectric material is formed on the third circuit layer 131, and the dielectric material is patterned to form the via hole 132a.

Next, a conductive pad 140 is formed on the third insulating layer 132, and a third conductive contact 133 is formed in the via hole 132a. For example, a conductive material is formed on the third insulating layer 132 and formed in the via hole 132a. Next, the conductive material is patterned to form the conductive pad 140 and the third conductive contact 133. Thus, the circuit redistribution structure 100 is formed on the substrate S.

Next, as shown in FIG. 8, one or more structural reinforcement elements 300 are formed on the circuit redistribution structure 100. For example, the bonding material 310 is used to attach the structural reinforcement element 300 to the third circuit redistribution layer 130.

Next, as shown in FIG. 9, the wafer 200 is placed on the circuit redistribution structure 100. For example, a plurality of metal bumps 210 (eg, wafer pins) on the lower surface of the wafer 200 are bonded to the conductive pad 140 using a solder material.

Next, as shown in FIG. 10, a protective layer 400 ″ is formed to cover the wafer 200 and the structural reinforcement element 300 and fill the gap between the wafer 200 and the third circuit redistribution layer 130.

Next, a chemical mechanical polishing (CMP) process is used to remove the top of the protective layer 400", thereby forming a protective layer 400 that exposes the upper surface of the structure strengthening element 300 as shown in FIG. 11. It should be noted that , Removing the top of the protective layer 400" provides specific technical effects. In detail, the thermal expansion coefficient of the material of the protective layer 400" usually differs greatly from the thermal expansion coefficients of other devices. Therefore, the excessively thick protective layer 400" is likely to cause warpage of the packaging structure. By removing the top of the protective layer 400", the warpage of the packaging structure can be improved.

Next, the substrate S is peeled off to expose the first circuit layer 111. Subsequently, a solder ball 500 that contacts the first wiring layer 111 is formed, thereby forming the package structure 10 shown in FIG. 1A.

12 to 17 are cross-sectional schematic diagrams at various stages of the manufacturing method of the package structure 10a according to the second embodiment of the present disclosure. FIG. 12 continues from FIG. 6, a third insulating layer 132 is formed to cover the third circuit layer 131, and the third insulating layer 132 includes a via hole 132a exposing a part of the third circuit layer 131. For example, a dielectric material is formed on the third circuit layer 131, and the dielectric material is patterned to form the via hole 132a.

Next, a conductive pad 140 is formed on the third insulating layer 132, and a third conductive contact 133 is formed in the via hole 132a. For example, a conductive material is formed on the third insulating layer 132 and formed in the via hole 132a. Next, the conductive material is patterned to form the conductive pad 140 and the third conductive contact 133. Thus, the circuit redistribution structure 100 is formed on the substrate S.

Next, as shown in FIG. 13, an internal conductive reinforcement element 600 is formed on the circuit redistribution structure 100. For example, the conductive connection member 620 of the inner conductive reinforcing element 600 is bonded to the conductive pad 140 through a bonding process. It is worth mentioning that the conductive pad 140 has a recess (as shown in FIG. 12) to provide specific technical effects. In detail, when the conductive connection member 620 and the conductive pad 140 are joined, the bottom of the conductive connection member 620 presses the inclined surface of the recess of the conductive pad 140, thereby generating a driving force, so that the conductive connection member 620 and the conductive pad 140 The diffusion speed of copper atoms (when both materials are copper) can be effectively increased. Therefore, the temperature and pressure required during the bonding process of the conductive connector 620 and the conductive pad 140 can be effectively reduced. At the same time, because there is no need to withstand higher temperatures and pressures, the overall structural stability can be effectively improved. The conductive pad 140 has the advantages of depressions, such as reducing the temperature and pressure required during the bonding process, and improving the structural stability. Please refer to US Patent Application No. 15/590,020 (all of which are incorporated by reference) In this article), I will not repeat them here.

Here, a method for manufacturing the internal conductive reinforcing element 600 is also provided. Please refer to FIG. 19 to FIG. 22. FIG. 19 to FIG. 22 are schematic cross-sectional views at various stages of the method for manufacturing the conductive strengthening element 600 according to an embodiment of the present disclosure. As shown in FIG. 19, a substrate 613 is first provided, wherein the substrate 613 has a Young's modulus of 30 to 200 GPa. Next, as shown in FIG. 20, a drilling process is performed to form a substrate 612 having a through hole 612a. Next, through the electroplating process, the conductive connecting member 620 shown in FIG. 21 is formed in the through hole 612a. Subsequently, a removal process (for example, by Etching) to remove the portion of the substrate 612 located in the region R1, thereby forming the inner conductive strengthening element 600 as shown in FIG. 22. The area R1 is the position where the wafer 200 is set in the subsequent operation.

Next, as shown in FIG. 14, the wafer 200 is placed on the circuit redistribution structure 100. For example, a plurality of metal bumps 210 (eg, wafer pins) on the lower surface of the wafer 200 are bonded to the conductive pad 140 using a solder material.

Next, as shown in FIG. 15, a protective layer 400 ″ is formed to cover the wafer 200 and the inner conductive reinforcement element 600 and fill the gap between the wafer 200 and the third circuit redistribution layer 130.

Next, a chemical mechanical polishing process is used to remove the top of the protective layer 400" to form the first protective layer 410 that exposes the upper surface of the inner conductive strengthening element 600 as shown in FIG. 16. As described above, by removing In addition to the top of the protective layer 400", the warpage of the packaging structure can be improved.

Next, as shown in FIG. 17, the electronic component 700 is disposed on the first protective layer 410, and the electronic component 700 is electrically connected to the top of the conductive connector 620. Specifically, the second conductive pad 820 is joined to the top of the conductive connection 620 using a solder material 510. The electronic component 700 is electrically connected to the first conductive pad 810 through a wire 700c, and the first conductive pad 810 is electrically connected to the second conductive pad 820 through an internal line. Therefore, the electronic component 700 is electrically connected to the top of the conductive connector 620.

Next, the substrate S is peeled off to expose the first circuit layer 111. Subsequently, solder balls 500 contacting the first wiring layer 111 are formed, thereby forming the package structure 10a shown in FIG. 2.

FIG. 18 is the package structure of the third embodiment of the present disclosure A schematic cross-sectional view of one stage of the manufacturing method of the structure 10b. FIG. 18 continues from FIG. 16 to form an antenna pattern 900 on the first protective layer 410 so that the antenna pattern contacts and is electrically connected to the top of the conductive connection member 620.

Next, the substrate S is peeled off to expose the first circuit layer 111. Subsequently, a solder ball 500 that contacts the first wiring layer 111 is formed, thereby forming a package structure 10b as shown in FIG. 3.

It can be known from the above embodiments of the invention that the package structure disclosed here has sufficient mechanical strength. Therefore, even if the coefficients of thermal expansion of each element material in the packaging structure are very different, warpage is unlikely to occur. In addition, since the package structure is less prone to warping, it is suitable to form a flat antenna pattern directly on the package structure. Or, another packaging structure is provided on the packaging structure to make a stacked packaging structure.

Although the present disclosure has been disclosed as above, other embodiments are also possible. Therefore, the spirit and scope of the requested items are not limited to the description contained in the embodiments herein.

Anyone who is familiar with this skill can understand that various changes and modifications can be made without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be subject to the scope defined in the attached patent application.

10‧‧‧Package structure

100‧‧‧ Line redistribution structure

110‧‧‧ Redistribution layer of the first line

111‧‧‧ First circuit layer

112‧‧‧First insulation layer

112a‧‧‧via

113‧‧‧First conductive contact

120‧‧‧ Redistribution layer of the second line

121‧‧‧ Second circuit layer

122‧‧‧Second insulation layer

122a‧‧‧via

123‧‧‧Second conductive contact

130‧‧‧ Redistribution layer of the third line

131‧‧‧ Third circuit layer

132‧‧‧The third insulation layer

132a‧‧‧via

133‧‧‧third conductive contact

140‧‧‧conductive pad

200‧‧‧chip

210‧‧‧Metal bump

300‧‧‧Strengthening components

310‧‧‧adhesive material

400‧‧‧Protective layer

500‧‧‧solder ball

D1‧‧‧Horizontal distance

Claims (16)

A packaging structure includes: a circuit redistribution structure, including a first circuit layer and a second circuit layer disposed on the first circuit layer, wherein the first circuit layer is electrically connected to the second circuit layer; A chip is arranged on the circuit redistribution structure and is electrically connected to the second circuit layer; a structure strengthening element is arranged on the circuit redistribution structure, wherein the structure strengthening element has a Young's mold of 30~200GPa In which, the structure strengthening element surrounds the wafer; and a protective layer overlies the side wall of the wafer and the structure strengthening element, wherein an upper surface of the structure strengthening element and an upper surface of the protective layer are coplanar. A packaging structure includes: a circuit redistribution structure, including a first circuit layer and a second circuit layer disposed on the first circuit layer, wherein the first circuit layer is electrically connected to the second circuit layer; A chip is disposed on the circuit redistribution structure and is electrically connected to the second circuit layer; a plurality of structural strengthening elements are disposed on the circuit redistribution structure, wherein the structure strengthening element has a Young Modulus, and one of the structural strengthening elements is located on a first side of the wafer, the other of the structural strengthening elements is located on a second side of the wafer, and the second side and the first Side-to-side or adjacent; and A protective layer covers the side walls of the chip and the structural strengthening element, wherein an upper surface of the structural strengthening element and an upper surface of the protective layer are coplanar. The packaging structure as described in item 1 or 2 of the patent application scope, wherein the structure strengthening element has a horizontal distance of 50-1000 microns from the chip. The packaging structure as described in item 1 or item 2 of the patent application scope, wherein the material of the structural strengthening element includes bismaleimide triazine resin, epoxy resin, solder paste or copper paste. A packaging structure includes: a circuit redistribution structure, including a first circuit layer and a second circuit layer disposed on the first circuit layer, wherein the first circuit layer is electrically connected to the second circuit layer; A chip is arranged on the circuit redistribution structure and is electrically connected to the second circuit layer; an inner conductive reinforcement element is arranged on the circuit redistribution structure and the inner conductive reinforcement element surrounds the chip, wherein the inner The conductive strengthening element includes: a strengthening layer having a Young's modulus of 30-200 GPa, wherein the strengthening layer has a through hole; and a conductive connection member disposed in the through hole, wherein a top of the conductive connection member and A bottom is exposed outside the reinforcement layer, and the bottom of the conductive connection is electrically connected to the second circuit layer; A first protective layer covering the side walls of the chip and the inner conductive strengthening element, wherein an upper surface of the inner conductive strengthening element and an upper surface of the first protective layer are coplanar; and an electronic element is disposed on the The first protective layer is electrically connected to the top of the conductive connection. The packaging structure as described in item 5 of the patent application scope further includes: a substrate structure disposed between the first protective layer and the electronic component, and the electronic component is electrically connected to the conductive connector through the substrate structure The top; and a second protective layer to cover the electronic component. The packaging structure as described in item 5 of the patent application scope, wherein the inner conductive strengthening element and the chip have a horizontal distance of 50 to 1000 microns. The packaging structure as described in item 5 of the patent application scope, wherein the reinforcing layer material includes bismaleimide triazine resin, epoxy resin, glass or ceramics. A packaging structure includes: a circuit redistribution structure, including a first circuit layer and a second circuit layer disposed on the first circuit layer, wherein the first circuit layer is electrically connected to the second circuit layer; A chip is disposed on the circuit redistribution structure and is electrically connected to the second circuit layer; an inner conductive reinforcement element is disposed on the circuit redistribution structure, the inner conductive reinforcement element surrounds the chip, wherein the inner conductive The strengthening element includes: a strengthening layer with a Young's modulus of 30-200 GPa, wherein the strengthening layer has a through hole; and a conductive connection member disposed in the through hole, wherein a top and a top of the conductive connection member The bottom is exposed outside the reinforcement layer, and the bottom of the conductive connector is electrically connected to the second circuit layer; a protective layer covers the side walls of the chip and the inner conductive reinforcement element, wherein one of the inner conductive reinforcement elements The upper surface and a top surface of the protective layer are coplanar; and an antenna pattern is disposed on the protective layer and is electrically connected to the top of the conductive connector. The package structure as described in item 9 of the patent application range, wherein the inner conductive strengthening element and the chip have a horizontal distance of 50 to 1000 microns. The packaging structure as described in item 9 of the patent application range, wherein the strengthening layer comprises bismaleimide triazine resin, glass or ceramics. A manufacturing method of a packaging structure includes the following operations: (i) providing a circuit redistribution structure, wherein the circuit redistribution structure includes a first circuit layer and a second circuit disposed on the first circuit layer Layer, and the first circuit layer is electrically connected to the second circuit layer; (ii) forming one or more structure strengthening elements on the circuit redistribution structure, wherein the structure strengthening elements have a Young's mold of 30~200GPa (Iii) setting a chip on the circuit redistribution structure, wherein the chip is electrically connected to the second circuit layer; (iv) forming a protective layer to cover the chip and the structure strengthening element; and (v) removing A top of the protective layer exposes an upper surface of the structural strengthening element. A manufacturing method of a packaging structure includes the following operations: (i) providing a circuit redistribution structure, wherein the circuit redistribution structure includes a first circuit layer and a second circuit layer disposed on the first circuit layer, And the first circuit layer is electrically connected to the second circuit layer; (ii) forming an inner conductive reinforcement element on the circuit redistribution structure, wherein the inner conductive reinforcement element includes: a reinforcement layer with a thickness of 30~200GPa Young's modulus, wherein the reinforcement layer has a through hole; and a conductive connection member is disposed in the through hole, wherein a top and a bottom of the conductive connection member are exposed outside the reinforcement layer, and the conductive connection member The bottom is electrically connected to the second circuit layer; (iii) a chip is disposed on the circuit redistribution structure, wherein the chip is electrically connected to the second circuit layer; (iv) a first protective layer is formed to cover the chip And the internal conductivity strengthening Component; and (v) an electronic component is disposed on the first protective layer, wherein the electronic component is electrically connected to the top of the conductive connector. The method for manufacturing a packaging structure as described in item 13 of the patent application scope, wherein operation (ii) includes the following steps: (a) providing a substrate, wherein the substrate has a Young's modulus of 30 to 200 GPa; (b) The substrate undergoes a drilling process to form the reinforcement layer with the through hole; (c) forming the conductive connection member in the through hole to form the inner conductive reinforcement element; and (d) providing the inner conductive reinforcement The component is on the circuit redistribution structure. The method for manufacturing a packaging structure as described in item 13 of the patent application scope, wherein in operation (v), the electronic component is disposed on a substrate structure and is covered by a second protective layer, and the electronic component passes through the The substrate structure is electrically connected to the top of the conductive connector. A manufacturing method of a packaging structure includes the following operations: (i) providing a circuit redistribution structure, wherein the circuit redistribution structure includes a first circuit layer and a second circuit layer disposed on the first circuit layer, And the first circuit layer is electrically connected to the second circuit layer; (ii) forming an internal conductive reinforcing element on the circuit redistribution structure, wherein the internal conductive reinforcing element includes: A reinforced layer having a Young's modulus of 30 to 200 GPa, wherein the reinforced layer has a through hole; and a conductive connector disposed in the through hole, wherein a top and a bottom of the conductive connector are exposed to the Outside the reinforcement layer, and the bottom of the conductive connector is electrically connected to the second circuit layer; (iii) a chip is placed on the circuit redistribution structure, wherein the chip is electrically connected to the second circuit layer; (iv) Forming a protective layer to cover the chip and the inner conductive strengthening element; and (v) forming an antenna pattern on the protective layer, wherein the antenna pattern is electrically connected to the top of the conductive connection member.

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