TWI682271B - Server system - Google Patents

Abstract

The present disclosure provides a server system comprising: a CPLD having a first firmware and a first serial peripheral interface; a serial peripheral read only memory having a second firmware and a second serial peripheral interface; wherein the first serial peripheral interface and the second serial peripheral interface are electrically connected through a serial peripheral signal. When the server system is turned on, the CPLD scans the first firmware and the second firmware. The CPLD configures the first firmware as the main firmware and the first firmware leads the booting when the first firmware exists. The CPLD configures the second firmware as the main firmware when the first firmware does not existed and the second exists.

Description

Server system

The invention relates to the technical field of servos, in particular to a servo system.

At present, a PAL (Programmable Array Logic) chip is used on the main board of the server to realize the timing control of the server system and the setting of some registers. It can be seen that the PAL chip is very important for the server.

During the operation of the system, if the timing of the firmware or the value of the register is wrong or confusing, the entire system will shut down. At this time, the traditional method can only update the firmware of the CPLD (Complex Programmable Logic Device). However, once the server is mass-produced, it is more troublesome for customers to update the firmware, because they cannot update the firmware conveniently and familiarly, and can only return to the factory, which will undoubtedly increase the company's cost.

In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a server system for solving the technical problem that the firmware of the server CPLD in the prior art causes the system to fail to boot normally.

To achieve the above and other related objects, the present invention provides a server system, including: a complex programmable logic device, including a first firmware and a first serial peripheral device interface; and serial peripheral device read-only memory, including The second firmware and the second serial peripheral device interface; the first serial peripheral device interface and the second serial peripheral device interface are electrically connected through the serial peripheral device signal; when the server is When the system is booted, the complex programmable logic device scans the first firmware and the second firmware. When the first firmware is present, the complex programmable logic device configures the first firmware as the main firmware and is booted by the first firmware When the first firmware does not exist and the second firmware exists, the complex programmable logic device configures the second firmware as the main firmware and leads the boot.

In an embodiment of the invention, the complex programmable logic device further includes a control module, a configuration module, a logic module, and a serial peripheral device interface control module.

In an embodiment of the invention, the complex programmable logic device further includes a selector, which is electrically connected to the serial peripheral device interface control module, the first serial peripheral device interface and the logic module, respectively, and the logic module controls The selector performs system booting judgment to determine whether the first firmware configured by the complex programmable logic device leads the booting or the second firmware configured by the serial peripheral device read-only memory.

In an embodiment of the invention, the complex programmable logic device uses a self-download mode to scan the first firmware.

In an embodiment of the invention, when the first firmware does not exist, the self-download mode configuration fails, and the complex programmable logic device uses the main serial peripheral device interface configuration mode to scan the second firmware.

In an embodiment of the present invention, the complex programmable logic device controls the serial peripheral device interface control module to be in the master control mode through the configuration module, and controls the serial peripheral device read-only memory to be the slave mode.

In one embodiment of the present invention, the complex programmable logic device controls the configuration serial peripheral device interface through the configuration module. The control module is in the slave mode, and controls the serial peripheral device read-only memory to be the master control mode.

In an embodiment of the invention, the first firmware is burned off-line by the production line, The second firmware is burned off-line by the production line.

In an embodiment of the invention, the format of the first firmware is a joint engineering design format or a universal bus format.

In an embodiment of the invention, the format of the second firmware is a binary format.

As described above, the server system of the present invention includes: a complex programmable logic device, including a first firmware and a first serial peripheral device interface; a serial peripheral device read-only memory, including a second firmware and a second serial Serial peripheral device interface; the first serial peripheral device interface and the second serial peripheral device interface are electrically connected through serial peripheral device signals; when the server system is powered on, the complex programmable logic device scans the first firmware and the second Firmware, when the first firmware exists, the complex programmable logic device configures the first firmware as the main firmware and is booted by the first firmware. When the first firmware does not exist and the second firmware exists, the complex The programmable logic device configures the second firmware as the main firmware. Through the technical solution of the present invention, the server can ensure the normal operation of the system even if the CPLD firmware has a problem. The above description of the disclosure and the following description of the embodiments are used to demonstrate and explain the spirit and principle of the present invention, and provide a further explanation of the scope of the patent application of the present invention.

10‧‧‧Server system

11‧‧‧ Complex programmable logic device

12‧‧‧Read-only memory for serial peripherals

111‧‧‧ First firmware

112‧‧‧The first serial peripheral device interface

113‧‧‧Control module

114‧‧‧Configuration module

115‧‧‧Logic module

116‧‧‧ Serial peripheral device interface control module

117‧‧‧selector

121‧‧‧ Second firmware

122‧‧‧Second serial peripheral interface

Figure 1 shows the schematic diagram of the JTAG switch multiplexing circuit of the CPLD in the existing server system.

FIG. 2 is a schematic structural diagram of a server system according to an embodiment of the invention.

FIG. 3 shows a detailed structural diagram of the server system in the embodiment of FIG. 2.

4 is a schematic structural diagram of a server system in another embodiment of the present invention.

The following describes the embodiments of the present invention through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments. The details in this specification can also be based on different viewpoints and applications, and various modifications or changes can be made without departing from the spirit of the present invention. It should be noted that the following embodiments and the features in the embodiments can be combined with each other without conflict.

It should be noted that the drawings provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show the elements related to the present invention rather than the number, shape and shape of the elements in actual implementation. Dimension drawing, the type, quantity and ratio of each element can be changed arbitrarily during its actual implementation, and its element layout type may also be more complicated.

FIG. 1 shows a schematic diagram of a switch multiplex circuit of a joint test work group (JTAG) of a complex programmable logic device (CPLD) in an existing server system. In the development stage, the server system includes a joint test work group connector (JTAG CONN), which is electrically connected to the CPLD joint test work group port (JTAG Port). When the external programming cable is connected to the JTAG Port, CPLD receives the programming file sent by the external device through JTAG CONN, and updates the firmware in the CPLD according to the programming file.

As shown in FIG. 1, for example, when both the output enable pin OE_N and the selection pin S output a low level, U182 selects JTAG to update the firmware, and XBIT_PAL_JTAG_N is a low level, that is, PAL_JTAG_DIS is a low level. As long as the cable is connected to JTAG CONN, PAL_HDR_N is the low level. In this way, the Switch MUX will select the JTAG CONN mode, so use JTAG CONN to update the firmware of the CPLD. If the cable is not connected to JTAG CONN, PAL_HDR_N is the high level, XBIT_PAL_JTAG_N is still the low level, that is, PAL_JTAG_DIS is still the low level. At this time, U182 will select the GMT mode, that is, you can update the CPLD firmware in ILO (Integrated Ligths-out, integrated remote management port on the HP server) mode.

Although, through the switching circuit of FIG. 1, the CPLD firmware in the JTAG interface mode and the GMT mode can be automatically switched, that is, the commonly used JLD format of the CPLD firmware (Joint engineering design, That is, joint engineering design) and VME format (Versa module Eurocard bus, universal bus) to meet the needs of different experimental groups and different users. However, once the server enters mass production, in order to save costs, JTAG CONN will be completely removed. Once the server cannot be turned on and other problems, customers can only choose to return to the factory for maintenance, which greatly increases the company's operating costs.

The purpose of the present invention is to provide a server system to ensure the normal booting of the system even when the firmware of the complex programmable logic device CPLD has problems.

As shown in FIG. 2, the server system 10 of this embodiment includes: a complex programmable logic device 11 and a serial peripheral device read-only memory 12, wherein the complex programmable logic device 11 and serial peripheral device read-only memory 12 communication connections.

Specifically, the complex programmable logic device 11 includes a first firmware 111 and a first serial peripheral interface 112. The first firmware 111 is pre-programmed from the production line to the complex programmable logic device 11 in an offline manner, and the format thereof is, for example, a joint engineering design format or a general bus format. The serial peripheral device read-only memory 12 includes a second firmware 121 and a second serial peripheral device interface 122. The second firmware 121 is pre-programmed from the production line to the serial peripheral device read-only memory 12 in an offline manner, and its format is, for example, a binary format. The first serial peripheral device interface 112 and the second serial peripheral device interface 122 are electrically connected through serial peripheral device signals.

When the server system 10 is turned on, the complex programmable logic device 11 scans the first firmware 111 and the second firmware 121. If the first firmware 111 exists, the complex programmable logic device 11 configures the first firmware 111 as the main firmware, and causes the first firmware 111 to boot up; when the first firmware 111 does not exist and the second firmware 111 When 121 exists, the complex programmable logic device 11 configures the second firmware 121 as the main firmware and directs the boot.

As shown in FIG. 3, the complex programmable logic device 11 of this embodiment further includes a control module 113, a configuration module 114, a logic module 115, and a serial peripheral device interface control module 116, wherein the configuration modules 114 are respectively It is electrically connected to the control module 113, the logic module 115, and the serial peripheral device interface control module 116.

In this embodiment, the complex programmable logic device 11 scans the first firmware 111 using the self-download mode. At this time, the complex programmable logic device 11 is the master configuration, and the serial peripheral device read-only memory 12 is the slave configuration. The complex programmable logic device 11 controls the serial peripheral device interface control module 116 through the configuration module 114 to be in the master control Mode, so that the serial peripheral device read-only memory 12 is a slave mode. When the first firmware 111 does not exist, the self-download mode configuration fails. At this time, the serial peripheral device read-only memory 12 becomes the master configuration, and the complex programmable logic device 11 becomes the slave configuration, the complex programmable logic The device 11 controls the serial peripheral device interface control module 116 in the slave mode through the configuration module 114, so that the serial peripheral device read-only memory 12 is in the master control mode, and the complex programmable logic device 11 uses the master serial peripheral device interface Scan the second firmware 121 in the configuration mode.

As shown in FIG. 4, further, in another embodiment, the complex programmable logic device 11 further includes a selector 117. The selector 117 is electrically connected between the logic module 115 and the serial peripheral device interface control module 116, and is also connected to the first serial peripheral device interface 112 to connect with The serial peripheral device read-only memory 12 communicates. The logic module 115 controls the selector 117 to perform system booting judgment. The selector 117 judges whether the first firmware 111 configured by the complex programmable logic device 11 leads the booting or the second firmware configured by the serial peripheral device read-only memory 12 Body 121 leads the boot.

During the research and development stage of the server system, the read-only memory of the joint test work group connector and the serial peripheral devices are retained, that is, the firmware of the CPLD can be updated through the joint test work group connector, and the serial peripheral devices Read only memory to update the firmware of CPLD. In the final stage of R&D, when the firmware is burned for the first time through a JTAG cable, the complex programmable logic device is configured as a serial peripheral device interface non-volatile memory mode, and the joint test work group connector receives the external device to send And update the second firmware according to the burned file to complete the burning of the read-only memory of serial peripheral devices. Therefore, the firmware inside can be read and converted into a binary file, and the firmware of the read-only memory of the serial peripheral device can be updated offline later.

After the server system entered mass production, the joint test work group connector was removed, and only the serial peripheral device read-only memory was retained, thereby greatly saving the company's costs. At this time, there is no need to jointly test the workgroup connector to update the complex programmable logic device. The firmware of the complex programmable logic device and the serial peripheral device read-only memory binary files are updated offline in the production line. In this way, even if the server system reaches the customer's hands, even if the timing is out of order, the main CPLD firmware can be resurrected to ensure the normal operation of the system.

In summary, the server system of the present invention can ensure the normal operation of the system in the case of CPLD firmware problems. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

The above-mentioned embodiments only exemplarily illustrate the principle and efficacy of the present invention, and are not intended to limit the present invention. Anyone familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the patent application scope of the present invention.

10‧‧‧Server system

11‧‧‧ Complex programmable logic device

12‧‧‧Read-only memory for serial peripherals

111‧‧‧ First firmware

112‧‧‧The first serial peripheral device interface

121‧‧‧ Second firmware

122‧‧‧Second serial peripheral interface

Claims (9)

A server system includes: a complex programmable logic device, including a first firmware and a first serial peripheral device interface; and a serial peripheral device read-only memory, including a second firmware and a first Two serial peripheral device interfaces; wherein the first serial peripheral device interface and the second serial peripheral device interface are electrically connected through a serial peripheral device signal; when the server system is powered on, the complex programmable logic device Scan the first firmware and the second firmware. When the first firmware exists, the complex programmable logic device configures the first firmware as the main firmware and the first firmware leads the boot. When the first firmware does not exist and the second firmware exists, the complex programmable logic device configures the second firmware as the main firmware and leads the boot. The server system according to claim 1, wherein the complex programmable logic device further includes a control module, a configuration module, a logic module, and a logic serial peripheral interface control module. The server system according to claim 2, wherein the complex programmable logic device further includes a selector, the selector and the logic serial peripheral device interface control module, the first serial peripheral device interface and the The logic module is electrically connected, and the logic module controls the selector to determine whether the system is booted by the first firmware configured by the complex programmable logic device or the read-only memory configuration of the serial peripheral device The second firmware dominates the boot. The server system of claim 1, wherein the complex programmable logic device scans the first firmware using a self-downloading mode. According to the server system of claim 4, when the first firmware does not exist, the self-download mode configuration fails, and the complex programmable logic device scans the second firmware using the main serial peripheral device interface configuration mode. The server system according to claim 5, wherein the complex programmable logic device controls and configures the logical serial peripheral device interface control module in the slave mode through the configuration module, and controls the serial peripheral device read-only memory to be Master control mode. According to the server system of claim 1, the first firmware is burned off-line by the production line, and the second firmware is burned off-line by the production line. The server system according to claim 1, wherein the format of the first firmware is a joint engineering design format or a universal bus format. The server system according to claim 1, wherein the format of the second firmware is a binary format.

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