TWI662676B - 具有內埋基板的線路載板及其製作方法與晶片封裝結構 - Google Patents
具有內埋基板的線路載板及其製作方法與晶片封裝結構 Download PDFInfo
- Publication number
- TWI662676B TWI662676B TW107130470A TW107130470A TWI662676B TW I662676 B TWI662676 B TW I662676B TW 107130470 A TW107130470 A TW 107130470A TW 107130470 A TW107130470 A TW 107130470A TW I662676 B TWI662676 B TW I662676B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- patterned
- circuit
- embedded substrate
- bumps
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 90
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 238000004806 packaging method and process Methods 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 334
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 69
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 62
- 229910052802 copper Inorganic materials 0.000 claims description 47
- 239000010949 copper Substances 0.000 claims description 47
- 229910000679 solder Inorganic materials 0.000 claims description 40
- 229910052759 nickel Inorganic materials 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 28
- 239000011889 copper foil Substances 0.000 claims description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims description 22
- 239000012792 core layer Substances 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53233—Copper alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
一種具有內埋基板的線路載板,包括線路結構以及內埋基板。線路結構包括第一介電層、第一圖案化線路層、凹槽以及多個第一凸塊。第一介電層具有彼此相對的第一表面與第二表面。第一圖案化線路層內埋於第一表面。第一凸塊配置於第一表面上。第一凸塊與第一圖案化線路層電性連接。凹槽暴露出第一介電層的一部份。內埋基板配置於凹槽內且包括多個第二凸塊。一種晶片封裝結構,包括上述具有內埋基板的線路載板。
Description
本發明是有關於一種線路載板及其製作方法與封裝結構,且特別是有關於一種具有內埋基板的線路載板及其製作方法與晶片封裝結構。
目前,在多個晶片互連的封裝結構中,常利用中介層來作為架橋元件,以連接不同的晶片並將晶片設置在線路載板上。然而,隨著消費者對於電子產品的小型化以及薄型化的需求,將中介層設置於線路載板上則限制了晶片封裝結構的尺寸大小,尤其限制了整體晶片封裝結構的Z軸高度。因此,如何有效地降低整體晶片封裝結構的Z軸高度,為本領域亟欲解決的問題。
本發明提供一種具有內埋基板的線路載板,可用來整合多種不同晶片、具有較薄的厚度。
本發明提供一種具有內埋基板的線路載板的製作方法,能製作得到可整合多種不同元件且具有較薄的厚度的線路載板。
本發明提供一種晶片封裝結構,具有較薄的封裝厚度以及較小的封裝體積。
本發明的一種具有內埋基板的線路載板包括線路結構以及內埋基板。線路結構包括第一介電層、第一圖案化線路層、凹槽以及多個第一凸塊。第一介電層具有彼此相對的第一表面與第二表面。第一圖案化線路層內埋於第一表面。第一凸塊配置於第一表面上。第一凸塊與第一圖案化線路層電性連接。凹槽暴露出第一介電層的一部份。內埋基板配置於凹槽內且包括多個第二凸塊。
在本發明的一實施例中,上述的線路結構更包括至少二第二圖案化線路層、至少一第二介電層以及至少一第一導電通孔。第二圖案化線路層與第二介電層依序疊置於第一介電層的第二表面上。第一導電通孔貫穿第二介電層。第二圖案化線路層透過第一導電通孔與另一第二圖案化線路層電性連接。
在本發明的一實施例中,上述的線路結構更包括圖案化防焊層。圖案化防焊層至少配置於線路結構相對遠離第一圖案化線路層的底表面上以及第一介電層的第一表面上。圖案化防焊層覆蓋第一介電層、第一圖案化線路層以及內埋基板。
在本發明的一實施例中,上述的圖案化防焊層暴露出第一凸塊以及第二凸塊。
在本發明的一實施例中,上述的第一介電層更具有第三表面。第三表面位於被凹槽暴露出的第一介電層的該部份上。第三表面與第一圖案化線路層的下表面切齊。
在本發明的一實施例中,上述的第一凸塊與第二凸塊齊平。
在本發明的一實施例中,上述的內埋基板更包括至少一介電層、至少一圖案化導電層以及至少一導電通孔。
在本發明的晶片封裝結構包括上述具有內埋基板的線路載板、第一晶片以及第二晶片。第一晶片配置於上述具有內埋基板的線路載板的線路結構上。第一晶片透過第一凸塊與線路結構電性連接,且第一晶片透過第二凸塊與內埋基板電性連接。第二晶片配置於上述具有內埋基板的線路載板的線路結構上。並透過第二凸塊與線路結構電性連接。第二晶片透過第一凸塊與線路結構電性連接,且第二晶片透過第二凸塊與內埋基板電性連接。
在本發明的一實施例中,上述的第一晶片包括多個第一焊球,第二晶片包括多個第二焊球。其中,第一晶片透過第一焊球電性連接至第一圖案化線路層與內埋基板。第二晶片透過第二焊球電性連接至第一圖案化線路層與內埋基板。
本發明的一種具有內埋基板的線路載板的製作方法包括以下步驟。提供線路結構且線路結構包括第一介電層、第一圖案化線路層、凹槽以及多個第一凸塊。第一介電層具有彼此相對的第一表面與第二表面。第一圖案化線路層內埋於第一表面。第一凸塊配置於第一表面上。第一凸塊與第一圖案化線路層電性連接。凹槽暴露出第一介電層的一部份。配置內埋基板於凹槽內。內埋基板包括多個第二凸塊。
在本發明的一實施例中,上述提供線路結構的步驟包括以下步驟。提供核心層且核心層包括核心介電層、至少一離型層以及至少一銅箔層。形成第一圖案化銅層於銅箔層上,且第一圖案化銅層包括多個凹洞。形成鎳層於第一圖案化銅層上,且鎳層覆蓋第一圖案化銅層及凹洞。形成第一凸塊以及第一圖案化線路層於鎳層上。壓合第一介電層於第一圖案化線路層上。第一介電層覆蓋第一圖案化線路層以及第一凸塊。移除核心層、第一圖案化銅層以及鎳層,以暴露出第一凸塊以及第一圖案化線路層。移除部份第一圖案化線路層,以形成凹槽並暴露出第一介電層的部份。
在本發明的一實施例中,上述在壓合第一介電層於第一圖案化線路層上之後,更包括:形成至少二第二圖案化線路層、至少一第二介電層以及至少一第一導電通孔。第二圖案化線路層與第二介電層依序疊置於第一介電層的第二表面上。第一導電通孔貫穿第二介電層。第二圖案化線路層透過第一導電通孔與另一第二圖案化線路層電性連接。
在本發明的一實施例中,上述形成第一圖案化銅層於銅箔層上的步驟包括:形成第一圖案化光阻層於銅箔層上。形成第一圖案化銅層於銅箔層上,且第一圖案化銅層不覆蓋第一圖案化光阻層。移除第一圖案化光阻層。
在本發明的一實施例中,上述形成第一凸塊以及第一圖案化線路層於鎳層上的步驟包括:形成第二圖案化光阻層於鎳層上。形成第二圖案化銅層於鎳層上,其中第二圖案化銅層不覆蓋第二圖案化光阻層且第二圖案化銅層填滿第一圖案化銅層的凹洞。移除第二圖案化光阻層。
在本發明的一實施例中,上述移除核心層、第一圖案化銅層以及鎳層的步驟包括:進行拆板程序,以使離型層與銅箔層彼此分離。以蝕刻方式依序去除銅箔層、第一圖案化銅層以及鎳層。
在本發明的一實施例中,上述在配置內埋基板於凹槽內之後,更包括:形成圖案化防焊層於線路結構相對遠離第一圖案化線路層的底表面上以及第一介電層的第一表面上。使圖案化防焊層覆蓋第一介電層、第一圖案化線路層以及內埋基板。
基於上述,在本發明具有內埋基板的線路載板及其製作方法與晶片封裝結構中,由於線路結構包括凹槽,使得內埋基板可配置於凹槽內,並使得第一晶片與第二晶片可分別透過第一凸塊與線路結構電性連接,且第一晶片與第二晶片可分別透過第二凸塊與內埋基板電性連接。藉此設計,使得本發明具有內埋基板的線路載板可整合多種不同晶片、具有較薄的厚度,並使得本發明的晶片封裝結構具有較薄的封裝厚度以及較小的封裝體積。
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
圖1A至圖1M繪示為本發明一實施例的一種具有內埋基板的線路載板的製作方法的剖面示意圖。請先參照圖1J,在本實施例中,首先,提供線路結構110。
詳細來說,請參照圖1A,提供核心層210,其中核心層210包括核心介電層212、至少一離型層214a、214b(圖1A中示意地繪示為2層)以及至少一銅箔層216a、216b(圖1A中示意地繪示為2層)。
接著,請同時參照圖1B與圖1C,形成第一圖案化銅層220於銅箔層216a上。其中,在本實施例中,形成第一圖案化銅層220於銅箔層216a上的步驟例如是:先形成第一圖案化光阻層R1於銅箔層216a上,再形成第一圖案化銅層220於銅箔層216a上,且第一圖案化銅層220不覆蓋第一圖案化光阻層R1,然後再移除第一圖案化光阻層R1,以得到第一圖案化銅層220。此時,形成的第一圖案化銅層220包括多個凹洞222。需要注意的是,雖然本實施例已揭示形成第一圖案化銅層220於銅箔層216a上的步驟,但本發明不以此為限。
然後,請參照圖1D,形成鎳層230於第一圖案化銅層220上。其中,鎳層230完全覆蓋第一圖案化銅層220及凹洞222且鎳層230的厚度一致。
接著,請同時參照圖1E與圖1F,形成多個第一凸塊112a以及第一圖案化線路層112b於鎳層230上。其中,在本實施例中,形成第一凸塊112a以及第一圖案化線路層112b於鎳層230上的步驟例如是:先形成第二圖案化光阻層R2於鎳層230上,再同時形成第二圖案化銅層112於鎳層230上。其中,第二圖案化銅層112不覆蓋第二圖案化光阻層R2,且第二圖案化銅層112填滿第一圖案化銅層220的凹洞222。而後,移除第二圖案化光阻層R2,以形成第一凸塊112a(圖1G中示意地繪示為10個)以及第一圖案化線路層112b,如圖1G所示。在本實施例中,第一凸塊112a與第一圖案化線路層112b為一體成型。需要注意的是,雖然本實施例已揭示形成第一凸塊112a以及第一圖案化線路層112b於鎳層230上的步驟,但本發明不以此為限。
再者,請再參照圖1G,壓合第一介電層111於第一圖案化線路層112b上。其中,第一介電層111具有彼此相對的第一表面111a與第二表面111b,且第一介電層111覆蓋第一圖案化線路層112b以及第一凸塊112a。然後,可選擇地再形成至少二第二圖案化線路層115(圖1G中示意地繪示為4層)、至少一第二介電層116(圖1G中示意地繪示為3層)以及至少一第一導電通孔117(圖1G中示意地繪示為11個)於第一介電層111上。具體來說,使第二圖案化線路層115與第二介電層116依序疊置於第一介電層111的第二表面111b上。第一導電通孔117貫穿第二介電層116。第二圖案化線路層115透過第一導電通孔117與另一第二圖案化線路層115電性連接。
然後,請參照圖1H,移除核心層210、第一圖案化銅層220以及鎳層230,以暴露出第一凸塊112a以及第一圖案化線路層112b。其中,在本實施例中,移除核心層210、第一圖案化銅層220以及鎳層230的步驟例如是:先進行拆板程序,以使離型層214a與銅箔層216a彼此分離,再以蝕刻方式依序去除銅箔層216a、第一圖案化銅層220以及鎳層230。需要注意的是,雖然本實施例已揭示移除核心層210、第一圖案化銅層220以及鎳層230的步驟,但本發明不以此為限。
而後,請同時參照圖1I與圖1J,移除部份第一圖案化線路層112b,以形成凹槽113並暴露出第一介電層111的部份。其中,在本實施例中,移除部份第一圖案化線路層112b以形成凹槽113的步驟例如是:先將第一介電層111與第一圖案化線路層112b上預定形成凹槽113以外的區域覆蓋一第三圖案化光阻層R3,例如是乾膜,再以蝕刻方式去除未覆蓋第三圖案化光阻層R3的部份第一圖案化線路層112b,以形成凹槽113並暴露出第一介電層111的部份。此時,第一介電層111更具有第三表面111c。其中,第三表面111c位於被凹槽113暴露出的第一介電層111的該部份上,且第三表面111c與第一圖案化線路層112b的下表面112b1切齊。需要注意的是,雖然本實施例已揭示移除部份第一圖案化線路層112b以形成凹槽113的步驟,但本發明不以此為限。此時,已製作完成線路結構110。
接著,請參照圖1K,配置內埋基板120於線路結構110的凹槽113內。其中,內埋基板120包括多個第二凸塊121(圖1K中示意地繪示為6個)、至少一介電層122(圖1K中示意地繪示為3層)、至少一圖案化導電層123(圖1K中示意地繪示為2層)以及至少一導電通孔124(圖1K中示意地繪示為2個)。在本實施例中,例如是利用膠層125將內埋基板120黏著固定在第一介電層111的第三表面111c上,並使內埋基板120的第二凸塊121與線路結構110的第一凸塊112a齊平。此處,內埋基板的材質可以是有機材料,例如是感光型聚醯亞胺(polyimide)、其他可感光成像介電材(photo-imagiable dielectric, PID)或其他適合的有機材料,但不以此為限。在一些其他實施例中,內埋基板的材質也可以是無機材料,例如是玻璃、二氧化矽、其他陶瓷材料、矽晶片(silicon chip)或其他半導體,但不以此為限。
然後,請同時參照圖1L與圖1M,形成圖案化防焊層118a於線路結構110相對遠離第一圖案化線路層112a的底表面116a上以及第一介電層111的第一表面111a上。於是,先將防焊層118配置於第一介電層111的第一表面111a上,將防焊層119配置於線路結構110相對遠離第一圖案化線路層112b的底表面116a上。也就是使防焊層118覆蓋第一介電層111、第一圖案化線路層112b以及內埋基板120,並使防焊層119覆蓋最遠離內層線路結構110的第二圖案化線路層115以及第二介電層116。接著,對防焊層118進行薄化製程,以形成圖案化防焊層118a並暴露出線路結構110的第一凸塊112a以及內埋基板120的第二凸塊121。對防焊層119進行圖案化製程,以形成圖案化防焊層119a並暴露出最遠離內層線路結構110的部份第二圖案化線路層115。此處,防焊層118與防焊層119的形成方式例如是噴印法,但不以此為限。此時,已製作完成具有內埋基板的線路載板100。
基於上述,在本實施例中,具有內埋基板的線路載板100包括線路結構110以及內埋基板120。其中,線路結構110包括第一介電層111、第一圖案化線路層112b、凹槽113以及多個第一凸塊112a。第一介電層111具有彼此相對的第一表面111a與第二表面111b。第一圖案化線路層112b內埋於第一表面111a。第一凸塊112a配置於第一表面111a上。第一凸塊112a與第一圖案化線路層112b電性連接。凹槽113暴露出第一介電層112b的一部份。內埋基板120配置於凹槽113內,且內埋基板120包括第二凸塊121。
在此必須說明的是,下述實施例沿用前述實施例的元件標號與部份內容,其中採用相同的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部份的說明可參考前述實施例,下述實施例不再重複贅述。
圖2繪示為本發明一實施例的一種晶片封裝結構的剖面示意圖。
本實施例中,晶片封裝結構包括具有內埋基板的線路載板100、第一晶片310以及第二晶片320。其中,第一晶片310配置於具有內埋基板的線路載板100的線路結構110上,第二晶片320配置於具有內埋基板的線路載板100的線路結構110上。第一晶片310透過第一凸塊112a與線路結構110電性連接,且第一晶片310透過第二凸塊121與內埋基板120電性連接。第二晶片320透過第一凸塊112a與線路結構110電性連接,且第二晶片320透過第二凸塊121與內埋基板120電性連接。
詳細來說,第一晶片310包括多個第一焊球312(圖2示意地繪示為8個)且第二晶片320包括多個第二焊球322(圖2示意地繪示為8個)。第一晶片310可透過第一焊球312電性連接至第一圖案化線路層112b與內埋基板120,且第二晶片320可透過第二焊球322電性連接至第一圖案化線路層112b與內埋基板120。
綜上所述,在本發明具有內埋基板的線路載板及其製作方法與晶片封裝結構中,由於線路結構包括凹槽,使得內埋基板可配置於凹槽內,並使得第一晶片與第二晶片可分別透過第一凸塊與線路結構電性連接,且第一晶片與第二晶片可分別透過第二凸塊與內埋基板電性連接。藉此設計,使得本發明具有內埋基板的線路載板可整合多種不同晶片、具有較薄的厚度,並使得本發明的晶片封裝結構具有較薄的封裝厚度以及較小的封裝體積。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10‧‧‧晶片封裝結構
100‧‧‧具有內埋基板的線路載板
110‧‧‧線路結構
111‧‧‧第一介電層
111a‧‧‧第一表面
111b‧‧‧第二表面
111c‧‧‧第三表面
112b‧‧‧第一圖案化線路層
112b1‧‧‧下表面
113‧‧‧凹槽
112a‧‧‧第一凸塊
115‧‧‧第二圖案化線路層
116‧‧‧第二介電層
116a‧‧‧底表面
117‧‧‧第一導電通孔
118、119‧‧‧防焊層
118a、119a‧‧‧圖案化防焊層
120‧‧‧內埋基板
121‧‧‧第二凸塊
122‧‧‧介電層
123‧‧‧圖案化導電層
124‧‧‧導電通孔
125‧‧‧膠層
210‧‧‧核心層
212‧‧‧核心介電層
214a、214b‧‧‧離型層
216a、216b‧‧‧銅箔層
220‧‧‧第一圖案化銅層
222‧‧‧凹洞
230‧‧‧鎳層
112‧‧‧第二圖案化銅層
310‧‧‧第一晶片
312‧‧‧第一焊球
320‧‧‧第二晶片
322‧‧‧第二焊球
R1‧‧‧第一圖案化光阻層
R2‧‧‧第二圖案化光阻層
R3‧‧‧第三圖案化光阻層
圖1A至圖1M繪示為本發明一實施例的一種具有內埋基板的線路載板的製作方法的剖面示意圖。 圖2繪示為本發明一實施例的一種晶片封裝結構的剖面示意圖。
Claims (20)
- 一種具有內埋基板的線路載板,包括: 一線路結構,包括一第一介電層、一第一圖案化線路層、一凹槽以及多個第一凸塊,其中該第一介電層具有彼此相對的一第一表面與一第二表面,該第一圖案化線路層內埋於該第一表面,該些第一凸塊配置於該第一表面上,該些第一凸塊與該第一圖案化線路層電性連接,且該凹槽暴露出該第一介電層的一部份;以及 一內埋基板,配置於該凹槽內,且包括多個第二凸塊。
- 如申請專利範圍第1項所述的具有內埋基板的線路載板,其中該線路結構更包括至少二第二圖案化線路層、至少一第二介電層以及至少一第一導電通孔,該第二圖案化線路層與該第二介電層依序疊置於該第一介電層的該第二表面上,該第一導電通孔貫穿該第二介電層,且該第二圖案化線路層透過該第一導電通孔與另一該第二圖案化線路層電性連接。
- 如申請專利範圍第1項所述的具有內埋基板的線路載板,其中該線路結構更包括一圖案化防焊層,該圖案化防焊層至少配置於該線路結構相對遠離該第一圖案化線路層的一底表面上以及該第一介電層的該第一表面上,且該圖案化防焊層覆蓋該第一介電層、該第一圖案化線路層以及該內埋基板。
- 如申請專利範圍第3項所述的具有內埋基板的線路載板,其中該圖案化防焊層暴露出該些第一凸塊以及該些第二凸塊。
- 如申請專利範圍第1項所述的具有內埋基板的線路載板,其中該第一介電層更具有一第三表面,該第三表面位於被該凹槽暴露出的該第一介電層的該部份上,且該第三表面與該第一圖案化線路層的一下表面切齊。
- 如申請專利範圍第1項所述的具有內埋基板的線路載板,其中該些第一凸塊與該些第二凸塊齊平。
- 如申請專利範圍第1項所述的具有內埋基板的線路載板,其中該內埋基板更包括至少一介電層、至少一圖案化導電層以及至少一導電通孔。
- 一種晶片封裝結構,包括:: 如申請專利範圍第1~7項中任一項所述的具有內埋基板的線路載板; 一第一晶片,配置於該具有內埋基板的線路載板的該線路結構上,其中該第一晶片透過該些第一凸塊與該線路結構電性連接,且該第一晶片透過該些第二凸塊與該內埋基板電性連接;以及 一第二晶片,配置於該具有內埋基板的線路載板的該線路結構上,其中該第二晶片透過該些第一凸塊與該線路結構電性連接,且該第二晶片透過該些第二凸塊與該內埋基板電性連接。
- 如申請專利範圍第8項所述的晶片封裝結構,其中該第一晶片包括多個第一焊球,該第二晶片包括多個第二焊球,其中該第一晶片透過該些第一焊球電性連接至該第一圖案化線路層與該內埋基板,且該第二晶片透過該些第二焊球電性連接至該第一圖案化線路層與該內埋基板。
- 一種具有內埋基板的線路載板的製作方法,包括: 提供一線路結構,該線路結構包括一第一介電層、一第一圖案化線路層、一凹槽以及多個第一凸塊,其中該第一介電層具有彼此相對的一第一表面與一第二表面,該第一圖案化線路層內埋於該第一表面,該些第一凸塊配置於該第一表面上,該些第一凸塊與該第一圖案化線路層電性連接,且該凹槽暴露出該第一介電層的一部份;以及 配置一內埋基板於該凹槽內,其中該內埋基板包括多個第二凸塊。
- 如申請專利範圍第10項所述的具有內埋基板的線路載板的製作方法,其中提供該線路結構的步驟包括: 提供一核心層,該核心層包括一核心介電層、至少一離型層以及至少一銅箔層; 形成一第一圖案化銅層於該銅箔層上,且該第一圖案化銅層包括多個凹洞; 形成一鎳層於該第一圖案化銅層上,且該鎳層覆蓋該第一圖案化銅層及該些凹洞; 形成該些第一凸塊以及該第一圖案化線路層於該鎳層上; 壓合該第一介電層於該第一圖案化線路層上,其中該第一介電層覆蓋該第一圖案化線路層以及該些第一凸塊; 移除部份該核心層、該第一圖案化銅層以及該鎳層,以暴露出該些第一凸塊以及該第一圖案化線路層;以及 移除部份該第一圖案化線路層,以形成該凹槽並暴露出該第一介電層的一部份。
- 如申請專利範圍第11項所述的具有內埋基板的線路載板的製作方法,其中在壓合該第一介電層於該第一圖案化線路層上之後,更包括: 形成至少二第二圖案化線路層、至少一第二介電層以及至少一第一導電通孔,其中該第二圖案化線路層與該第二介電層依序疊置於該第一介電層的該第二表面上,該第一導電通孔貫穿該第二介電層,且該第二圖案化線路層透過該第一導電通孔與另一該第二圖案化線路層電性連接。
- 如申請專利範圍第11項所述的具有內埋基板的線路載板的製作方法,其中形成該第一圖案化銅層於該銅箔層上的步驟包括: 形成一第一圖案化光阻層於該銅箔層上; 形成一第一圖案化銅層於該銅箔層上,且該第一圖案化銅層不覆蓋該第一圖案化光阻層;以及 移除該第一圖案化光阻層。
- 如申請專利範圍第11項所述的具有內埋基板的線路載板的製作方法,其中形成該些第一凸塊以及該第一圖案化線路層於該鎳層上的步驟包括: 形成一第二圖案化光阻層於該鎳層上; 形成一第二圖案化銅層於該鎳層上,其中該第二圖案化銅層不覆蓋該第二圖案化光阻層且該第二圖案化銅層填滿該第一圖案化銅層的該些凹洞;以及 移除該第二圖案化光阻層。
- 如申請專利範圍第11項所述的具有內埋基板的線路載板的製作方法,其中移除該核心層、該第一圖案化銅層以及該鎳層的步驟包括: 進行一拆板程序,以使該離型層與該銅箔層彼此分離;以及 以蝕刻方式依序去除該銅箔層、該第一圖案化銅層以及該鎳層。
- 如申請專利範圍第10項所述的具有內埋基板的線路載板的製作方法,其中該第一介電層更具有一第三表面,該第三表面位於被該凹槽暴露出的該第一介電層的該部份上,且該第三表面與該第一圖案化線路層的一下表面切齊。
- 如申請專利範圍第10項所述的具有內埋基板的線路載板的製作方法,其中該些第一凸塊與該些第二凸塊齊平。
- 如申請專利範圍第10項所述的具有內埋基板的線路載板的製作方法,其中該內埋基板更包括至少一介電層、至少一圖案化導電層以及至少一導電通孔。
- 如申請專利範圍第10項所述的具有內埋基板的線路載板的製作方法,其中在配置該內埋基板於該凹槽內之後,更包括: 形成一圖案化防焊層於該線路結構相對遠離該第一圖案化線路層的一底表面上以及該第一介電層的該第一表面上,使該圖案化防焊層覆蓋該第一介電層、該第一圖案化線路層以及該內埋基板。
- 如申請專利範圍第19項所述的具有內埋基板的線路載板的製作方法,其中該圖案化防焊層暴露出該些第一凸塊以及該些第二凸塊。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW107130470A TWI662676B (zh) | 2018-08-31 | 2018-08-31 | 具有內埋基板的線路載板及其製作方法與晶片封裝結構 |
US16/162,396 US10964634B2 (en) | 2018-08-31 | 2018-10-17 | Method of manufacturing circuit carrier with embedded semiconductor substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW107130470A TWI662676B (zh) | 2018-08-31 | 2018-08-31 | 具有內埋基板的線路載板及其製作方法與晶片封裝結構 |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI662676B true TWI662676B (zh) | 2019-06-11 |
TW202011557A TW202011557A (zh) | 2020-03-16 |
Family
ID=67764564
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW107130470A TWI662676B (zh) | 2018-08-31 | 2018-08-31 | 具有內埋基板的線路載板及其製作方法與晶片封裝結構 |
Country Status (2)
Country | Link |
---|---|
US (1) | US10964634B2 (zh) |
TW (1) | TWI662676B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI732568B (zh) * | 2020-05-28 | 2021-07-01 | 欣興電子股份有限公司 | 內埋元件的基板結構及其製造方法 |
US11410933B2 (en) | 2020-10-06 | 2022-08-09 | Unimicron Technology Corp. | Package structure and manufacturing method thereof |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11482481B2 (en) * | 2019-09-27 | 2022-10-25 | Intel Corporation | Semiconductor device and system |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20160066423A1 (en) * | 2014-09-01 | 2016-03-03 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing the same |
US20160133552A1 (en) * | 2012-12-20 | 2016-05-12 | Intel Corporation | High density organic bridge device and method |
US20170330837A1 (en) * | 2014-12-16 | 2017-11-16 | At & S Austria Technologie & Systemtechnik Aktiengesellschaft | Contacting Embedded Electronic Component Via Wiring Structure in a Component Carrier's Surface Portion With Homogeneous Ablation Properties |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7863735B1 (en) * | 2009-08-07 | 2011-01-04 | Stats Chippac Ltd. | Integrated circuit packaging system with a tiered substrate package and method of manufacture thereof |
US9385095B2 (en) * | 2010-02-26 | 2016-07-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D semiconductor package interposer with die cavity |
TWI492680B (zh) * | 2011-08-05 | 2015-07-11 | Unimicron Technology Corp | 嵌埋有中介層之封裝基板及其製法 |
US10026671B2 (en) * | 2014-02-14 | 2018-07-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design for semiconductor packages and method of forming same |
US9704735B2 (en) * | 2014-08-19 | 2017-07-11 | Intel Corporation | Dual side solder resist layers for coreless packages and packages with an embedded interconnect bridge and their methods of fabrication |
US9542522B2 (en) | 2014-09-19 | 2017-01-10 | Intel Corporation | Interconnect routing configurations and associated techniques |
US9941226B2 (en) * | 2014-12-15 | 2018-04-10 | Industrial Technology Research Institute | Integrated millimeter-wave chip package |
US9443824B1 (en) | 2015-03-30 | 2016-09-13 | Qualcomm Incorporated | Cavity bridge connection for die split architecture |
WO2017111790A1 (en) | 2015-12-23 | 2017-06-29 | Manusharow Mathew J | Improving size and efficiency of dies |
CN108780785A (zh) * | 2016-03-30 | 2018-11-09 | 英特尔公司 | 混合微电子基底 |
US10943869B2 (en) * | 2017-06-09 | 2021-03-09 | Apple Inc. | High density interconnection using fanout interposer chiplet |
US10453802B2 (en) * | 2017-08-30 | 2019-10-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure, semiconductor device and method for manufacturing the same |
KR101963292B1 (ko) * | 2017-10-31 | 2019-03-28 | 삼성전기주식회사 | 팬-아웃 반도체 패키지 |
-
2018
- 2018-08-31 TW TW107130470A patent/TWI662676B/zh active
- 2018-10-17 US US16/162,396 patent/US10964634B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20160133552A1 (en) * | 2012-12-20 | 2016-05-12 | Intel Corporation | High density organic bridge device and method |
US20160066423A1 (en) * | 2014-09-01 | 2016-03-03 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing the same |
US20170330837A1 (en) * | 2014-12-16 | 2017-11-16 | At & S Austria Technologie & Systemtechnik Aktiengesellschaft | Contacting Embedded Electronic Component Via Wiring Structure in a Component Carrier's Surface Portion With Homogeneous Ablation Properties |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI732568B (zh) * | 2020-05-28 | 2021-07-01 | 欣興電子股份有限公司 | 內埋元件的基板結構及其製造方法 |
CN113745188A (zh) * | 2020-05-28 | 2021-12-03 | 欣兴电子股份有限公司 | 内埋组件的基板结构及其制造方法 |
US11410933B2 (en) | 2020-10-06 | 2022-08-09 | Unimicron Technology Corp. | Package structure and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
US20200075469A1 (en) | 2020-03-05 |
US10964634B2 (en) | 2021-03-30 |
TW202011557A (zh) | 2020-03-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR102440119B1 (ko) | 반도체 패키지 및 그 제조방법 | |
TWI425896B (zh) | 具有內埋式導電線路之電路板及其製造方法 | |
CN110896066B (zh) | 具有内埋基板的线路载板及其制作方法与芯片封装结构 | |
TWI649845B (zh) | 半導體封裝結構及其製造方法 | |
TWI559488B (zh) | 封裝結構及其製法 | |
CN102956511B (zh) | 半导体封装结构的制作方法 | |
TWI571979B (zh) | 整合式被動模組、半導體裝置及其製作方法 | |
JP5188426B2 (ja) | 半導体装置及びその製造方法、電子装置 | |
US9324580B2 (en) | Process for fabricating a circuit substrate | |
US8847369B2 (en) | Packaging structures and methods for semiconductor devices | |
TW201312713A (zh) | 半導體裝置、垂直堆疊有該半導體裝置之半導體模組構造及其製造方法 | |
TWI662676B (zh) | 具有內埋基板的線路載板及其製作方法與晶片封裝結構 | |
TW201541586A (zh) | 晶片堆疊封裝體及其製造方法 | |
CN107622953B (zh) | 封装堆迭结构的制法 | |
TWI692802B (zh) | 線路載板結構及其製作方法與晶片封裝結構 | |
US9066458B2 (en) | Fabricating method of circuit board and circuit board | |
US9775246B2 (en) | Circuit board and manufacturing method thereof | |
JP5581830B2 (ja) | 部品内蔵基板の製造方法及び部品内蔵基板 | |
TWI768874B (zh) | 封裝結構及其製作方法 | |
CN113496983A (zh) | 半导体封装载板及其制法与半导体封装制程 | |
TWM508791U (zh) | 封裝基板與晶片封裝結構 | |
KR101441466B1 (ko) | 초박형 패키지기판 및 제조방법 | |
US9955578B2 (en) | Circuit structure | |
TWM499645U (zh) | 整合式被動模組及半導體裝置 | |
KR20220133636A (ko) | 반도체 패키지의 제조 방법 |