TWI651704B - Panel driving circuit and panel driving method - Google Patents

Abstract

The panel driving circuit includes a first switching unit, a second switching unit, and a first capacitor. The input end of the first switching unit is configured to receive a start signal, and the control end is configured to receive the first clock signal. The first switching unit is turned on according to the first clock signal to output an activation signal at the output end. The input end of the second switching unit is configured to receive a driving voltage, and the control end is electrically connected to the output end of the first switching unit at the first node to receive an activation signal. The first capacitor has a first end and a second end, wherein the first end is for receiving the second clock signal, and the second end is electrically connected to the first node. When the second switching unit is turned on according to the startup signal, the second clock signal generates a coupling voltage through the first capacitor to the first node, and the driving voltage is output through the second switching unit to drive the panel.

Description

Panel drive circuit and panel drive method

The present disclosure relates to a panel driving circuit, and more particularly to a panel driving circuit and a panel driving method capable of enhancing a driving signal output capability.

In general, the panel requires driving of the driving circuit to generate an image, and the driving signal generated by the driving circuit enables the pixel electrode to emit light according to the data signal.

However, the output of the panel driving circuit is affected by the leakage current in the driving circuit, which makes it difficult for the output driving signal to maintain a stable voltage during an image frame time, and the image brightness is unstable in the same image frame. phenomenon.

In order to improve the instability of the aforementioned driving signal, a panel driving circuit is proposed in an embodiment of the disclosed document. The panel driving circuit includes a first switching unit, a second switching unit, and a first capacitor. The first switch unit has an input end, an output end and a control end, wherein the input end is used for receiving The start signal is received, and the control terminal is configured to receive the first clock signal. The first switching unit is turned on according to the first clock signal to output an activation signal at the output end. The second switching unit has an input end, an output end and a control end, wherein the input end of the second switch unit is configured to receive a driving voltage, and the control end of the second switching unit is electrically connected to the output end of the first switching unit at the first node To receive the start signal. The first capacitor has a first end and a second end, wherein the first end is for receiving the second clock signal, and the second end is electrically connected to the first node. When the second switching unit is turned on according to the startup signal, the second clock signal generates a coupling voltage through the first capacitor to the first node, and the driving voltage is output through the second switching unit to drive the panel.

Furthermore, another embodiment of the present disclosure proposes a panel driving method. The panel driving method is used for the panel driving circuit. The panel driving circuit includes a first switching unit, a second switching unit, and a first capacitor, wherein the first switching unit and the second switching unit are electrically connected to the first node, and one end of the first capacitor is electrically connected to the first node. The panel driving method includes: providing a start signal having a first potential to the first switching unit and providing a first clock signal to turn on the first switching unit during the first time period, and turning the start signal to the first node to enable the first The node has a first potential to turn on the second switching unit, the second switching unit turns on the driving voltage to output to the panel; in the second period, provides the second clock signal to the first capacitor, and the second clock signal transmits the first capacitor A coupling voltage is generated to the first node to boost the first node to a boosting potential.

Through the panel driving circuit and the panel driving method disclosed in the disclosure document, the panel driving circuit can output a stable driving signal to make the panel The brightness of the image is more stable.

100, 300, 400, 500, 600‧‧‧ panel drive circuit

200‧‧‧ display panel

C1, C2, C3‧‧‧ capacitors

CK1‧‧‧ first clock signal

CK2‧‧‧ second clock signal

EM‧‧‧ drive signal

M1~M10‧‧‧Switch unit

P, Q‧‧‧ nodes

RST‧‧‧Reset circuit

STV‧‧‧ start signal

T1~T5‧‧‧

T51~T56‧‧‧ time interval

VG1‧‧‧ drive voltage

VG2‧‧‧Reset voltage

1 is a circuit diagram of a panel driving circuit of one embodiment of the present disclosure.

FIG. 2 is a signal timing waveform diagram of an embodiment of the present disclosure.

Figure 3 is a circuit diagram of a panel driving circuit of one embodiment of the present disclosure.

Figure 4 is a circuit diagram of a panel driving circuit of one embodiment of the present disclosure.

Figure 5 is a circuit diagram of a panel driving circuit of one embodiment of the present disclosure.

Figure 6 is a circuit diagram of a panel driving circuit of one embodiment of the present disclosure.

The following detailed description of the embodiments of the present invention is intended to be illustrative of the invention, and is not intended to limit the invention, and the description of structural operation is not intended to limit the order of execution, any The means for re-combining the components, resulting in equal functionality, are within the scope of the present disclosure.

The terms used in the entire specification and the scope of application for patents, unless otherwise specified, usually have each term used in this field. In the content disclosed herein, and the ordinary meaning in the special content. Certain terms used to describe the disclosure are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in the description of the disclosure.

Please refer to FIG. 1 . FIG. 1 is a circuit diagram of a panel driving circuit 100 according to an embodiment of the disclosure. According to this embodiment, the panel driving circuit 100 is configured to generate a driving signal EM to drive a display panel 200. The panel driving circuit 100 includes switching units M1 to M3, capacitors C1 to C2, and a reset circuit RST. The reset circuit RST includes switch units M4 to M8. In this example, the switching units M1 to M8 are N-type thin film transistors (N-type TFTs) which are turned on according to a high potential voltage and turned off according to a low potential voltage. In another embodiment, the switch units M1 M M8 can be P-type thin film transistors (P-type TFTs), and the like is turned on according to a low potential voltage, and is turned off according to a high potential voltage. . For convenience of explanation, only the N-type transistors of each of the switch units will be exemplified below.

In an embodiment, the driving signal EM is used to control the lighting stage of the display panel 200. In some practical applications, the display panel 200 may be an OLED display panel in which a plurality of pixels are respectively composed of a plurality of organic light-emitting diodes (OLEDs), and the driving signal EM is used to control each pixel in the display panel 200. The light-emitting state of the organic light-emitting diode. In some practical applications, the display panel 200 may be a liquid crystal display panel including a backlight module (not shown), and the driving signal EM is used to control the lighting state of the backlight module in the display panel 200.

In an embodiment, when the driving signal EM generated by the panel driving circuit 100 is at a high level, the organic light emitting diode or the backlight module in the display panel 200 enters a light emitting stage, and on the other hand, the panel driving circuit 100 When the generated driving signal EM is at a low level, the backlight module or the organic light emitting diode in the display panel 200 stops emitting light.

In general, the driving process of the display panel 200 may include a reset phase, a data writing phase, and/or a compensation phase in addition to the above-mentioned lighting phase, but the disclosure is not limited thereto. In general, the duration of the illumination phase is relatively long compared to the stages of reset, data writing or compensation. Therefore, the panel driving circuit 100 needs to provide the driving signal EM having a stable voltage level for a long time. If the drive signal EM decays or changes over time, it may cause the brightness of the display to drop or flicker.

The switch unit M1 is configured to receive the enable signal STV and is turned on according to the first clock signal CK1 to output the start signal STV at its output. The switching unit M2 is configured to receive the driving voltage VG1. In the example in which each switching unit is an N-type transistor, the driving voltage VG1 is a high potential constant voltage. The control terminal of the switching unit M2 is connected to the output terminal of the switching unit M1 at the node Q, and thus the switching unit M2 can be turned on according to the potential of the node Q to output the driving voltage VG1 as the driving signal EM.

The input end of the switch unit M3 receives the first clock signal CK1, the control end is connected to the output end of the switch unit M1 (ie, the connection node Q), and the output end thereof is connected to the capacitor C2 at the node P, and is connected to the reset circuit. The control terminal of the switching unit M4 of the RST. Wherein, when the switch unit M3 is turned on, the first clock signal CK1 will be sent to the control end of the switch unit M4.

The input end of the switch unit M4 is connected to the output end of the switch unit M7, and the output end of the switch unit M4 is connected to the output end of the switch unit M8 and the control end of the switch units M5, M6. The switch unit M7 is configured to be turned on according to the second clock signal CK2 to receive the driving voltage VG1. When the driving voltage VG1 passes through the switching units M7 and M4, the switching units M5 and M6 are further turned on.

The output of the switching unit M5 is connected to the node Q, and the output of the switching unit M6 is connected to the output of the switching unit M2. The input terminals of the switch units M5 and M6 receive the reset voltage VG2, and the reset voltage VG2 is a constant voltage of the low voltage level. Therefore, when the switching units M5, M6 are turned on, the reset voltage VG2 is turned on to the output terminals of the node Q and the switching unit M2 to pull the potentials of the output terminals of the node Q and the switching unit M2 low.

One end of the capacitor C1 receives the second clock signal CK2, and the other end is connected to the node Q. One end of the capacitor C2 also receives the second clock signal CK2, and the other end is connected to the node P. The operation of the panel driving circuit 100 will be described in detail with reference to FIG.

FIG. 2 is a timing waveform diagram of signals for the panel driving circuit 100 in one embodiment of the disclosed document. In the first period T1 of FIG. 2, the enable signal STV is at a high voltage level, and the first clock signal CK1 is also at a high voltage level. Therefore, the switching unit M1 is turned on to transmit the enable signal STV to the node Q, the node Q has the potential of the enable signal STV, and further turns on the switch unit M2, and the drive voltage VG1 is driven to be output by the switch unit M2 as the drive signal EM. Panel 200. In an embodiment, the driving signal EM is used to drive the light emitting unit in the display panel 200, such as an organic light emitting diode or a backlight module of each pixel, but the disclosure is not limited thereto.

At the same time, the switching unit M3 and the switching unit M8 of the reset circuit RST are also turned on due to the potential of the output terminal of the switching unit M1. Wherein, when the switching unit M8 is turned on, the low potential reset voltage VG2 will pass through the switching unit M8 to turn off the switching units M5, M6. Therefore, the reset voltage VG2 cannot be turned on to the output of the node Q and the switching unit M2.

Then, in the second time period T2, the first clock signal CK1 is at a low voltage level, and the switching unit M1 is turned off, so that the potential of the node Q is in a floating state. The second clock signal CK2 is at a high voltage level, so the second clock signal CK2 generates a coupling voltage to the node Q through the capacitor C1, so that the potential of the node Q is raised to the boosting potential. The boosting potential of the node Q is a superimposed potential of both the potential supplied by the enable signal STV at the first time period T1 and the coupled voltage of the second clock signal CK2 at the second time period T2, as shown in FIG.

The potential of the node Q is used to control the switching state of the switching unit M2. Generally, if the potential of the node Q is in a floating state (ie, the constant voltage source continuously maintains the potential of the node Q), the node Q may be caused by the leakage current of the transistor. The potential drop, for example, the leakage current may pass through the switching unit M5 connected to the node Q. In this embodiment, the potential of the node Q is raised by the second clock signal CK2 during the second time period T2, so that the potential of the node Q is continuously maintained above the threshold voltage of the switching unit M2, and the switching unit M2 is continuously turned on. .

During the second time period T2, because the output of the switch unit M1 (ie, the potential of the node Q) is a high voltage level, and the switching unit M3 is still in an on state during this period, so the node P will receive the first clock signal CK1 of the low voltage level.

In addition, in the second time period T2, the switching unit M7 is in an on state, the switching unit M4 is in an off state, and the switching units M5, M6 of the reset circuit RST are still maintained in an off state.

In the third time period T3, the first clock signal CK1 returns to the high voltage level, and the switching unit M1 is turned on. Because the start signal STV at this time is at a low voltage level, the switch unit M1 outputs a low voltage level to the node Q while turning off the switch units M3, M8, and M2.

During the fourth time period T4, the second clock signal CK2 is at a high voltage level, and the switch unit M3 is in an off state, so the second clock signal CK2 can generate a coupling voltage to the node P through the capacitor C2 to further switch Unit M4 is turned on. At the same time, the switching unit M7 is also turned on by the second clock signal CK2, so the driving voltage VG1 of the high voltage level will pass through the switching units M7 and M4 to further turn on the switching units M5 and M6. When the switching units M5 and M6 are turned on, the reset voltage VG2 is turned on to the output terminals of the node Q and the switching unit M2 to pull the potentials of the output terminals of the node Q and the switching unit M2 to the potential of the reset voltage VG2.

It can be seen from the above that the second clock signal CK2 is coupled to the node Q (the second period T2) through the capacitor C1, and the potential of the node Q can be raised to continuously maintain the complete conduction of the switching unit M2, thereby enhancing the output capability of the driving signal EM. Further, please refer to the fifth time period T5 in FIG. 2 . In an embodiment, the fifth time period T5 corresponds to the light emitting stage of the display panel 200. The board driving circuit 100 is configured to output a driving signal EM that is stable at a high voltage level in the fifth period T5.

The operation state of the panel driving circuit 100 in the time interval T51 in the fifth period T5 is similar to the first period T1 described above, the startup signal STV is at the high voltage level, and the first clock signal CK1 is also at the high voltage level. Therefore, the switching unit M1 is turned on to transmit the enable signal STV to the node Q, the node Q has the potential of the enable signal STV, and further turns on the switch unit M2, and the drive voltage VG1 is driven to be output by the switch unit M2 as the drive signal EM. Panel 200.

The operation state of the panel driving circuit 100 in the time interval T52 in the fifth period T5 is similar to the second period T2 described above, the first clock signal CK1 is at the low voltage level, and the switching unit M1 is turned off, so that the potential of the node Q is Floating. The second clock signal CK2 is at a high voltage level, so the second clock signal CK2 generates a coupling voltage to the node Q through the capacitor C1, so that the potential of the node Q is raised to the boosting potential.

The operation state of the panel driving circuit 100 in the time interval T53 in the fifth time period T5 is different from the aforementioned third time period T3. At this time, the start signal STV is at the high voltage level, and when the first clock signal CK1 is also high. When the voltage level turns on the switching unit M1, the node Q has the potential of the enable signal STV.

The operation state of the panel driving circuit 100 in the time interval T54 in the fifth time period T5 is similar to the aforementioned second time period T2, the first clock signal CK1 is at the low voltage level, the switching unit M1 is turned off, and the potential of the node Q is made. Floating. The second clock signal CK2 is at a high voltage level Bit, so the second clock signal CK2 generates a coupling voltage to the node Q through the capacitor C1, and again raises the potential of the node Q to the boosting potential. And so on, in the time interval T56 in the fifth time period T5, the potential of the node Q is again raised to the boosting potential.

In the fifth time period T5, the start signal STV is at the high voltage level, so in the fifth time period T5, whenever the second clock signal CK2 is at the high voltage level (for example, the time intervals T52, T54 and T56), The coupling voltage can be generated through the capacitor C1 to continuously raise the potential of the node Q, so that the start unit M2 can maintain stable conduction during the time of the image frame, so that the driving signal EM can stably output.

In an embodiment of the present disclosure, the switch unit M7 can also be removed to simplify the circuit, as shown in FIG. FIG. 3 is a circuit diagram of the panel driving circuit 300 of one embodiment of the disclosed document. In FIG. 3, the panel driving circuit 300 is substantially the same as the panel driving circuit 100. However, the switching unit M7 is removed, and the switching unit M4 directly receives the second clock signal CK2. That is, when the switching unit M4 is turned on according to the potential of the node P, if the second clock signal CK2 is at the high voltage level, the switching unit M5 can be turned on by the switching unit M4. The signal timing waveform of FIG. 2 is also applicable to the panel driving circuit 300. It should be particularly noted that in the fourth period T4, the switching unit M3 is first turned off by the enable signal STV, and the second clock signal of the high voltage level is turned off. CK2 raises the potential of the node P via the capacitor C2, whereby the potential of the node P turns on the switching unit M4, and at this time, the second clock signal CK2 of the high voltage level is turned on to the switching units M5 and M6, and the potential and the switch of the node Q are turned on. The potential at the output of unit M2 is pulled low.

In another embodiment of the present disclosure, the switch unit can also be added between the node Q of the panel driving circuit 100 and the output end of the switch unit M1. FIG. 4 is a circuit diagram of a panel driving circuit 400 according to an embodiment of the present disclosure. The panel driving circuit 400 further has a switching unit M9 compared to the panel driving circuit 100. The switch unit M9 is disposed between the node Q and the output end of the switch unit M1, and receives the first clock signal CK1. When the first clock signal CK1 is at the high voltage level, the switching units M1, M9 are turned on, so that the enable signal STV can be sent to the node Q. When the first clock signal CK1 is at the low voltage level, the switch unit M9 is turned off, thereby preventing the current of the node Q from flowing back and generating a leakage phenomenon. The signal timing waveform of Fig. 2 is also applicable to the panel driving circuit 400.

In still another embodiment of the present disclosure, the switch unit M9 of the panel driving circuit 400 can be set in the form of a unidirectional switch. FIG. 5 illustrates the panel driving circuit 500 of one embodiment of the disclosed document. The circuit diagram is shown. In the panel drive circuit 500, the switch unit M10 replaces the switch unit M9 in the panel drive circuit 400. The control end of the switch unit M10 is connected to its input end. When the switch unit M1 is turned on, if the start signal STV is at the high voltage level, the switch unit M10 is turned on. When the start signal STV is at the low voltage level, the switching unit M10 is turned off, so the current of the node Q does not reflow and the leakage phenomenon occurs.

It should be understood that the one-way switch unit M10 can also be replaced by a diode (not shown). The positive terminal of the diode is connected to the output terminal of the switch unit M1, and the negative terminal of the diode is connected to the node Q. Therefore, when the diode receives the forward bias, it turns on, and the potential of the node Q goes to the diode. Said reverse bias, so the diode is not conducting, thus preventing possible leakage.

In still another embodiment of the present disclosure, a capacitor may be added between the output end of the switch unit M2 and the node Q in the panel driving circuit 100 to further assist the potential of the node Q, as shown in FIG. A circuit diagram of the panel driving circuit 600 of an embodiment is shown. In Fig. 6, the panel driving circuit 600 has a capacitor C3. Both ends of the capacitor C3 are respectively connected to the output terminal of the switch unit M2 and the node Q. When the switching unit M2 is turned on, the driving voltage VG1 is output as the driving signal EM. At the same time, the voltage of the driving signal EM is coupled to the node Q through the capacitor C3, so that the potential rise of the node Q can be further assisted, and the stable conduction of the switching unit M2 can be maintained.

Through the disclosure of the above panel driving circuits, the driving signal EM can stably drive the lighting circuit in the display panel, for example, the organic light emitting diode of each pixel in the display panel or the backlight module of the display panel, and the panel image can be completely and stably obtained. Brightness is presented.

Although the embodiments of the present invention have been disclosed as above, it is not intended to limit the present invention, and any person skilled in the art can make some modifications and retouchings without departing from the spirit and scope of the present invention. The scope is defined as defined in the scope of the patent application.

Claims (10)

A panel driving circuit includes: a first switching unit having an input end, an output end, and a control end, wherein the input end is configured to receive a start signal, and the control end is configured to receive a first clock signal, The first switch unit is turned on or off according to the first clock signal, and the start signal is outputted when the first switch unit is turned on; and a second switch unit has an input end, an output end, and a a control terminal, wherein the input end of the second switch unit is configured to receive a driving voltage, and the control end of the second switch unit is electrically connected to the output end of the first switch unit at a first node to receive the a first capacitor and a second terminal, wherein the first end is configured to receive a second clock signal, and the second end is electrically connected to the first node; When the second switching unit is turned on according to the startup signal, the second clock signal generates a coupling voltage to the first node through the first capacitor, and the driving voltage is output through the second switching unit to drive a panel. The panel driving circuit of claim 1, further comprising: a third switching unit having an input end, an output end, and a control end, wherein the input end of the third switch unit receives the first clock signal The control terminal of the third switch unit is electrically connected to the output end of the first switch unit; a reset circuit is electrically connected to the output end of the first switch unit, the first node, the second The output of the switch unit, and The second node is electrically connected to the output end of the third switch unit; and a second capacitor has a first end and a second end, wherein the first end of the second capacitor is configured to receive the second end The pulse signal, the second end of the second capacitor is electrically connected to the second node. The panel driving circuit of claim 2, wherein the reset circuit comprises: a fourth switching unit electrically connected to the second node to be turned on according to a potential of the second node; and a fifth switching unit electrically connected The fourth switch unit and the first node receive a reset voltage; and a sixth switch unit electrically connected to the fourth switch unit and the output end of the second switch unit, and receives the reset voltage When the fourth switching unit is turned on, the fifth switching unit and the sixth switching unit are turned on according to the second clock signal to further conduct the reset voltage to the first node and the second switching unit, respectively. The output. The panel driving circuit of claim 1, further comprising: a seventh switching unit disposed between the output end of the first switching unit and the first node, wherein the first switching unit and the seventh switching unit are configured according to the The first clock signal is turned on or off. The panel driving circuit of claim 1, further comprising: a third capacitor having a first end and a second end, wherein the third The first end of the capacitor is electrically connected to the first node, and the second end of the third capacitor is electrically connected to the output end of the second switch unit. A panel driving method for a panel driving circuit, the panel driving circuit includes a first switching unit, a second switching unit and a first capacitor, wherein the first switching unit and the second switching unit are first The node is electrically connected, and one end of the first capacitor is electrically connected to the first node, and the panel driving method includes: providing a start signal having a first potential to the first switch unit during a first time period; Providing a first clock signal to turn on the first switch unit, and the start signal is turned on to the first node, so that the first node has the first potential to turn on the second switch unit, and the second switch unit is turned on a driving voltage is output to a panel; a second clock signal is supplied to the first capacitor during a second period, and the second clock signal generates a coupling voltage to the first node through the first capacitor The first node is boosted to a boosting potential. The panel driving method of claim 6, further comprising: providing the activation signal having a second potential to the first switching unit and providing the first clock signal to turn on the first And a switching unit that turns on the startup signal to the first node, so that the first node has the second potential to turn off the second switching unit. The panel driving method of claim 6, wherein the panel driving circuit further comprises a third switching unit and a reset circuit, the The third switch unit is coupled to the first switch unit, the reset circuit is configured to provide a reset voltage to the first node and the second switch unit, and the reset circuit is at a second node and the third switch The unit driving method further includes: causing the activation signal provided by the first switching unit to be turned on by the third switching unit during the first time period; and providing the first clock signal during the second time period Up to the third switching unit, the third switching unit turns on the first clock signal to the reset circuit, and the reset circuit stops acting according to the first clock signal to not output the reset voltage. The panel driving method of claim 8, further comprising: providing the activation signal having a second potential to the first switching unit and providing the first clock signal to turn on the first And a switching unit, the activation signal is passed through the first switching unit to turn off the third switching unit. The panel driving method of claim 9, wherein the panel driving circuit further comprises a second capacitor, one end of the second capacitor is coupled to the second node, and the panel driving method further comprises: during a fourth period, Providing the second clock signal to the second capacitor, the second clock signal actuating the reset circuit through the second capacitor, so that the reset circuit provides the reset voltage to the first node and the first Two switch units.