TWI641219B - Power-on control circuit and input/output control circuit - Google Patents
Power-on control circuit and input/output control circuit Download PDFInfo
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Abstract
一種電源啟動控制電路,用以產生第一控制信號來控制輸出級電路,其包括第一與第二電源端、開關電路、反向器鏈電路、以及電容器。開關電路具有接收第一控制信號的控制端、耦接第二電源端的輸入端、以及耦接第一節點的輸出端。反向器鏈電路耦接第一電源端,且具有耦接第一節點的輸入端,用以產生第一控制信號。電容器耦接於第一節點與接地端之間。當第一電源端接收第一電壓而第二電源端尚未接收到第二電壓時,開關電路根據第一控制信號而導通。當第一電源端接收第一電壓且第二電源端接收第二電壓時,開關電路根據第一控制信號而關閉。 A power start control circuit for generating a first control signal for controlling an output stage circuit including first and second power terminals, a switch circuit, an inverter chain circuit, and a capacitor. The switch circuit has a control end that receives the first control signal, an input that is coupled to the second power supply end, and an output that is coupled to the first node. The inverter chain circuit is coupled to the first power terminal and has an input coupled to the first node for generating a first control signal. The capacitor is coupled between the first node and the ground. When the first power terminal receives the first voltage and the second power terminal has not received the second voltage, the switching circuit is turned on according to the first control signal. When the first power terminal receives the first voltage and the second power terminal receives the second voltage, the switching circuit is turned off according to the first control signal.
Description
本發明係有關於一種電源啟動控制電路,特別是有關於一種具有較低漏電流的電源啟動控制電路。 The present invention relates to a power start control circuit, and more particularly to a power start control circuit having a lower leakage current.
在一些積體電路中,其輸出端電路可能同時由兩個不同的電壓來供電。舉例來說,耦接一輸入/出墊的輸出級電路由電壓3.3V來供電,而用來控制輸出級初端電路的控制電路由電壓1.8V來供電。當電壓3.3V已被提供而電壓1.8V尚未被提供時,由於控制電路不動作而使得輸出級電路的輸入端處於浮接狀態,這導致在輸出級電路中具有一漏電流。為了解決輸出級電路的漏電流,則利用電源啟動電路來截斷此漏電流的路徑。然而,一般的電源啟動電路在電壓3.3V與1.8V皆已被提供的情況下,也會有漏電流的產生,造成不必要的功率消耗。 In some integrated circuits, the output circuit may be powered by two different voltages simultaneously. For example, an output stage circuit coupled to an input/output pad is powered by a voltage of 3.3V, and a control circuit for controlling the initial stage circuit of the output stage is powered by a voltage of 1.8V. When a voltage of 3.3V has been supplied and a voltage of 1.8V has not been supplied, the input of the output stage circuit is in a floating state due to the inoperative operation of the control circuit, which results in a leakage current in the output stage circuit. In order to solve the leakage current of the output stage circuit, the power start circuit is used to cut off the path of the leakage current. However, in the case where a general power supply starting circuit has been supplied with voltages of 3.3V and 1.8V, leakage current is also generated, resulting in unnecessary power consumption.
本發明提供一種電源啟動控制電路,用以產生第一控制信號來控制輸出級電路。電源啟動控制電路包括第一電源端、第二電源端、開關電路、反向器鏈電路、以及電容器。第一電源端用以接收第一電壓。第二電源端用以接收第二電壓。開關電路具有接收第一控制信號的控制端、耦接第二電源端的輸入端、以及耦接第一節點的輸出端。反向器鏈電路耦接 第一電源端,且具有耦接第一節點的輸入端,用以產生第一控制信號。電容器耦接於第一節點與接地端之間。當第一電源端接收第一電壓而第二電源端尚未接收到第二電壓時,開關電路根據第一控制信號而導通。當第一電源端接收第一電壓且第二電源端接收第二電壓時,開關電路根據第一控制信號而關閉。 The invention provides a power start control circuit for generating a first control signal to control an output stage circuit. The power start control circuit includes a first power terminal, a second power terminal, a switching circuit, an inverter chain circuit, and a capacitor. The first power terminal is configured to receive the first voltage. The second power terminal is configured to receive the second voltage. The switch circuit has a control end that receives the first control signal, an input that is coupled to the second power supply end, and an output that is coupled to the first node. Inverter chain circuit coupling The first power terminal has an input coupled to the first node for generating a first control signal. The capacitor is coupled between the first node and the ground. When the first power terminal receives the first voltage and the second power terminal has not received the second voltage, the switching circuit is turned on according to the first control signal. When the first power terminal receives the first voltage and the second power terminal receives the second voltage, the switching circuit is turned off according to the first control signal.
本發明又提供一種輸入/出控制電路,耦接輸入/出接墊。輸入/出控制電路包括第一電源端、第二電源端、輸出級電路、以及電源啟動控制電路。第一電源端用以接收第一電壓。第二電源端用以接收第二電壓。輸出級電路耦接輸入/出接墊以及第一電源端,且受控於第一控制信號。電源啟動控制電路耦接輸出級電路,用以產生第一控制信號。電源啟動控制電路包括開關電路、反向器鏈電路、以及電容器。開關電路具有接收第一控制信號的控制端、耦接第二電源端的輸入端、以及耦接第一節點的輸出端。反向器鏈電路耦接第一電源端,且具有耦接第一節點的輸入端,用以產生第一控制信號。電容器耦接於第一節點與接地端之間。當該第一電源端接收第一電壓而第二電源端尚未接收到第二電壓時,開關電路根據第一控制信號而導通。當第一電源端接收第一電壓且第二電源端接收第二電壓時,開關電路根據該第一控制信號而關閉。 The invention further provides an input/output control circuit coupled to the input/outlet pad. The input/output control circuit includes a first power terminal, a second power terminal, an output stage circuit, and a power start control circuit. The first power terminal is configured to receive the first voltage. The second power terminal is configured to receive the second voltage. The output stage circuit is coupled to the input/outlet pad and the first power terminal, and is controlled by the first control signal. The power start control circuit is coupled to the output stage circuit for generating the first control signal. The power start control circuit includes a switch circuit, an inverter chain circuit, and a capacitor. The switch circuit has a control end that receives the first control signal, an input that is coupled to the second power supply end, and an output that is coupled to the first node. The inverter chain circuit is coupled to the first power terminal and has an input coupled to the first node for generating a first control signal. The capacitor is coupled between the first node and the ground. When the first power terminal receives the first voltage and the second power terminal has not received the second voltage, the switch circuit is turned on according to the first control signal. When the first power terminal receives the first voltage and the second power terminal receives the second voltage, the switch circuit is turned off according to the first control signal.
1‧‧‧輸入/出控制電路 1‧‧‧Input/Output Control Circuit
10‧‧‧電源啟動控制電路 10‧‧‧Power start control circuit
11‧‧‧輸出級電路 11‧‧‧Output stage circuit
12‧‧‧閘極控制電路 12‧‧‧ gate control circuit
13、14‧‧‧電源端 13, 14‧‧‧ power terminal
20…22‧‧‧反向電路 20...22‧‧‧reverse circuit
23‧‧‧NMOS電晶體 23‧‧‧ NMOS transistor
24‧‧‧緩衝電路 24‧‧‧ buffer circuit
25‧‧‧PMOS電晶體 25‧‧‧ PMOS transistor
30、40‧‧‧傳輸閘 30, 40‧‧‧ transmission gate
100‧‧‧開關電路 100‧‧‧Switch circuit
101‧‧‧電阻器 101‧‧‧Resistors
102‧‧‧電容器 102‧‧‧ capacitor
103‧‧‧反向器鏈電路 103‧‧‧Inverter chain circuit
104‧‧‧回授電路 104‧‧‧Return circuit
110、112‧‧‧PMOS電晶體 110, 112‧‧‧ PMOS transistor
111、113‧‧‧NMOS電晶體 111, 113‧‧‧ NMOS transistor
200、210、220‧‧‧PMOS電晶體 200, 210, 220‧‧‧ PMOS transistors
201、211、221‧‧‧NMOS電晶體 201, 211, 221‧‧‧ NMOS transistors
240、242‧‧‧NMOS電晶體 240, 242‧‧‧ NMOS transistor
241、243‧‧‧PMOS電晶體 241, 243‧‧‧ PMOS transistor
300、400‧‧‧PMOS電晶體 300, 400‧‧‧ PMOS transistor
301、401‧‧‧NMOS電晶體 301, 401‧‧‧ NMOS transistor
GND‧‧‧接地端 GND‧‧‧ ground terminal
N10…N13、N20…N23‧‧‧節點 N10...N13, N20...N23‧‧‧ nodes
PAD‧‧‧輸入/出墊 PAD‧‧‧Input/Output
POC0…POC3‧‧‧控制信號 POC0...POC3‧‧‧ control signal
第1圖表示根據本發明一實施例的輸入/出控制電路。 Figure 1 shows an input/output control circuit in accordance with an embodiment of the present invention.
第2A圖表示根據本發明另一實施例的輸入/出控制電路。 Fig. 2A shows an input/output control circuit in accordance with another embodiment of the present invention.
第2B圖表示第2A圖的輸入/出控制電路操作在電源啟動控 制階段的示意圖。 Figure 2B shows the input/output control circuit of Figure 2A operating at power-on control Schematic diagram of the stage of production.
第2C圖表示第2A圖的輸入/出控制電路操作在穩定階段的示意圖。 Fig. 2C is a view showing the operation of the input/output control circuit of Fig. 2A in the stabilization phase.
第3圖表示根據本發明另一實施例的輸入/出控制電路。 Figure 3 shows an input/output control circuit in accordance with another embodiment of the present invention.
第4圖表示根據本發明又一實施例的輸入/出控制電路。 Fig. 4 shows an input/output control circuit according to still another embodiment of the present invention.
第5圖表示根據本發明一實施例的輸入/出控制電路。 Figure 5 shows an input/output control circuit in accordance with an embodiment of the present invention.
第6圖表示根據本發明另一實施例的輸入/出控制電路。 Figure 6 shows an input/output control circuit in accordance with another embodiment of the present invention.
第7圖表示根據本發明又一實施例的輸入/出控制電路。 Figure 7 shows an input/output control circuit in accordance with still another embodiment of the present invention.
為使本發明之上述目的、特徵和優點能更明顯易懂,下文特舉一較佳實施例,並配合所附圖式,作詳細說明如下。 The above described objects, features and advantages of the present invention will become more apparent from the description of the appended claims.
第1圖是表示根據本發明一實施例的輸入/出控制電路。參閱第1圖,輸入/出控制電路1屬於一積體電路的輸出端電路的一部分,且耦接此積體電路的一輸入/出墊PAD。輸入/出控制電路1包括電源啟動控制電路10、輸出級電路11、以及閘極控制電路12。電源啟動控制電路10包括開關電路100、電阻器101、電容器102、反向器鏈電路103、以及回授電路104。輸出級電路11包括P型金氧半(p-type metal-oxide-semiconductor,PMOS)電晶體110與112以及N型金氧半(N-type metal-oxide-semiconductor,NMOS)電晶體111與113。開關電路100的控制端接收一控制信號POC2,其輸入端耦接電源端13,其輸出端耦接節點N10。開關電路100的導通/關閉狀態是由控制信號POC2所控制。電阻器101耦接於節點N10與N11 之間。電容器102耦接於節點N11與接地端GND之間。反向器鏈電路103耦接於電源端14與接地端GND,且具有複數個串接的反向器。反向器鏈電路103的輸入端耦接節點N10,且根據節點N10上的電壓來產生互為反向的控制信號POC2與POC3。回授電路104耦接於反向器鏈電路103與節點N11之間,其可根據控制信號POC2來改變節點N11上控制信號POC0的電壓位準。 Fig. 1 is a diagram showing an input/output control circuit according to an embodiment of the present invention. Referring to FIG. 1, the input/output control circuit 1 is part of an output circuit of an integrated circuit and is coupled to an input/output pad PAD of the integrated circuit. The input/output control circuit 1 includes a power start control circuit 10, an output stage circuit 11, and a gate control circuit 12. The power start control circuit 10 includes a switch circuit 100, a resistor 101, a capacitor 102, an inverter chain circuit 103, and a feedback circuit 104. The output stage circuit 11 includes p-type metal-oxide-semiconductor (PMOS) transistors 110 and 112 and N-type metal-oxide-semiconductor (NMOS) transistors 111 and 113. . The control terminal of the switch circuit 100 receives a control signal POC2, the input end of which is coupled to the power supply terminal 13, and the output end of which is coupled to the node N10. The on/off state of the switch circuit 100 is controlled by the control signal POC2. The resistor 101 is coupled to the nodes N10 and N11 between. The capacitor 102 is coupled between the node N11 and the ground GND. The inverter chain circuit 103 is coupled to the power terminal 14 and the ground GND, and has a plurality of inverters connected in series. The input end of the inverter chain circuit 103 is coupled to the node N10, and generates mutually inverted control signals POC2 and POC3 according to the voltage on the node N10. The feedback circuit 104 is coupled between the inverter chain circuit 103 and the node N11, and can change the voltage level of the control signal POC0 on the node N11 according to the control signal POC2.
PMOS電晶體110的閘極接收控制信號POC2,其源極耦接電壓端14,且其汲極耦接節點N12。NMOS電晶體111的閘極接收控制信號POC3,其汲極耦接節點N13,且其源極耦接接地端GND。PMOS電晶體112的閘極耦接節點N12,其源極耦接電壓端14,且其汲極耦接輸入/出墊PAD。NMOS電晶體113的閘極耦接節點N13,其汲極耦接輸入/出墊PAD,且其源極耦接接地端GND。閘極控制電路12耦接電源端13與電源端14。閘極控制電路12也耦接節點N12與N13,其可分別提供閘極控制信號至PMOS電晶體112的閘極與NMOS電晶體114的閘極。 The gate of the PMOS transistor 110 receives the control signal POC2, the source of which is coupled to the voltage terminal 14, and the drain of which is coupled to the node N12. The gate of the NMOS transistor 111 receives the control signal POC3, the drain of which is coupled to the node N13, and the source of which is coupled to the ground GND. The gate of the PMOS transistor 112 is coupled to the node N12, the source of which is coupled to the voltage terminal 14, and the drain of which is coupled to the input/output pad PAD. The gate of the NMOS transistor 113 is coupled to the node N13, the drain of which is coupled to the input/output pad PAD, and the source of which is coupled to the ground GND. The gate control circuit 12 is coupled to the power terminal 13 and the power terminal 14. The gate control circuit 12 is also coupled to nodes N12 and N13, which can respectively provide a gate control signal to the gate of the PMOS transistor 112 and the gate of the NMOS transistor 114.
電源端13與14係用來接收不同的電壓。舉例來說,電源端13係用來接收1.8伏(V)的電壓,而電源端14係用來接收3.3V的電壓。在一些情況下,電源端14已接收到3.3V電壓,但是電源端13尚未接收到1.8V電壓。舉例來說,1.8V電壓係由一電壓轉換器對3.3V電壓進行降壓後所產生。因此,電源端13會比電源端14接收到電壓。在本發明實施例中,當電源端14接收到3.3V電壓而電源端13尚未接收到1.8V電壓(即電源端13具有0V)時,輸入/出控制電路1操作在一電源啟動控制階段。在輸入/出控制電路1進入電源啟動控制階段的瞬間,節點N11上的控 制信號POC0的電壓位準為0V,且反向器鏈電路103根據節點N11上的控制信號POC0(0V)產生具有0V電壓位準的控制信號POC2以及具有3.3V電壓位準的控制信號POC3。因此可知,控制信號POC2具有低電壓位準,而控制信號POC3具有高電壓位準,也就是,控制信號POC2與POC3的電壓位準互為反向。此時,開關電路100根據具有0V電壓位準的控制信號POC2而導通。PMOS電晶體110以及NMOS電晶體11N1分別根據控制信號POC2與POC3而導通。因此,節點N12與N13分別具有3.3V電壓與0V電壓,以分別關閉PMOS電晶體112與NMOS電晶體113。此外,由於電源端13尚未接收到1.8V電壓使得閘極控制電路12不操作,因此PMOS電晶體112與NMOS電晶體113導通/關閉狀態不受閘極控制電路12的控制。如此一來,在電源啟動控制階段中,由於PMOS電晶體112與NMOS電晶體113皆關閉,在輸出級電路11中介於電源端14與接地端GND的漏電流路徑則被截斷,避免了驅動漏電流的產生。此外,在電源啟動控制階段,回授電路104不根據控制信號POC2來改變節點N11上的電壓位準。 Power terminals 13 and 14 are used to receive different voltages. For example, power terminal 13 is used to receive a voltage of 1.8 volts (V) and power terminal 14 is used to receive a voltage of 3.3V. In some cases, power supply terminal 14 has received a 3.3V voltage, but power supply terminal 13 has not received a 1.8V voltage. For example, the 1.8V voltage is generated by a voltage converter that steps down the 3.3V voltage. Therefore, the power supply terminal 13 receives a voltage than the power supply terminal 14. In the embodiment of the present invention, when the power supply terminal 14 receives the 3.3V voltage and the power supply terminal 13 has not received the 1.8V voltage (ie, the power supply terminal 13 has 0V), the input/output control circuit 1 operates in a power supply start control phase. At the moment when the input/output control circuit 1 enters the power-on startup control phase, the control on the node N11 The voltage level of the signal POC0 is 0V, and the inverter chain circuit 103 generates a control signal POC2 having a voltage level of 0V and a control signal POC3 having a voltage level of 3.3V in accordance with the control signal POC0 (0V) on the node N11. Therefore, it can be seen that the control signal POC2 has a low voltage level, and the control signal POC3 has a high voltage level, that is, the voltage levels of the control signals POC2 and POC3 are opposite each other. At this time, the switch circuit 100 is turned on in accordance with the control signal POC2 having a voltage level of 0V. The PMOS transistor 110 and the NMOS transistor 11N1 are turned on in accordance with the control signals POC2 and POC3, respectively. Therefore, the nodes N12 and N13 have a voltage of 3.3 V and a voltage of 0 V, respectively, to turn off the PMOS transistor 112 and the NMOS transistor 113, respectively. In addition, since the power supply terminal 13 has not received the 1.8V voltage so that the gate control circuit 12 does not operate, the on/off states of the PMOS transistor 112 and the NMOS transistor 113 are not controlled by the gate control circuit 12. In this way, in the power-on control phase, since both the PMOS transistor 112 and the NMOS transistor 113 are turned off, the leakage current path between the power terminal 14 and the ground GND in the output stage circuit 11 is cut off, thereby avoiding driving leakage. The generation of current. Further, in the power-on control phase, the feedback circuit 104 does not change the voltage level on the node N11 in accordance with the control signal POC2.
當電源端14接收到3.3V電壓且電源端13也接收到1.8V電壓時,輸入/出控制電路1操作在一穩定階段。在輸入/出控制電路1由電源啟動控制階段進入穩定階段的瞬間,控制信號POC2仍為0V,且開關電路100根據控制信號POC2而導通。此時,節點N11上控制信號POC0的電壓位準變為1.8V,且反向器鏈電路103根據節點N11上的控制信號POC0(1.8V)來產生電壓位準為3.3V的控制信號POC2以及電壓位準為1.8V的控制信 號POC3。因此可知,控制信號POC2具有高電壓位準,而控制信號POC3具有低電壓位準。此時,具有3.3V電壓位準的控制信號POC2關閉了開關電路100,且回授電路104提供回授路徑以根據控制信號POC2來改變節點N11上控制信號POC0的電壓位準使其變為控制信號POC2的電壓位準,即3.3V。由於控制信號POC0的電壓位準由1.8V變為3.3V,反向器鏈電路103的輸入端也處於3.3V,藉此截斷反向器鏈電路103中介於電源端14與接地端GND之間的漏電流路徑。此外,在穩定階段中,PMOS電晶體110以及NMOS電晶體111分別根據控制信號POC2與POC3而關閉。此時,由於閘極控制器12透過電源端13由1.8V供電且透過電源端14由3.3V供電而操作,PMOS電晶體112與NMOS電晶體113導通/關閉狀態則由閘極控制電路12來控制。 When the power supply terminal 14 receives the 3.3V voltage and the power supply terminal 13 also receives the 1.8V voltage, the input/output control circuit 1 operates in a stable phase. At the instant when the input/output control circuit 1 enters the steady phase from the power-on control phase, the control signal POC2 is still 0V, and the switch circuit 100 is turned on according to the control signal POC2. At this time, the voltage level of the control signal POC0 on the node N11 becomes 1.8V, and the inverter chain circuit 103 generates the control signal POC2 having a voltage level of 3.3V according to the control signal POC0 (1.8V) on the node N11 and Control signal with a voltage level of 1.8V No. POC3. Therefore, it can be seen that the control signal POC2 has a high voltage level and the control signal POC3 has a low voltage level. At this time, the control signal POC2 having a voltage level of 3.3V turns off the switching circuit 100, and the feedback circuit 104 provides a feedback path to change the voltage level of the control signal POC0 on the node N11 according to the control signal POC2 to make it control. The voltage level of signal POC2, which is 3.3V. Since the voltage level of the control signal POC0 is changed from 1.8V to 3.3V, the input terminal of the inverter chain circuit 103 is also at 3.3V, thereby intercepting the inverter chain circuit 103 between the power supply terminal 14 and the ground terminal GND. Leakage current path. Further, in the stabilization phase, the PMOS transistor 110 and the NMOS transistor 111 are turned off according to the control signals POC2 and POC3, respectively. At this time, since the gate controller 12 is powered by 1.8V through the power supply terminal 13 and is powered by 3.3V through the power supply terminal 14, the PMOS transistor 112 and the NMOS transistor 113 are turned on/off by the gate control circuit 12. control.
根據上述,在電源啟動控制階段與穩定階段中,透過截斷漏電流路徑來避免漏電流的產生,藉此減少不必要的功率消耗。以下將透過各種實施例來詳細說明本案輸入/出控制電路1的操作。 According to the above, in the power-on startup control phase and the stabilization phase, the leakage current is prevented from being generated by intercepting the leakage current path, thereby reducing unnecessary power consumption. The operation of the input/output control circuit 1 of the present invention will be described in detail below through various embodiments.
第2A圖係表示根據本發明另一實施例的輸入/出控制電路。參閱第2A圖,開關電路100包括PMOS電晶體25。PMOS電晶體24的閘極耦接開關電路100的控制端以接收控制信號POC2,其汲極耦接開關電路100的輸入端(即耦接電源端13),且其源極耦接開關電路100的輸出端(即耦接節點N10)。PMOS電晶體24的井區耦接電源端14。反向器鏈電路103包括反向電路20~22以及NMOS電晶體23。反向電路20包括PMOS電晶體200以及NMOS電晶體201。反向電路21包括PMOS電晶體210以及 NMOS電晶體211。反向電路22包括PMOS電晶體220以及NMOS電晶體221。PMOS電晶體200的閘極耦接反向器鏈電路103的輸入端(即,耦接節點N11),其源極耦接電源端14,且其汲極端耦接節點N20。NMOS電晶體201的閘極耦接反向器鏈電路103的輸入端(即,耦接節點N11),其汲極耦接節點N20,且其源極耦接接地端GND。根據反向電路20的架構可知,節點N11可作為反向電路20的輸入端,而節點20可作為反向電路20的輸出端。NMOS電晶體23的閘極耦接節點N20,且其汲極耦接電源端14,且其源極耦接接地端GND。PMOS電晶體210的閘極耦接節點N20,其源極耦接電源端14,且其汲極端耦接節點N21。NMOS電晶體211的閘極耦接節點N20,其汲極耦接節點N21,且其源極耦接接地端GND。根據反向電路21的架構可知,節點N20可作為反向電路21的輸入端,而節點21可作為反向電路21的輸出端。PMOS電晶體220的閘極耦接節點N21,其源極耦接電源端14,且其汲極端耦接節點N22。NMOS電晶體221的閘極耦接節點N21,其汲極耦接節點N22,且其源極耦接接地端GND。根據反向電路22的架構可知,節點N21可作為反向電路22的輸入端,而節點22可作為反向電路22的輸出端。反向器鏈電路103於節點N20上產生控制信號POC1,於節點N21上產生控制信號POC2,且於節點N22上產生控制信號POC3。NMOS電晶體23係用於當發生靜電放電事件時,用來提供一靜電放電路徑。 Fig. 2A shows an input/output control circuit in accordance with another embodiment of the present invention. Referring to FIG. 2A, the switching circuit 100 includes a PMOS transistor 25. The gate of the PMOS transistor 24 is coupled to the control terminal of the switch circuit 100 to receive the control signal POC2, the drain of which is coupled to the input end of the switch circuit 100 (ie, coupled to the power supply terminal 13), and the source thereof is coupled to the switch circuit 100. The output (ie, coupled to node N10). The well region of the PMOS transistor 24 is coupled to the power terminal 14. The inverter chain circuit 103 includes reverse circuits 20 to 22 and an NMOS transistor 23. The reverse circuit 20 includes a PMOS transistor 200 and an NMOS transistor 201. The reverse circuit 21 includes a PMOS transistor 210 and NMOS transistor 211. The reverse circuit 22 includes a PMOS transistor 220 and an NMOS transistor 221. The gate of the PMOS transistor 200 is coupled to the input end of the inverter chain circuit 103 (ie, the coupling node N11), the source of which is coupled to the power terminal 14 and the terminal of which is coupled to the node N20. The gate of the NMOS transistor 201 is coupled to the input end of the inverter chain circuit 103 (ie, coupled to the node N11), the drain of which is coupled to the node N20, and the source of which is coupled to the ground GND. According to the architecture of the reverse circuit 20, the node N11 can serve as the input of the inverting circuit 20, and the node 20 can serve as the output of the inverting circuit 20. The gate of the NMOS transistor 23 is coupled to the node N20, and the drain is coupled to the power terminal 14 and the source thereof is coupled to the ground GND. The gate of the PMOS transistor 210 is coupled to the node N20, the source of which is coupled to the power terminal 14 and the terminal of which is coupled to the node N21. The gate of the NMOS transistor 211 is coupled to the node N20, the drain of the node is coupled to the node N21, and the source thereof is coupled to the ground GND. According to the architecture of the inverting circuit 21, the node N20 can serve as the input of the inverting circuit 21, and the node 21 can serve as the output of the inverting circuit 21. The gate of the PMOS transistor 220 is coupled to the node N21, the source of which is coupled to the power terminal 14 and the terminal of which is coupled to the node N22. The gate of the NMOS transistor 221 is coupled to the node N21, the drain of the node is coupled to the node N22, and the source thereof is coupled to the ground GND. According to the architecture of the reverse circuit 22, the node N21 can serve as the input of the inverting circuit 22 and the node 22 can serve as the output of the inverting circuit 22. The inverter chain circuit 103 generates a control signal POC1 at the node N20, a control signal POC2 at the node N21, and a control signal POC3 at the node N22. The NMOS transistor 23 is used to provide an electrostatic discharge path when an electrostatic discharge event occurs.
參與2A圖,回授電路104包括緩衝電路24。緩衝電路24的輸入端耦接於節點N21,且其輸出端耦接節點N11。緩衝電路24透過節點N21接收控制信號POC2,以將其緩衝至節點 N11,藉此控制控制信號POC0的電壓位準。緩衝電路24包括NMOS電晶體240與242以及PMOS電晶體241與243。PMOS電晶體241的閘極耦接緩衝電路24的輸入端,其源極耦接電源端14,且其汲極端耦接節點N23。NMOS電晶體240的閘極耦接緩衝電路24的輸入端,其汲極耦接節點N23,且其源極耦接接地端GND。PMOS電晶體243的閘極耦接節點N23,其源極耦接電源端14,且其汲極端耦接緩衝電路24的輸出端。NMOS電晶體242的閘極耦接節點N23,其汲極耦接緩衝電路23的輸出端,且其源極耦接接地端GND。NMOS電晶體240與242以及PMOS電晶體241與243共同操作來對節點N23上的電壓或信號進行緩衝。以下將說明第2A圖實施例中輸入/出控制電路的詳細操作。 In the 2A diagram, the feedback circuit 104 includes a buffer circuit 24. The input end of the buffer circuit 24 is coupled to the node N21, and the output end thereof is coupled to the node N11. The buffer circuit 24 receives the control signal POC2 through the node N21 to buffer it to the node. N11, thereby controlling the voltage level of the control signal POC0. The buffer circuit 24 includes NMOS transistors 240 and 242 and PMOS transistors 241 and 243. The gate of the PMOS transistor 241 is coupled to the input end of the buffer circuit 24, the source of which is coupled to the power supply terminal 14, and the other end of which is coupled to the node N23. The gate of the NMOS transistor 240 is coupled to the input end of the buffer circuit 24, the drain of which is coupled to the node N23, and the source of which is coupled to the ground GND. The gate of the PMOS transistor 243 is coupled to the node N23, the source of which is coupled to the power terminal 14 and the terminal of which is coupled to the output of the buffer circuit 24. The gate of the NMOS transistor 242 is coupled to the node N23, the drain of which is coupled to the output of the buffer circuit 23, and the source of which is coupled to the ground GND. NMOS transistors 240 and 242 and PMOS transistors 241 and 243 operate in conjunction to buffer the voltage or signal on node N23. The detailed operation of the input/output control circuit in the embodiment of Fig. 2A will be described below.
參閱第2B圖,當電源端14接收到3.3V電壓而電源端13尚未接收到1.8V電壓(即電源端13具有0V)時,輸入/出控制電路1操作在電源啟動控制階段。在輸入/出控制電路1進入電源啟動控制階段的瞬間,節點N11上的控制信號POC0的電壓位準為0V。透過反向電路20~22執行的反向操作,反向電路20於節點N20上產生具有3.3V電壓位準的控制信號POC1,反向電路21於節點N21上產生具有0V電壓位準的控制信號POC2,且反向電路22於節點N22上產生具有3.3V電壓位準的控制信號POC3。此時,PMOS電晶體25根據具有0V電壓位準的控制信號POC2而導通,以使節點N11上的控制信號POC0的電壓位準維持在0V。PMOS電晶體110以及NMOS電晶體111分別根據控制信號POC2與POC3而導通。此時,節點N12與N13分別具有3.3V電壓與0V電壓,以分別關閉PMOS電晶體112與NMOS電晶體113。此外, 由於電源端13尚未接收到1.8V電壓使得閘極控制電路12不操作,因此PMOS電晶體112與NMOS電晶體113的導通/關閉狀態在電源啟動控制階段中不受閘極控制電路12的控制。如此一來,在電源啟動控制階段中,由於PMOS電晶體112與NMOS電晶體113皆關閉,在輸出級電路11中介於電源端14與接地端GND的漏電流路徑則被截斷,避免了驅動漏電流的產生。 Referring to Fig. 2B, when the power supply terminal 14 receives the 3.3V voltage and the power supply terminal 13 has not received the 1.8V voltage (i.e., the power supply terminal 13 has 0V), the input/output control circuit 1 operates in the power supply start control phase. At the instant when the input/output control circuit 1 enters the power-on control phase, the voltage level of the control signal POC0 on the node N11 is 0V. Through the reverse operation performed by the inverting circuits 20 to 22, the inverting circuit 20 generates a control signal POC1 having a voltage level of 3.3 V at the node N20, and the inverting circuit 21 generates a control signal having a voltage level of 0 V at the node N21. POC2, and the inverting circuit 22 generates a control signal POC3 having a voltage level of 3.3V on the node N22. At this time, the PMOS transistor 25 is turned on in accordance with the control signal POC2 having a voltage level of 0 V, so that the voltage level of the control signal POC0 on the node N11 is maintained at 0V. The PMOS transistor 110 and the NMOS transistor 111 are turned on in accordance with the control signals POC2 and POC3, respectively. At this time, the nodes N12 and N13 have a voltage of 3.3 V and a voltage of 0 V, respectively, to turn off the PMOS transistor 112 and the NMOS transistor 113, respectively. In addition, Since the power supply terminal 13 has not received the 1.8V voltage so that the gate control circuit 12 does not operate, the on/off states of the PMOS transistor 112 and the NMOS transistor 113 are not controlled by the gate control circuit 12 in the power supply start control phase. In this way, in the power-on control phase, since both the PMOS transistor 112 and the NMOS transistor 113 are turned off, the leakage current path between the power terminal 14 and the ground GND in the output stage circuit 11 is cut off, thereby avoiding driving leakage. The generation of current.
此外,參閱第2B圖,在電源啟動控制階段,回授電路104的緩衝電路24接收0V電壓位準的控制信號POC2。透過緩衝電路24的緩衝操作,緩衝電路24的輸出端也維持在0V的電壓位準。因此可知,節點N11上的控制信號POC0仍維持在0V。換句話說,回授電路104不改變節點N11上的電壓位準。 Further, referring to FIG. 2B, in the power-on control phase, the buffer circuit 24 of the feedback circuit 104 receives the control signal POC2 of the 0V voltage level. Through the buffering operation of the buffer circuit 24, the output terminal of the buffer circuit 24 is also maintained at a voltage level of 0V. Therefore, it can be seen that the control signal POC0 on the node N11 is still maintained at 0V. In other words, the feedback circuit 104 does not change the voltage level on the node N11.
參閱第2C圖,當電源端14接收到3.3V電壓且電源端13也接收到1.8V電壓時,輸入/出控制電路1操作在一穩定階段。在輸入/出控制電路1由電源啟動控制階段進入穩定階段的瞬間,控制信號POC2仍為0V,且PMOS電晶體25根據具有0V電壓位準的控制信號POC2而持續導通。此時,節點N11上控制信號POC0的電壓位準變為1.8V。透過反向電路20~22執行的反向操作,反向電路20於節點N20上產生具有0V電壓位準的控制信號POC1,反向電路21於節點N21上產生具有3.3V電壓位準的控制信號POC2,且反向電路22於節點N22上產生具有0V電壓位準的控制信號POC3。因此可得知,在輸入/出控制電路1由電源啟動控制階段進入穩定階段的瞬間,由於PMOS電晶體200的閘極的電壓為1.8V而其源極的電壓為3.3V,PMOS電晶體200無法完全地關閉,導致在一漏電流路徑形成於電源端14與接地端GND 之間且通過電晶體200與201。PMOS電晶體25根據具有3.3V電壓位準的控制信號POC2而關閉。在本發明實施例中,透過回授電路104的操作,可截斷上述的漏電流路徑,說明書如下。參閱第4C圖,回授電路104的緩衝電路24接收3.3V電壓位準的控制信號POC2。透過緩衝電路24的緩衝操作,節點N11的電壓位準由1.8V提高至3.3V。換句話說,在穩定階段,回授電路104此時提供了一回授路徑,以根據控制信號POC2來改變節點N11上控制信號POC0的電壓位準使其變為控制信號POC2的電壓位準,即3.3V。由於PMOS電晶體200的閘極與源極的的電壓都為3.3V,因此PMOS電晶體200關閉,藉以截斷介於電源端14與接地端GND之間且通過電晶體200與201的漏電流路徑。 Referring to Fig. 2C, when the power supply terminal 14 receives a voltage of 3.3 V and the power supply terminal 13 also receives a voltage of 1.8 V, the input/output control circuit 1 operates in a stable phase. At the instant when the input/output control circuit 1 enters the stabilization phase from the power-on control phase, the control signal POC2 is still 0V, and the PMOS transistor 25 is continuously turned on according to the control signal POC2 having the 0V voltage level. At this time, the voltage level of the control signal POC0 on the node N11 becomes 1.8V. Through the reverse operation performed by the inverting circuits 20-22, the inverting circuit 20 generates a control signal POC1 having a voltage level of 0 V at the node N20, and the inverting circuit 21 generates a control signal having a voltage level of 3.3 V at the node N21. POC2, and the inverting circuit 22 generates a control signal POC3 having a voltage level of 0V on the node N22. Therefore, it can be seen that at the moment when the input/output control circuit 1 enters the stabilization phase from the power-on startup control phase, since the voltage of the gate of the PMOS transistor 200 is 1.8 V and the voltage of its source is 3.3 V, the PMOS transistor 200 Cannot be completely turned off, resulting in a leakage current path formed at the power supply terminal 14 and the ground GND Between and through the transistors 200 and 201. The PMOS transistor 25 is turned off in accordance with the control signal POC2 having a voltage level of 3.3V. In the embodiment of the present invention, the leakage current path can be cut off by the operation of the feedback circuit 104, and the description is as follows. Referring to Fig. 4C, the buffer circuit 24 of the feedback circuit 104 receives the control signal POC2 of the 3.3V voltage level. Through the buffering operation of the buffer circuit 24, the voltage level of the node N11 is increased from 1.8V to 3.3V. In other words, in the stabilization phase, the feedback circuit 104 provides a feedback path at this time to change the voltage level of the control signal POC0 on the node N11 to the voltage level of the control signal POC2 according to the control signal POC2. That is 3.3V. Since the voltages of the gate and the source of the PMOS transistor 200 are both 3.3V, the PMOS transistor 200 is turned off, thereby cutting off the leakage current path between the power terminal 14 and the ground GND and passing through the transistors 200 and 201. .
此外,參閱第2C圖,在穩定階段中,PMOS電晶體110以及NMOS電晶體111分別根據控制信號POC2與POC3而關閉。由於閘極控制器12在穩定階段中透過電源端13由1.8V供電且由透過電源端14由3.3V供電而操作,PMOS電晶體112與NMOS電晶體113導通/關閉狀態則由閘極控制電路12來控制。 Further, referring to FIG. 2C, in the stabilization phase, the PMOS transistor 110 and the NMOS transistor 111 are turned off according to the control signals POC2 and POC3, respectively. Since the gate controller 12 is powered by 1.8V through the power supply terminal 13 and is powered by 3.3V through the power supply terminal 14 during the stabilization phase, the PMOS transistor 112 and the NMOS transistor 113 are turned on/off by the gate control circuit. 12 to control.
根據上述,藉由電源啟動控制電路10的操作,不僅可截斷在電源啟動階段在輸出級電路11的漏電流路徑,也可在穩定階段中截斷在反向器鏈電路103中的漏電流路徑,藉此減少不必要的功率消耗。 According to the above, by the operation of the power-on control circuit 10, not only the leakage current path in the output stage circuit 11 during the power-start phase but also the leakage current path in the inverter chain circuit 103 can be cut off in the stabilization phase. Thereby reducing unnecessary power consumption.
在第2A-2C圖的實施例中,回授電路104僅包括緩衝電路24。在其他實施例中,回授電路104還可包括一傳輸閘,其至少受控於控制信號POC2。在一實施例中,參閱第3圖,回授電路104還包括傳輸閘30,其耦接於緩衝電路24的輸出端與 節點N11之間。傳輸閘30包括PMOS電晶體300與NMOS電晶體301。PMOS電晶體300的閘極接收控制信號POC3,其源極耦接緩衝電路24的輸出端(即耦接電晶體242與243的源極),且其汲極耦接節點N11。NMOS電晶體301的閘極接收控制信號POC2,其汲極耦接緩衝電路24的輸出端(即耦接電晶體242與243的源極),且其源極耦接耦接節點N11。在第3圖的實施例中,具有與第2A-2C圖的實施例中相同符號的電路與元件在電源啟動控制階段與穩定階段的操作如同上述的第2A-2C的實施例,在此將省略敘述。下文僅說明傳輸閘30的操作。在電源啟動控制階段,PMOS電晶體300與NMOS電晶體301分別根據具有3.3V電壓位準的控制信號POC3與具有0V電壓位準的控制信號POC2而關閉。因此,回授電路104不提供介於節點N21與N11之間的回授路徑,如此一來,回授電路104不根據控制信號POC2來改變節點N11上的電壓位準。在穩定階段,PMOS電晶體300與NMOS電晶體301分別根據具有0V電壓位準的控制信號POC3與具有3.3V電壓位準的控制信號POC2而導通。因此,回授電路104提供了介於節點N21與N11之間的回授路徑,以根據控制信號POC2來改變節點N11上控制信號POC0的電壓位準使其變為控制信號POC2的電壓位準,即3.3V。 In the embodiment of the 2A-2C diagram, the feedback circuit 104 includes only the buffer circuit 24. In other embodiments, the feedback circuit 104 can also include a transmission gate that is at least controlled by the control signal POC2. In an embodiment, referring to FIG. 3, the feedback circuit 104 further includes a transmission gate 30 coupled to the output of the buffer circuit 24 and Between nodes N11. The transfer gate 30 includes a PMOS transistor 300 and an NMOS transistor 301. The gate of the PMOS transistor 300 receives the control signal POC3, the source of which is coupled to the output of the buffer circuit 24 (ie, the source of the transistors 242 and 243), and the drain is coupled to the node N11. The gate of the NMOS transistor 301 receives the control signal POC2, the drain of which is coupled to the output of the buffer circuit 24 (ie, the source of the transistors 242 and 243), and the source of the transistor 301 is coupled to the node N11. In the embodiment of Fig. 3, the circuits and elements having the same reference numerals as in the embodiment of the second A-2C diagram operate in the power-start control phase and the stabilization phase as in the above-described embodiment of the second embodiment A-2C, The description is omitted. Only the operation of the transfer gate 30 will be described below. In the power-on control phase, the PMOS transistor 300 and the NMOS transistor 301 are turned off according to a control signal POC3 having a voltage level of 3.3 V and a control signal POC2 having a voltage level of 0 V, respectively. Therefore, the feedback circuit 104 does not provide a feedback path between the nodes N21 and N11, and thus, the feedback circuit 104 does not change the voltage level on the node N11 according to the control signal POC2. In the stabilization phase, the PMOS transistor 300 and the NMOS transistor 301 are turned on according to the control signal POC3 having a voltage level of 0 V and the control signal POC2 having a voltage level of 3.3 V, respectively. Therefore, the feedback circuit 104 provides a feedback path between the nodes N21 and N11 to change the voltage level of the control signal POC0 on the node N11 to the voltage level of the control signal POC2 according to the control signal POC2. That is 3.3V.
在另一實施例中,參閱第4圖,回授電路104還包括傳輸閘40,其耦接於節點21與緩衝電路24的輸入端之間。傳輸閘40包括PMOS電晶體400與NMOS電晶體401。PMOS電晶體400的閘極接收控制信號POC3,其源極耦接節點N21,且其汲極耦接緩衝電路24的輸入端(即耦接電晶體240與241的閘極)。NMOS 電晶體401的閘極接收控制信號POC2,其汲極耦接節點N21,且其源極耦接緩衝電路24的輸入端(即耦接電晶體240與241的閘極)。在第4圖的實施例中,具有與第2A-2C圖的實施例中相同符號的電路與元件在電源啟動控制階段與穩定階段的操作如同上述的第2A-2C的實施例,在此將省略敘述。下文僅說明傳輸閘40的操作。在電源啟動控制階段,PMOS電晶體400與NMOS電晶體401分別根據具有3.3V電壓位準的控制信號POC3與具有0V電壓位準的控制信號POC2而關閉。因此,回授電路104不提供介於節點N21與N11之間的回授路徑,如此一來,回授電路104不根據控制信號POC2來改變節點N11上的電壓位準。在穩定階段,PMOS電晶體400與NMOS電晶體401分別根據具有0V電壓位準的控制信號POC3與具有3.3V電壓位準的控制信號POC2而導通。因此,回授電路104提供了介於節點N21與N11之間的回授路徑,以根據控制信號POC2來改變節點N11上控制信號POC0的電壓位準使其變為控制信號POC2的電壓位準,即3.3V。 In another embodiment, referring to FIG. 4, the feedback circuit 104 further includes a transfer gate 40 coupled between the node 21 and the input of the buffer circuit 24. The transfer gate 40 includes a PMOS transistor 400 and an NMOS transistor 401. The gate of the PMOS transistor 400 receives the control signal POC3, the source of which is coupled to the node N21, and the drain of which is coupled to the input terminal of the buffer circuit 24 (ie, the gates of the transistors 240 and 241). NMOS The gate of the transistor 401 receives the control signal POC2, the drain of which is coupled to the node N21, and the source thereof is coupled to the input terminal of the buffer circuit 24 (ie, the gates of the transistors 240 and 241 are coupled). In the embodiment of Fig. 4, the circuits and elements having the same reference numerals as in the embodiment of the second A-2C diagram operate in the power-start control phase and the stabilization phase as in the above-described embodiment of the second embodiment A-2C, The description is omitted. Only the operation of the transfer gate 40 will be described below. In the power-on control phase, the PMOS transistor 400 and the NMOS transistor 401 are turned off according to a control signal POC3 having a voltage level of 3.3 V and a control signal POC2 having a voltage level of 0 V, respectively. Therefore, the feedback circuit 104 does not provide a feedback path between the nodes N21 and N11, and thus, the feedback circuit 104 does not change the voltage level on the node N11 according to the control signal POC2. In the stabilization phase, the PMOS transistor 400 and the NMOS transistor 401 are turned on according to the control signal POC3 having a voltage level of 0 V and the control signal POC2 having a voltage level of 3.3 V, respectively. Therefore, the feedback circuit 104 provides a feedback path between the nodes N21 and N11 to change the voltage level of the control signal POC0 on the node N11 to the voltage level of the control signal POC2 according to the control signal POC2. That is 3.3V.
在上述的第2A、3、與4圖的實施例中,電源啟動控制電路10包括電阻器101。在其他實施例中,電源啟動控制電路10不具有第2A、3、與4圖的實施例中電阻器101,而以開關電路100的PMOS電晶體25所提供電阻來做為第2A、3、與4圖的實施例中的電阻器101。參閱第5圖,與第2A圖的實施例比較起來,電源啟動控制電路10不具有第2A圖的實施例中電阻器101。參閱第6圖,與第3圖的實施例比較起來,電源啟動控制電路10不具有第3圖的實施例中電阻器101。參閱第7圖,與第4圖的實施例比較起來,電源啟動控制電路10不具有第4圖的實 施例中電阻器101。 In the above embodiments of FIGS. 2A, 3, and 4, the power source start control circuit 10 includes the resistor 101. In other embodiments, the power-on control circuit 10 does not have the resistor 101 in the embodiments of FIGS. 2A, 3, and 4, but the resistors provided by the PMOS transistor 25 of the switch circuit 100 are used as the 2A, 3, Resistor 101 in the embodiment of Figure 4. Referring to Fig. 5, in comparison with the embodiment of Fig. 2A, the power-on control circuit 10 does not have the resistor 101 of the embodiment of Fig. 2A. Referring to Fig. 6, in comparison with the embodiment of Fig. 3, the power-on control circuit 10 does not have the resistor 101 of the embodiment of Fig. 3. Referring to FIG. 7, compared with the embodiment of FIG. 4, the power-on control circuit 10 does not have the actual picture of FIG. In the embodiment, the resistor 101.
本發明雖以較佳實施例揭露如上,然其並非用以限定本發明的範圍,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可做些許的更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the scope of the present invention. Any one of ordinary skill in the art can make a few changes without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims.
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US20090206891A1 (en) * | 2007-06-13 | 2009-08-20 | Honeywell International Inc. | Power Cycling Power On Reset Circuit for Fuse Initialization Circuitry |
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