TWI637598B - Register configuration circuit - Google Patents

Abstract

A register configuration circuit includes a counter, an enabling unit, and a register. The counter has N+1 bits, and counts the pulse number of a second control signal according to a logic value of a first control signal to generate a latch enable signal and an N+1 bit The data signal, N is a positive integer and greater than or equal to 1. The decimal value corresponding to the data signal of the N+1 bits is the result counted by the counter. The register latches the logic value of the data signal of the N+1 bits according to a latch signal generated by the enabling unit to generate a register output signal of N+1 bits. The register configuration circuit can prevent signal surge phenomenon and is applied to the row tube driving chip of the LED display screen.

Description

Register configuration circuit

The invention relates to a register configuration circuit, in particular to a register configuration circuit for generating control signals of multiple bits.

The conventional light-emitting diode display screen includes a plurality of light-emitting diodes, and can be normally displayed by being driven by a plurality of row driving tube chips and a plurality of constant current source chips. As a simple example, suppose a light-emitting diode display screen includes 8 columns * 16 rows, a total of 128 light-emitting diodes; a row driver tube chip receives three control signals and an enable signal to output eight column controls Signal, the column control signals are respectively output to the anode terminals of the eight columns of light-emitting diodes; the constant current source chip includes 16 output terminals to electrically connect the cathode terminals of the 16 rows of light-emitting diodes, respectively. By enabling the row drive transistor chip with the enable signal, the three control signals are converted into the eight column control signals alternately to logic 1, so that the eight column light emitting diodes alternately emit light, and by The on-time of the 16 rows of light-emitting diodes is controlled by the constant current source wafer, and then the gray scale of the 16 light-emitting diodes in any one of the eight columns of light-emitting diodes is controlled to achieve the correct display of the entire light-emitting The entire screen of the diode display. However, the conventional line-drive tube chips are often inconsistent because of the product quality, such as power supply voltage variations and large deviations in the turn-on voltage, etc. Control and other setting options for parameter adjustment. Therefore, how to select the built-in options of these row drive transistor chips has become a problem to be solved.

Therefore, an object of the present invention is to provide a register configuration circuit that generates a control signal of multiple bits.

Therefore, the register configuration circuit of the present invention includes a counter, an enabling unit, and a register.

The counter has N + 1 bits, and receives a first control signal and a second control signal, and according to the logic value of the first control signal, the pulse number of the second control signal is counted to generate A latch enable signal and a N + 1 bit data signal. N is a positive integer and greater than or equal to 1, and the decimal value corresponding to the N + 1-bit data signal is the result of counting by the counter.

The enabling unit receives the first control signal, and is electrically connected to the counter to receive the latch enabling signal, and generates a latch signal according to the first control signal and the latch enabling signal.

The scratchpad has N + 1 bits, and is electrically connected to the enabling unit and the counter to receive the latch signal and the N + 1 bit data signal, respectively, and according to the latch signal, the The logic value of the N + 1 bit data signal is latched to generate a N + 1 bit register output signal.

In some embodiments, when the first control signal is equal to a first logic value, the counter starts counting the pulse number of the second control signal from zero.

When the counter starts counting from zero to a preset threshold, the output logic value of the latch enable signal is changed from a third logic value to a fourth logic value, and the result counted by the counter is reset Return to zero.

After the counter resets the counting result to zero, the pulse wave number of the second control signal is counted again. When the first control signal is equal to a second logic value, the counter stops counting.

In some embodiments, the third logic value is equal to logic 0, and the fourth logic value is equal to logic 1. The enabling unit includes an inverter gate and a gate. The inverter gate receives the first control signal to generate a reverse signal. The AND gate receives the reverse signal and the latch enable signal from the counter, and performs an AND operation to generate the latch signal.

In some embodiments, when the logic value of the latch signal is changed from logic 0 to logic 1, the scratchpad latches the logic value of the data signal to generate the N + 1 bit Temporary output signal.

In some embodiments, wherein the first logic value is equal to logic 1, the second logic value is equal to logic 0, the counter is triggered by the positive edge of the pulse of the second control signal to count.

In some embodiments, where N = 3, the preset threshold is equal to 8.

The effect of the present invention is that the counter counts the pulse number of the second control signal according to the logic value of the first control signal, so as to realize that the first control signal and the second control signal are not transmitting video When transmitting data, the parameter data is transmitted, and by designing the preset threshold, the counter can effectively prevent the glitch phenomenon of the first control signal and the second control signal, and can correctly generate The register outputs signals.

Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same number.

Referring to FIG. 1, an embodiment of the temporary register configuration circuit of the present invention includes a counter 1, an enabling unit 2, and a temporary register 3.

The counter 1 has N + 1 bits, and receives a first control signal A0 and a second control signal A1, and according to the logic value of the first control signal A0, the pulse number of the second control signal A1 Count to generate a latch enable signal LAT_EN and an N + 1 bit data signal DATA. N is a positive integer and greater than or equal to 1. The decimal value corresponding to the N + 1-bit data signal DATA is the result of the counter 1 counting. In this embodiment, for convenience of explanation, N = 3 is taken as an example for description, that is, DATA is DATA <3: 0>, but in other embodiments, N may also be other positive integers.

In more detail, when the first control signal A0 is equal to a first logic value, the counter 1 starts counting the pulse number of the second control signal A1 from zero. In this embodiment, the first logic value is equal to logic 1, and the counter 1 is triggered by the positive edge of the pulse of the second control signal A1 to count, but in other embodiments, it is not limited to this. 3 again, FIG. 3 is a timing diagram illustrating an example of a first control signal A0, a second control signal A1, a data signal DATA, a latch enable signal LAT_EN, a latch signal LAT_CLK, and a temporary The relationship between the register output signals REG. The value of the data signal DATA in FIG. 3 is expressed in hexadecimal. When the first control signal A0 is equal to logic 1, the counter 1 is triggered by the positive edge of the second control signal A1 and counts the second control signal A1 The number of pulses makes the decimal value corresponding to the data signal DATA be 0, 1, 2 ... 7 in order.

When the counter 1 starts counting from zero to a preset threshold, the output logic value of the latch enable signal LAT_EN is changed from a third logic value to a fourth logic value, and the counter 1 counts The results are reset to zero. In this embodiment, the third logical value is equal to logical 0, the fourth logical value is equal to logical 1, and the preset threshold is equal to 8, but in other embodiments, the third logical value and the fourth logical value It can also be logic 1 and logic 0, respectively, and the preset threshold can also be other positive integers. Referring again to FIG. 3, when the counter 1 counts to the eighth pulse number of the second control signal A1, that is, when it is triggered by the ninth positive edge, the counter 1 will latch the enable signal LAT_EN The logic value is changed from logic 0 to logic 1, and the decimal value corresponding to the data signal DATA is also changed from 7 to 0, that is, reset to zero instead of 8.

After the counter 1 resets the counting result to zero, the pulse number of the second control signal A1 is counted again. Referring again to FIG. 3, after the counter 1 resets the counting result to zero, that is, after the decimal value corresponding to the data signal DATA changes from 7 to 0, the counter 1 counts again so that the ten corresponding to the data signal DATA The carry value is then 0, 1, 2 ... 10 (that is, a in hexadecimal), 11 (that is, b in hexadecimal).

When the first control signal A0 is equal to a second logic value, the counter 1 stops counting. In this embodiment, the second logical value is equal to logic 0, but in other embodiments, it is not limited to this. Referring again to FIG. 3, when the logic value of the first control signal A0 changes from logic 1 to logic 0, the counter 1 stops counting, and the decimal value corresponding to the data signal DATA remains at 11 (that is, hexadecimal b ).

Referring to FIG. 1, the enabling unit 2 receives the first control signal A0, and is electrically connected to the counter 1 to receive the latch enable signal LAT_EN, and according to the first control signal A0 and the latch enable signal LAT_EN, This latch signal LAT_CLK is generated. Referring again to FIG. 2, in this embodiment, the enabling unit 2 includes an inverter gate (Inverter Gate) 21 and an AND gate (AND Gate) 22.

The inverter gate 21 receives the first control signal A0 to generate a reverse signal. The AND gate 22 receives the reverse signal and the latch enable signal LAT_EN from the counter 1, and performs an AND operation to generate the latch signal LAT_CLK. Referring again to FIG. 3, when the logic value of the first control signal A0 changes from logic 1 to logic 0, and the logic value of the latch enable signal LAT_EN is logic 1, the logic value of the latch signal LAT_CLK changes from logic 0 Becomes logic 1.

The register 3 has N + 1 bits, and is electrically connected to the enabling unit 2 and the counter 1 to respectively receive the latch signal LAT_CLK and the N + 1 bit data signal DATA, and according to the The latch signal LAT_CLK latches the logic value of the N + 1 bit data signal DATA to generate the N + 1 bit register output signal REG. In this embodiment, N = 3, that is, REG is REG <3: 0>.

In more detail, when the logic value of the latch signal LAT_CLK is changed from logic 0 to logic 1, the register 3 latches the logic value of the data signal DATA to generate the N + 1 bits The register output signal of the element is REG. Referring again to FIG. 3, when the logic value of the latch signal LAT_CLK changes from logic 0 to logic 1, the register output signal REG latches the logic value of the data signal DATA, so that the register output signal REG The logical value is 1011 (that is, hexadecimal b).

The following illustrates an application of the register configuration circuit of the present invention. A light-emitting diode display screen includes a plurality of light-emitting diodes, and can be driven by a plurality of row drive tube chips and a plurality of constant current source chips. Display the screen normally. For the convenience of explanation, it is simply assumed that the light-emitting diode display screen includes 8 columns * 16 rows, a total of 128 light-emitting diodes, so only one row driver tube chip is needed, that is, a constant current source chip.

The row drive tube wafer receives a first control signal (A0), a second control signal (A1), a third control signal (A3), and an enable signal to output eight column control signals. The control signals are respectively output to the anode ends of the eight columns of light-emitting diodes. The constant current source wafer includes 16 output terminals to electrically connect the cathode terminals of the 16 rows of light-emitting diodes, respectively. In order to solve the problem of different quality of the line drive tube chip, the line drive tube chip has built-in or external function modules, such as: selection of erasing mode, control of erasing voltage, etc., and requires multiple bits Control signal to select the setting options of these function modules.

The first control signal (A0), the second control signal (A1), and the third control signal (A3) are generated by a light-emitting diode receiving card, and are displayed on the light-emitting diode display screen. Between the displayed different frames, the first control signal (A0) and the second control signal (A1) can use the idle time of transmitting video data to transmit the setting parameters of these function modules. In other words, the video data is used to make the light-emitting diodes of the light-emitting diode display normally emit light, and the time when the light-emitting diodes do not need to emit light is received by the register configuration circuit of the invention The first control signal (A0) and the second control signal (A1) can convert the setting parameters into the output signal of the register in the form of the number of pulses of the second control signal, and then output to these function modes group.

In summary, the counter counts the number of pulses of the second control signal according to the logic value of the first control signal to realize that the first control signal and the second control signal are not transmitting video data When the parameter data is transmitted, and the design of the preset threshold value, the counter can effectively prevent the glitch phenomenon of the first control signal and the second control signal, and can correctly generate the The register outputs a signal, so it can indeed achieve the purpose of the invention.

However, the above are only examples of the present invention, and the scope of implementation of the present invention cannot be limited by this, any simple equivalent changes and modifications made according to the scope of the patent application of the present invention and the content of the patent specification are still classified as Within the scope of the invention patent.

1‧‧‧Counter
2‧‧‧Enable unit
21‧‧‧Inverter brake
22‧‧‧ and gate
3‧‧‧register
A0‧‧‧ First control signal
A1‧‧‧Second control signal
LAT_EN‧‧‧Latch enable signal
LAT_CLK‧‧‧Latch signal
DATA‧‧‧Data signal
REG‧‧‧register output signal

Other features and functions of the present invention will be clearly presented in the embodiment with reference to the drawings, in which: FIG. 1 is a block diagram illustrating an embodiment of the register configuration circuit of the present invention; FIG. 2 is a circuit diagram, Illustrate an enabling unit of this embodiment; and FIG. 3 is a timing diagram illustrating the relationship between multiple signals of this embodiment.

Claims (6)

A register configuration circuit includes: a counter having N + 1 bits, and receiving a first control signal and a second control signal, and controlling the second control according to the logic value of the first control signal The pulse number of the signal is counted to generate a latch enable signal and a N + 1 bit data signal, N is a positive integer and greater than or equal to 1, the N + 1 bit data signal corresponds to ten The carry value is the result of counting by the counter; an enabling unit receives the first control signal and is electrically connected to the counter to receive the latch enabling signal, and according to the first control signal and the latch enabling signal To generate a latch signal; and a temporary register with N + 1 bits, and electrically connect the enabling unit and the counter to receive the latch signal and the N + 1 bit data signal, respectively And, according to the latch signal, the logic value of the N + 1 bit data signal is latched to generate a N + 1 bit output signal of the temporary register. The temporary memory configuration circuit according to claim 1, wherein when the first control signal is equal to a first logic value, the counter starts counting the pulse number of the second control signal from zero, and when the counter is When zero starts to count to a preset threshold, the output logic value of the latch enable signal is changed from a third logic value to a fourth logic value, and the result counted by the counter is reset to zero. After the counter resets the counting result to zero, the pulse number of the second control signal is counted again, and when the first control signal is equal to a second logic value, the counter stops counting. The scratchpad configuration circuit according to claim 2, wherein the third logic value is equal to logic 0, the fourth logic value is equal to logic 1, and the enabling unit includes: an inverter gate to receive the first control Signal to generate a reverse signal; and a AND gate to receive the reverse signal and the latch enable signal from the counter, and perform an AND operation to generate the latch signal. The scratchpad configuration circuit as described in claim 3, wherein when the logic value of the latch signal is changed from logic 0 to logic 1, the scratchpad latches the logic value of the data signal to generate the N +1 bit register output signal. The register configuration circuit according to claim 4, wherein the first logic value is equal to logic 1, the second logic value is equal to logic 0, and the counter is triggered by the positive edge of the pulse of the second control signal to count. The temporary memory configuration circuit according to claim 5, wherein, when N = 3, the preset threshold is equal to 8.