CN116386556A - Display panel drive circuit - Google Patents

Abstract

The invention provides a driving circuit of a display panel, which comprises a driving signal generating circuit for generating a driving signal in a frame period to drive a display element of the display panel, wherein the driving signal has at least one first on pulse width, at least one first off pulse width, at least one second on pulse width and at least one second off pulse width, the first on pulse width is larger than the second on pulse width, and the first off pulse width is smaller than the second off pulse width. The driver can reduce electromagnetic interference and improve display quality.

Description

Display panel drive circuit

technical field

The present invention relates to a driving circuit, in particular to a driving circuit of a display panel.

Background technique

Display devices have become necessary equipment for electronic products for displaying information. Display devices have been developed from liquid crystal display devices to submillimeter light emitting diode (Mini LED) display devices and micro light emitting diode (Micro LED) display devices. As a display element, the light emitting diode can improve the display quality of the display device. The way of driving the above-mentioned light emitting diodes in the known technology will cause high electromagnetic interference (Electromagnetic Interference, EMI), which will affect the display quality.

Based on the above, the present invention provides a driving circuit for a display panel, which can reduce EMI and improve display quality.

Contents of the invention

An object of the present invention is to provide a driving circuit for a display panel, which changes the frequency of a driving signal for driving a display element during a frame period, so as to reduce electromagnetic interference and improve display quality.

The present invention provides a driving circuit for a display panel, which includes a driving signal generating circuit, the driving signal generating circuit generates a driving signal during a frame period to drive a display element of the display panel, and the driving signal has at least one first pulse wave Width, at least one second pulse width, at least one third pulse width, the first pulse width is greater than the second pulse width and the third pulse width, the second pulse width is greater than the third pulse width. The driving signal generation circuit firstly generates the second pulse width, and then generates the first pulse width or the third pulse width at a time in the frame period.

The present invention further provides a driving circuit for a display panel, which includes a driving signal generating circuit. The driving signal generating circuit generates a driving signal during a frame period to drive a display element of the display panel. The driving signal has at least one first conductive On-pulse width and at least one first cut-off pulse width, at least one second on-pulse width, at least one second off-pulse width, the first on-pulse width is greater than the second on-pulse width, the second on-pulse width A cut-off pulse width is smaller than a second cut-off pulse width.

The present invention further provides a driving circuit for a display panel, which includes a driving signal generating circuit, and the driving signal generating circuit generates a driving signal having a plurality of first pulse widths during an F-1 frame period to drive the display panel. a display element, and generate driving signals with a plurality of second pulse widths during an F frame period to drive the display element. The second pulse widths are different from the first pulse widths, and the time during the F-1 frame is the same as the time during the F frame, where F is an integer greater than 2.

Description of drawings

FIG. 1 is a schematic diagram of an embodiment of the drive architecture of the present invention;

Fig. 2 is a block diagram of an embodiment of the driver and display element of the present invention;

Fig. 3 is a block diagram of an embodiment of the controller and the driver of the present invention;

Fig. 4 is the block diagram of an embodiment of the driving circuit of the present invention;

5 is a schematic diagram of a first embodiment of a driving signal;

6 is a schematic diagram of a second embodiment of a driving signal;

7 is a schematic diagram of a third embodiment of a driving signal;

8 is a schematic diagram of a fourth embodiment of a driving signal;

9 is a schematic diagram of a fifth embodiment of a driving signal;

10 is a schematic diagram of a sixth embodiment of a driving signal;

11 to 13 are schematic diagrams of seventh to ninth embodiments of driving signals, respectively.

Detailed ways

In order to have a further understanding and understanding to the characteristics of the present invention and the achieved effects, the following examples and explanations are provided:

Certain terms are used in the specification and claims to refer to specific components. However, those skilled in the technical field of the present invention should understand that manufacturers may use different terms to refer to the same component. Moreover, the specification and claims The difference in name is not used as a way to distinguish components, but the difference in overall technology of components is used as a criterion for distinguishing. "Includes" mentioned throughout the specification and claims is an open term, so it should be interpreted as "including but not limited to". Furthermore, the term "coupled" herein includes any direct and indirect means of connection. Therefore, if it is described that a first device is coupled to a second device, it means that the first device may be directly connected to the second device, or may be indirectly connected to the second device through other devices or other connection means.

Please refer to the first figure and the second figure, the first figure is a schematic diagram of an embodiment of the driving architecture of the present invention, and the second figure is a block diagram of an embodiment of the driver and the display element of the present invention. As shown in the figure, the driving architecture includes a controller 1 and multiple drivers 2 to drive multiple pixels of the display panel 10 to display images. The drivers 2 are arranged in multiple columns, and each driver 2 is coupled to a plurality of display elements 4 to drive the display elements 4 to emit light. In an embodiment of the present invention, the display elements 4 can be submillimeter LEDs or micro LEDs. The controller 1 is coupled to the drivers 2 and transmits an input data Din, a timing signal DCK, a clock signal PWMCLK and an enable signal EN to the drivers 2 . In an embodiment of the present invention, the controller 1 can be an independent chip. Since the drivers 2 are arranged in multiple columns, the pixels arranged in rows and columns on the display panel 10 can be controlled.

Please refer to FIG. 3 , which is a block diagram of an embodiment of the controller and the driver of the present invention. As shown in the figure, each driver 2 includes an enabling circuit 6 , a storage circuit 7 and a driving circuit 9 . The enabling circuit 6 receives the enabling signal EN, and enables the storage circuit 7 to receive the input data Din according to the timing signal DCK according to the enabling signal EN. The driving circuit 9 is coupled to the storage circuit 7 and the display elements 4, and generates a plurality of driving signals according to the input data Din and the clock signal PWMCLK received by the storage circuit 7 to drive the display elements 4 to generate light to display images. . After the first driver 2 drives these display elements 4, the enable circuit 6 of the first driver 2 will disable the storage circuit 7 of the first driver 2, and send an enable signal EN to the second driver 2. The enabling circuit 6 is used to perform the above actions to drive the display elements 4 coupled to the second driver 2 , and so on.

Please refer to FIG. 4 , which is a block diagram of an embodiment of the driving circuit of the present invention. As shown in the figure, the storage circuit 7 is coupled to the enabling circuit 6 and receives the input data Din and a timing signal DCK. The enabling circuit 6 enables the storage circuit 7 according to the received enabling signal, and drives the storage circuit 7 to receive according to the timing signal DCK. The input data Din is input, and the input data Din is stored. The driving circuit 9 includes a driving signal generating circuit, which includes a plurality of comparison circuits 91 , a counter 93 , and a plurality of level conversion circuits 95 . The comparison circuits 91 are coupled to the storage circuit 7 and the counter 93 . The counter 93 receives the clock signal PWMCLK, and counts according to the clock signal PWMCLK to output a count signal, and the count signal changes as the counter 93 counts. Each comparison circuit 91 receives the count signal and the pixel data of the input data Din stored in the storage circuit 7, and compares the count signal with the pixel data. When the pixel data is greater than the count signal, the comparison circuit 281 outputs a drive signal with a drive level. For example high level. In another embodiment of the present invention, when the pixel data is less than the count signal, the comparison circuit 91 outputs a driving signal with a driving level. The level conversion circuits 95 are coupled to the comparison circuits 91 and convert the driving signals output by the comparison circuits 91 . In an embodiment of the present invention, the level conversion circuit 95 may not be needed. One end of these display elements 4 is coupled to a supply voltage VDD, a switch MOS is coupled between the other end of these display elements R, G, B and a ground end, the driving signal generated by the comparison circuit 9 is used to control the switch MOS , so as to drive current to flow through the display elements 4 to generate light. It can be known from the above description that the time during which the comparison circuit 91 continues to generate the driving level of the driving signal is the driving time, that is, the time for driving the display element 4 , which determines the brightness of the display element 4 .

Please refer to FIG. 5 , which is a schematic diagram of an embodiment of a driving signal. As shown in the figure, the driving signal has an on-pulse width (high level) and an off-pulse width (low level) in one frame period, and the on-pulse width determines the time for the display element 4 to generate light.

Please refer to FIG. 6 , which is a schematic diagram of another embodiment of the driving signal. As shown in the figure, the driving signal has multiple on-pulse widths and multiple off-pulse widths in one frame period. The driving signal shown in the sixth figure is better than the driving signal shown in the fifth figure, which can reduce the display Flicker phenomenon of element 4. Similarly, the display element is driven to display for 0.1 second, and the frame period is 0.2 second. The driving signal in the fifth figure drives the display element to be continuously on for 0.1 second, and is continuously off for 0.1 second, so it is easy to generate flicker. If the driving signal shown in Figure 6 has a pulse width of 10, it means that 0.1 seconds is divided into 10 pulse widths, and the display elements are respectively driven to display for 0.01 seconds. In this way, during the frame period, it is still bright for 0.1 seconds, but it can be reduced flashing. However, continuously driving the display element with the same on-pulse width will cause higher electromagnetic interference.

Please refer to FIG. 7 , which is a schematic diagram of the third embodiment of the driving signal. As shown in the figure, the driving circuit 9 generates a driving signal during one frame period. The driving signal has a plurality of first pulse widths and a plurality of second pulse widths. The first pulse width is greater than the second pulse width, which means driving The frequency of the clock signal PWMCLK received by the circuit 9 is the first frequency f1 or the second frequency f2, and the drive circuit 9 generates the first pulse width according to the clock signal PWMCLK with the first frequency, and generates the first pulse width according to the clock signal with the second frequency The signal PWMCLK generates the second pulse width. The first frequency f1 is smaller than the second frequency f2. Since the frequency of the driving signal changes within a frame period, electromagnetic interference can be reduced. The counter 91 counts based on a fixed number of clocks to generate the first pulse width and the second pulse width. For example, the counter 91 counts again every time the clock signal PWMCLK reaches 4096.

Please refer to FIG. 8 , which is a schematic diagram of the fourth embodiment of the driving signal. As shown in the figure, the driving circuit 9 generates a driving signal during one frame period, and the driving signal has multiple first pulse widths, multiple second pulse widths, and multiple third pulse widths, and the first pulse width is greater than the first pulse width. The second pulse width and the third pulse width, the second pulse width is greater than the third pulse width, which means that the frequency of the clock signal PWMCLK received by the drive circuit 9 is the first frequency f1, the second frequency f2 or the third frequency f3, the driving circuit 9 generates the first pulse width according to the clock signal PWMCLK having the first frequency f1, and generates the second pulse width according to the clock signal PWMCLK having the second frequency f2, and the driving circuit 9 generates the second pulse width according to the clock signal having the third frequency The clock signal PWMCLK of f3 generates a third pulse width. The first frequency f1 is lower than the second frequency f2 and the third frequency f3, and the third frequency f3 is lower than the second frequency f2. In one embodiment of the present invention, at a certain time within the frame period, the second pulse width is generated first, and then the first pulse width or the third pulse width is generated successively, that is, the first pulse width is first generated according to the second frequency. Two pulse widths, and then generate a first pulse width or a third pulse width according to the first frequency or the third frequency. The counter 91 counts based on a fixed number of clocks to generate a third pulse width.

In one embodiment of the present invention, the driving signal generation circuit sequentially generates N first pulse widths of the first pulse widths, and the second pulse widths within the frame period and outside a certain time. The P second pulse widths of these third pulse widths, the Q third pulse widths of these third pulse widths, N, P, and Q are integers greater than 0, that is, the first, second or third pulse waves can be continuously generated width. Alternatively, Q third pulse widths of the third pulse widths, P second pulse widths of the second pulse widths, and N first pulse widths of the first pulse widths are sequentially generated. pulse width.

The driving circuit 9 of the present invention generates a driving signal during a plurality of frame periods, and the time of the frame periods is the same, and the driving signal has at least one of the first, second and third pulse widths. That is, the drive signal is generated during an F-1 frame period, an F frame period, and an F+1 frame period, and the drive signal has a first pulse width, a second pulse width, and a third pulse width. At least one, the time of the F-1th frame period, the time of the Fth frame period and the time of the F+1th frame period are the same, and F is an integer greater than 2.

Please refer to FIG. 9 , which is a schematic diagram of a fifth embodiment of the driving signal. As shown in the figure, during one frame period, the frequency of the clock signal PWMCLK changes from the first frequency f1 to the second frequency f2 with time, and then changes from the second frequency f2 to the first frequency f1 with time, so that During the period when the frequency of the clock signal PWMCLK is changed from the first frequency f1 to the second frequency f2, the drive circuit generates the first on-pulse width and the first cut-off pulse width according to the clock signal PWMCLK, and the frequency of the clock signal PWMCLK During the transition from the second frequency f2 to the first frequency f1, a second on-pulse width and a second off-pulse width are generated according to the clock signal PWMCLK. The first on-pulse width is greater than the second on-pulse width, and the first off-pulse width is smaller than the second off-pulse width. The first on-pulse width is equal to the second off-pulse width, and the second on-pulse width is equal to the first off-pulse width. The first on-pulse width is equal to the second off-pulse width, and the second on-pulse width is equal to the first off-pulse width. The counter 91 counts based on a fixed number of clocks to generate a first on-pulse width, a first off-pulse width, a second on-pulse width, and a second off-pulse width.

Please refer to FIG. 10 , which is a schematic diagram of a sixth embodiment of the driving signal. As shown in the figure, during one frame period, the frequency of the clock signal PWMCLK is changed from the first frequency f1 to the third frequency f3 and then changed to the second frequency f2, then changed from the second frequency f2 to the third frequency f3, and then changed to to the first frequency f1 for the driving circuit to generate a driving signal with a variable pulse width, and the driving signal is similar to the embodiment in the ninth figure.

Please refer to the eleventh figure to the thirteenth figure, the driving circuit 9 of the present invention generates driving signals during a plurality of frame periods, and the time of these frame periods is the same to drive the same display element, and the driving signal generated during each frame period The driving signals have the same pulse width, but the pulse widths in different frame periods are different, which means that the driving circuit generates the driving signals in different frame periods according to three clock signals PWMCLK with different frequencies. For example, the eleventh figure is during the F-1 frame period, the twelfth figure is during the first F frame period, and the thirteenth figure is during the F+1 frame period, and the driving signals of the three have the first pulse width respectively. , the second pulse width and the third pulse width, the time of the F-1th frame period, the time of the F-th frame period and the time of the F+1-th period are the same, and F is an integer greater than 2.

But the above is only an embodiment of the present invention, and is not used to limit the scope of the present invention. Therefore, all equivalent changes and modifications made according to the structure, characteristics and spirit described in the scope of the patent application of the present invention are valid. Should be included in the patent application scope of the present invention.

Claims (17)

1. A driving circuit of a display panel, comprising:

a driving signal generating circuit for generating a driving signal in a frame period to drive a display element of the display panel, wherein the driving signal has at least one first pulse width, at least one second pulse width and at least one third pulse width, the first pulse width is larger than the second pulse width and the third pulse width, and the second pulse width is larger than the third pulse width;

the driving signal generating circuit generates the second pulse width at a time within the frame period, and then generates the first pulse width or the third pulse width.

2. The driving circuit of claim 1, wherein the driving signal generating circuit generates the second pulse width first, then generates the first pulse width, and then generates the third pulse width during the time of the frame.

3. The driving circuit of claim 1, wherein the driving signal generating circuit generates the second pulse width first, then generates the third pulse width, and then generates the first pulse width during the time of the frame.

4. The driving circuit of claim 1, wherein the driving signal generating circuit generates the first pulse width, the second pulse width and the third pulse width according to a fixed number of a plurality of clocks.

5. The driving circuit of claim 4, wherein the driving signal generating circuit generates the driving signal according to a clock signal, the clock signal having a plurality of clocks, the clock signal having a frequency of a first frequency, a second frequency or a third frequency, the driving signal generating circuit generating the first pulse width according to the clock signal having the first frequency, the second pulse width according to the clock signal having the second frequency, and the third pulse width according to the clock signal having the third frequency.

6. The driving circuit of claim 1, wherein the at least one first pulse width comprises a plurality of first pulse widths, the at least one second pulse width comprises a plurality of second pulse widths, the at least one third pulse width comprises a plurality of third pulse widths, the driving signal generating circuit sequentially generates N first pulse widths of the first pulse widths, P second pulse widths of the second pulse widths, Q third pulse widths of the third pulse widths within the frame period and outside the frame period, N, P, Q is greater than an integer of 0.

7. The driving circuit of claim 1, wherein the at least one first pulse width comprises a plurality of first pulse widths, the at least one second pulse width comprises a plurality of second pulse widths, the at least one third pulse width comprises a plurality of third pulse widths, the driving signal generating circuit sequentially generates Q third pulse widths of the third pulse widths, P second pulse widths of the second pulse widths, N first pulse widths of the first pulse widths within the frame period and outside the frame period, N, P, Q is an integer greater than 0.

8. The driving circuit of claim 1, wherein the frame period is an F-1 frame period, the driving signal generating circuit generates the driving signal in an F-1 frame period and an f+1 frame period, the driving signal having at least one of the first pulse width, the second pulse width and the third pulse width, the time of the F-1 frame period, the time of the F frame period and the time of the f+1 frame period being the same, F being an integer greater than 2.

9. A driving circuit of a display panel, comprising:

the driving signal generating circuit generates a driving signal in a frame period to drive a display element of the display panel, wherein the driving signal has at least one first on pulse width, at least one first off pulse width, at least one second on pulse width and at least one second off pulse width, the first on pulse width is larger than the second on pulse width, and the first off pulse width is smaller than the second off pulse width.

10. The driving circuit of claim 9, wherein the first on pulse width is equal to the second off pulse width, and the second on pulse width is equal to the first off pulse width.

11. The driving circuit of claim 9, wherein the first on pulse width is equal to the second off pulse width, and the second on pulse width is equal to the first off pulse width.

12. The driving circuit of claim 9, wherein the driving signal generating circuit generates the first pulse width and the second pulse width according to a fixed number of a plurality of clocks.

13. The driving circuit of claim 12, wherein the driving signal generating circuit generates the driving signal according to a clock signal, the clock signal has a plurality of clocks, a frequency of the clock signal is changed from a first frequency to a second frequency over time, and then is changed from the second frequency to the first frequency over time, the second frequency is higher than the first frequency, during the period that the frequency of the clock signal is changed from the first frequency to the second frequency, the driving signal generating circuit generates the first on pulse width and the first off pulse width according to the clock signal, and during the period that the frequency of the clock signal is changed from the second frequency to the first frequency, the second on pulse width and the second off pulse width according to the clock signal.

14. A driving circuit of a display panel, comprising:

a driving signal generating circuit for generating a driving signal having a plurality of first pulse widths to drive a display element of the display panel during an F-1 frame period and generating the driving signal having a plurality of second pulse widths to drive the display element during an F frame period;

the second pulse widths are different from the first pulse widths, the time of the F-1 frame period and the time of the F frame period are the same, and F is an integer greater than 2.

15. The driving circuit of claim 14, wherein the driving signal generating circuit generates the driving signal having a plurality of third pulse widths in an f+1 frame period to drive the display device, the third pulse widths being different from the first pulse widths and the second pulse widths, the time during the F-1 frame period, the time during the F frame period, and the time during the f+1 frame period being the same.

16. The driving circuit of claim 15, wherein the driving signal generating circuit generates the first pulse widths, the second pulse widths, and the third pulse widths according to a fixed number of clocks.

17. The driving circuit of claim 16, wherein the driving signal generating circuit generates the driving signal according to a clock signal, the clock signal having a plurality of clocks, the clock signal having a frequency of a first frequency, a second frequency or a third frequency, the driving signal generating circuit generating the first pulse widths according to the clock signal having the first frequency, the second pulse widths according to the clock signal having the second frequency, and the third pulse widths according to the clock signal having the third frequency.

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