TWI634636B - Semiconductor structure - Google Patents

Abstract

A semiconductor structure includes an insulating layer, a plurality of stepped vias, and a patterned circuit layer. The insulating layer includes an upper surface and a lower surface opposite to the upper surface. The stepped vias are disposed on the insulating layer to electrically conduct the upper surface and the lower surface. Each of the stepped vias includes a top cover portion and a connection portion connected to the top cover portion. The top cover portion is disposed on the upper surface and a top surface of the top cover portion is coplanar with the upper surface. A minimum diameter of the top cover portion is larger than a maximum diameter of the connecting portion. The patterned circuit layer is disposed on the upper surface and is electrically connected to the stepped vias.

Description

Semiconductor structure

The present invention relates to a semiconductor structure, and more particularly, to a semiconductor structure having a stepped via hole.

In recent years, with the rapid development of electronic technology and the rise of the semiconductor industry, more user-friendly and better-functioning electronic products have been constantly introduced, and they have been designed to be light, thin, short, and small. As current wafers, semiconductor components, or circuit boards are all aimed at achieving the goal of high integration, the line width and line spacing between integrated circuits inside them have become smaller and smaller, even reaching the level of nanometers. . However, as the line width and line pitch become smaller, the size of the vias is also limited, which is a great process test for deeper vias.

In addition, because the degree of bonding between the material of the wires and vias (for example: copper) and the dielectric material with a low dielectric constant is not ideal, delamination, damage, or Fracture phenomenon. In addition, due to the difference in the coefficient of thermal expansion (CTE) between the dielectric material and the conductive material, the joint between the dielectric material and the conductive material is easily damaged by thermal stress, causing warpage and deformation. (warpage) or delamination, thereby reducing the reliability and service life of the semiconductor structure.

The invention provides a semiconductor structure, which can improve the reliability of the semiconductor structure and effectively reduce the diameter of the via hole.

The semiconductor structure of the present invention includes a first insulating layer, a plurality of first stepped vias, and a first patterned circuit layer. The first insulating layer includes a first upper surface and a first lower surface opposite to the first upper surface. The first stepped vias are disposed on the first insulating layer to electrically conduct the first upper surface and the first lower surface. Each of the first stepped vias includes a top cover portion and a connection portion connected to the top cover portion. The top cover portion is disposed on the first upper surface and a top surface of the top cover portion is coplanar with the first upper surface. A minimum diameter of the top cover portion is greater than a maximum diameter of the connection portion. The first patterned circuit layer is disposed on the first upper surface and is electrically connected to the first stepped via.

In an embodiment of the present invention, a bottom surface of the first patterned circuit layer is lower than a first upper surface.

In an embodiment of the present invention, a diameter of the above-mentioned cover portion is formed by mechanical drilling to form a vertical hole wall, and the connecting portion is formed by a laser process.

In an embodiment of the present invention, the first stepped through hole further includes a sub-connecting portion connected to the connecting portion, and the connecting portion is connected between the top cover portion and the sub-connecting portion, and a minimum of the connecting portion The diameter is larger than a maximum diameter of the sub-connecting portion.

In an embodiment of the present invention, the first stepped through hole further includes a base portion disposed on the first lower surface, the connecting portion is connected between the top cover portion and the base portion, and a minimum diameter of the base portion Larger than the maximum diameter of the connection.

In an embodiment of the present invention, the base portion is formed with a vertical hole wall by mechanical drilling.

In an embodiment of the present invention, the material of the first insulating layer includes a selectively-platable insulating material, which includes a non-conductive metal composite or a generally used insulating material.

In an embodiment of the present invention, the material of the first insulating layer includes epoxy resin, polyester, acrylate, fluoropolymer, polyphenylene oxide, polyimide, phenol resin, and polyfluorene. , Silicon polymer, BT resin (Bismaleimide-Triazine modified epoxy resin), cyanate polyester, polyethylene, polycarbonate resin, acrylonitrile-butadiene-styrene copolymer, polyethylene terephthalate (PET), polybutylene terephthalate (PBT), liquid crystal polyester (LCP), polyamide (PA), nylon 6, copolyacetal (POM), polyphenylene sulfide (PPS) ), Polycarbonate (PC), polymethacrylate (PMMA), ABS resin (Acrylonitrile Butadiene Styrene, ABS) or cyclic olefin copolymer (COC).

In an embodiment of the present invention, the metal in the non-conductive metal composite includes zinc, copper, silver, gold, nickel, palladium, platinum, cobalt, rhodium, iridium, indium, iron, manganese, aluminum, and chromium , Tungsten, vanadium, tantalum, titanium, or any combination thereof.

In an embodiment of the present invention, the semiconductor structure further includes a second insulating layer, a second patterned circuit layer, and a plurality of second stepped vias. The second insulating layer includes a second upper surface and a second lower surface opposite to the second upper surface. The second insulating layer is stacked on the first insulating layer with the second lower surface. The second patterned circuit layer is disposed on the second upper surface. The second stepped via is disposed on the second insulating layer to electrically conduct the first patterned circuit layer and the second patterned circuit layer.

In an embodiment of the invention, a material of the first insulating layer includes silicon or glass.

In an embodiment of the present invention, the semiconductor structure further includes a first wafer including an active surface and a back surface opposite to the active surface. The first insulating layer covers the active surface of the first wafer and exposes the back surface. The first step The through-hole is connected between the first upper surface and the active surface to electrically connect the first patterned circuit layer and the first chip.

In an embodiment of the present invention, the semiconductor structure further includes a plurality of solder balls disposed on the first upper surface and electrically connected to the first pattern circuit layer.

In an embodiment of the present invention, the semiconductor structure further includes a first chip and a first reconfiguration circuit layer. The first wafer includes a first active surface and a first back surface opposite to the first active surface. The first insulating layer covers the first back surface of the first wafer, and the first lower surface exposes the first active surface. The first reconfiguration circuit layer is disposed on the first lower surface and is electrically connected to the first active surface. The first stepped vias penetrate the first insulation layer to connect the first patterned circuit layer and the first reconfiguration circuit layer.

In an embodiment of the present invention, the first stepped through hole further includes a base portion disposed on the first lower surface, the connecting portion is connected between the top cover portion and the base portion, and a minimum diameter of the base portion Larger than the maximum diameter of the connection.

In an embodiment of the present invention, the semiconductor structure further includes a plurality of solder balls disposed on the first reconfiguration circuit layer to electrically connect the first chip.

In an embodiment of the present invention, the semiconductor structure further includes a second wafer, a second insulating layer, a second reconfiguration circuit layer, and a plurality of solder balls. The second chip includes a second active surface and a second back surface opposite to the second active surface. The second insulating layer includes a second upper surface and a second lower surface opposite to the second upper surface. The second insulating layer covers the second back surface of the second wafer, and the second lower surface exposes the second active surface. The second reconfiguration circuit layer is disposed on the second lower surface and is electrically connected to the second active surface. The solder ball is connected between the first insulation layer and the second reconfiguration circuit layer to electrically connect the first patterned circuit layer and the second reconfiguration circuit layer.

Based on the above, the semiconductor structure of the present invention uses at least two laser processes or at least one mechanical drilling plus at least one laser process to drill in stages to form stepped vias to reduce each laser drilling. Therefore, the maximum diameter of the stepped vias can be reduced without reducing the depth of the stepped vias, thereby increasing the density of the circuit layout of the semiconductor structure. In addition, because mechanical drilling has the advantages of fast speed and consistent hole diameter, using its advantages in combination with the laser process can achieve cost savings and size control. In addition, the stepped via formed by this process has a stepped appearance, and the stepped appearance can increase the bonding force between the stepped via and the insulating layer to prevent the stepped via and the insulating layer The occurrence of delamination between them can further improve the reliability of the semiconductor structure.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention. Referring to FIG. 1, in this embodiment, the semiconductor structure 100 includes a first insulating layer 110, a plurality of first stepped vias 120, and a first patterned circuit layer 130. The first insulating layer 110 includes a first upper surface 112 and a first lower surface 114 opposite to the first upper surface 112. The first stepped via 120 is disposed on the first insulating layer 110 to electrically conduct the first upper surface 112 and the first lower surface 114. In this embodiment, the first stepped through hole 120 may be formed by laser drilling or a combination of mechanical drilling and laser drilling.

Generally speaking, due to the limitation of the laser process, the aspect ratio of vias formed by lasers cannot exceed 3: 1. In other words, the depth of the vias can only reach the maximum diameter of the vias at most. Three times as much as mechanical drilling due to strength limitations due to size, can not be too deep drilling. Therefore, as the depth of the via becomes deeper, its maximum diameter will increase accordingly, which will occupy more space in the semiconductor structure, which is contrary to the current goal of semiconductor components toward high-level circuit accumulation. In view of this, in this embodiment, the first stepped through hole 120 may be formed by at least two laser drilling processes or at least one mechanical drilling process plus at least one laser process in stages to reduce each laser The depth of the drilling holes can reduce the maximum diameter of the first stepped via 120 without shortening the depth of the first stepped via 120, thereby increasing the density of the circuit layout of the semiconductor structure 100.

Therefore, as shown in FIG. 1, the first stepped through hole 120 formed according to the above manufacturing method may include a top cover portion 122 and a connection portion 124 connected to the top cover portion 122. The top cover portion 122 is disposed on the first upper surface 112 of the first insulating layer 110 and the top surface of the top cover portion 122 is coplanar with the first upper surface 112. The minimum diameter of the top cover portion 122 is greater than the maximum diameter of the connection portion 124. That is, the diameters of the top cover portion 122 and the connection portion 124 have a step difference so that the first stepped through hole 120 has a stepped shape. This stepped appearance can also increase the bonding force between the first stepped via hole 120 and the first insulating layer 110 to prevent delamination between the first stepped via hole 120 and the first insulating layer 110. .

In detail, in this embodiment, the first stepped through hole 120 may be formed by first drilling through a depth from the first upper surface 112 to the bottom of the top cover portion 122 by mechanical drilling or laser, and then continuing to The laser is drilled from the bottom of the top cover portion 122 to the bottom of the connection portion 124 (the first lower surface 114 in this embodiment). It should be noted here that the hole wall of a hole formed by mechanical drilling is substantially vertical, that is, if the top cover portion 122 is formed by mechanical drilling, the diameter of the top and bottom of the top cover portion 122 may be Substantially the same, and the holes formed by laser drilling are generally funnel-shaped, that is, if the top cover portion 122 and / or the connecting portion 124 are formed by laser drilling, the top cover portion 122 and / or The diameter of the top of the connection portion 124 may be larger than the diameter of the bottom thereof.

In this embodiment, the first patterned circuit layer 130 is disposed on the first upper surface 112 of the first insulating layer 110 and is electrically connected to the first stepped via 120. Of course, the first patterned circuit layer 130 can be disposed on the first upper surface 112 and the first lower surface 114 of the first insulating layer 110 at the same time, and the first stepped via 120 can be used to electrically connect the upper and lower surfaces 112, 114 的 first patterned circuit layer 130. In this embodiment, the material of the first insulating layer 110 includes a selectively-platable insulating material or a generally-used insulating material, which includes a non-conductive metal composite. Thus, in this embodiment, the first insulating layer 110 can be used for selection. With the characteristic of electroless plating, a first patterned circuit layer 130 as shown in FIG. 1 is formed directly on the first upper surface 112. In this embodiment, the selectively plated insulating material may include epoxy resin, polyester, acrylate, fluoropolymer, polyphenylene oxide, polyimide, phenolic resin, polyfluorene, and silicon polymerization. Resin, BT resin (Bismaleimide-Triazine modified epoxy resin), cyanate polyester, polyethylene, polycarbonate resin, acrylonitrile-butadiene-styrene copolymer, polyethylene terephthalate (PET), Polybutylene terephthalate (PBT), liquid crystal polyester (LCP), polyamidoamine (PA), nylon 6, copolyacetal (POM), polyphenylene sulfide (PPS), polycarbonate (Polycarbonate, PC), polymethacrylate (PMMA), ABS resin (Acrylonitrile Butadiene Styrene, ABS) or cyclic olefin copolymer (COC), etc. Metals in non-conductive metal composites can include zinc, copper, silver, gold, nickel, palladium, platinum, cobalt, rhodium, iridium, indium, iron, manganese, aluminum, chromium, tungsten, vanadium, tantalum, titanium, or Any combination.

In detail, the step of selectively plating on the first upper surface 112 of the first insulating layer 110 to form the first patterned circuit layer 130 may include: using a laser on the first upper surface 112 of the first insulating layer 110. A line trench corresponding to the first patterned circuit layer 130 is carved along a path to form the first patterned circuit layer 130, so that the non-conductive metal compound in the line trench is destroyed and the reduced metallization is released. Highly active heavy metal nucleus, or roughening the surface in the trench to adsorb the seed crystals in the plating solution, and then select the selective plating and electroplating dielectric material after laser The first patterned circuit layer 130 is formed by electroplating to directly plate and electroplat the circuit grooves. Therefore, the first patterned circuit layer 130 formed according to the above process is embedded in the first upper surface 112 of the first insulating layer 110, and the first upper surface 112 of the first insulating layer 110 exposes the first patterned circuit layer. Top of 130.

In addition, in this embodiment, a laser groove is directly etched on the first upper surface 112 of the first insulating layer 110 to correspond to the first patterned circuit layer 130, and plating and plating are directly performed on the circuit groove. The first patterned circuit layer 130 is formed. Therefore, the bottom surface of the first patterned circuit layer 130 may be lower than the first upper surface 112 of the first insulating layer 110. In addition, the lower surface of the various first patterned circuit layers formed directly on the surface of the first insulating layer 110 in this manner may be lower than the surface of the first insulating layer 110. Of course, this embodiment is only used for illustration and is not limited thereto.

In addition, the first stepped vias 120 can also be formed into stepped vias by two lasers in stages, and then use the characteristics of the first insulating layer 110 that can be selectively plated and plated. The stepped through-holes are directly plated and plated to form a conductive material in the stepped through-holes, and then the first stepped through-hole 120 is completed. Of course, this embodiment is only for illustration. In other embodiments of the present invention, the material of the first insulating layer 110 may also be silicon or glass. That is, the first insulating layer 110 may be a silicon substrate or a glass substrate, which may be used as, for example, an interposer, and the first stepped via 120 may be used as a silicon substrate or a glass substrate for electricity. Sexually connected vias.

FIG. 2 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention. It must be noted here that the semiconductor structure 100a of this embodiment is similar to the semiconductor structure 100 of FIG. 1, so this embodiment follows the component numbers and parts of the previous embodiment, in which the same reference numerals are used to indicate the same or similar Element, and description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiment, which is not repeatedly described in this embodiment. Please refer to FIG. 2. Differences between the semiconductor structure 100 a and the semiconductor structure 100 in FIG. 1 will be described below.

In this embodiment, when the required depth of the first stepped via 120 is deep, the first stepped via 120 may further include a sub-connecting portion 126 connected to the connecting portion 124, and the connecting portion 124 It is connected between the top cover portion 122 and the sub-connection portion 126, and the minimum diameter of the connection portion 124 is larger than the maximum diameter of the sub-connection portion 126. That is, in a case where the required depth of the first stepped via 120 is deep, the first stepped via 120 may be drilled by one mechanical drilling plus two laser drillings or by two mechanical drilling plus one laser Drill holes or three lasers to form stepped through holes in stages. In detail, in this embodiment, the first stepped through-hole 120 may be formed by first drilling the depth from the first upper surface 122 to the bottom of the top cover portion 122 by mechanical drilling or laser, and then continuing to The laser is drilled from the bottom of the top cover portion 122 to the bottom of the connection portion 124, and then, the laser is drilled from the bottom of the connection portion 124 to the bottom of the sub-connection portion 126 (in this embodiment, it is the first Look at surface 114). Of course, this embodiment is only used for illustration, and the present invention does not limit the number of lasers for forming the first step-shaped via hole 120 by laser in stages.

FIG. 3 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention. It must be noted here that the semiconductor structure 100b of this embodiment is similar to the semiconductor structure 100 of FIG. 1, so this embodiment follows the component numbers and parts of the previous embodiment, in which the same reference numerals are used to indicate the same or similar Element, and description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiment, which is not repeatedly described in this embodiment. Please refer to FIG. 3. Differences between the semiconductor structure 100 b and the semiconductor structure 100 of FIG. 1 will be described below.

In this embodiment, when the required depth of the first stepped via hole 120 is deep, the first stepped via hole 120 may also include a base portion 128 that is disposed on the first bottom of the first insulating layer 110. The surface 114 and the connection portion 124 are connected between the top cover portion 122 and the base portion 128, wherein the minimum diameter of the base portion 128 is greater than the maximum diameter of the connection portion.

That is, in the case where the required depth of the first stepped via 120 is deep, in this embodiment, mechanical drilling or laser can be used to pass from the first upper surface 112 and the first lower surface 114 to the first insulating layer, respectively. 110 is drilled in the core direction to form the top cover portion 122 and the base portion 128, respectively. Next, drilling is continued from the bottom of the top cover portion 122 to the base portion 128 with a laser. In this way, the diameter of the connecting portion 124 will gradually decrease from the end connected to the top cover portion 122 to the end away from the top cover portion 122. Alternatively, in other embodiments, a laser can be drilled from the bottom of the base portion 128 to the top cover portion 122 to form a connection portion. In this way, the diameter of the connection portion will be away from the base portion from the end of the connection base portion 128. One end of 128 gradually decreases. This embodiment is only used for illustration, and the present invention does not limit the number and direction of lasers for forming the first stepped through hole 120 by mechanical drilling or laser in stages.

FIG. 4 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the invention. It must be noted here that the semiconductor structure 100c of this embodiment is similar to the semiconductor structure 100 of FIG. 1, so this embodiment follows the component numbers and parts of the previous embodiment, in which the same reference numerals are used to indicate the same or similar Element, and description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiment, which is not repeatedly described in this embodiment. Please refer to FIG. 4. Differences between the semiconductor structure 100 c and the semiconductor structure 100 of FIG. 1 will be described below.

In this embodiment, the semiconductor structure 100c further includes a second insulating layer 140, a second patterned circuit layer 160, and a plurality of second stepped vias 150. The second insulating layer 140 includes a second upper surface 142 and a second lower surface 144 opposite to the second upper surface 142. The second insulating layer 140 is stacked on the first insulating layer 110 with the second lower surface 144 thereof. The second patterned circuit layer 160 is disposed on the second upper surface 142. The second stepped vias 150 are disposed in the second insulating layer 140 to electrically conduct the first patterned circuit layer 130 and the second patterned circuit layer 160. That is, the semiconductor structure 100c of this embodiment is a multilayer board structure.

In detail, the second insulating layer 140 may be the same as the material of the first insulating layer 110, and also includes a commonly used insulating material or a selectively plated insulating material, wherein the selectively plated insulating material includes a non-conductive metal composite. In this way, in this embodiment, the second electroplated layer 140 can be formed directly on the second upper surface 142 by utilizing the selective plating property of the second insulating layer 140. Therefore, the second patterned circuit layer 160 formed according to the above process is embedded in the second upper surface 142 of the second insulating layer 140, and the second upper surface 142 of the second insulating layer 140 exposes the second patterned circuit layer. Top of 160. In addition, a bottom surface of the second patterned circuit layer 160 is lower than a second upper surface 142 of the second insulating layer 140.

In addition, the second stepped via 150 can also be formed into two stepped vias in two stages by laser, and then the second insulating layer 140 can be selectively plated and plated. The stepped through-holes are directly plated and plated to form a conductive material in the stepped through-holes, and then the second stepped through-hole 150 is completed. Therefore, the structure of the second stepped via hole 150 may be similar to that of the first stepped via hole 120 of FIGS. 1 to 3.

FIG. 5 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the invention. It must be noted here that the semiconductor structure 100d of this embodiment is similar to the semiconductor structure 100 of FIG. 1, so this embodiment follows the component numbers and parts of the previous embodiment, in which the same reference numerals are used to indicate the same or similar Element, and description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiment, which is not repeatedly described in this embodiment. Please refer to FIG. 5. Differences between the semiconductor structure 100 d and the semiconductor structure 100 of FIG. 1 will be described below.

In this embodiment, the semiconductor structure 100d may further include a first wafer 170 and a plurality of solder balls 180. The first wafer 170 includes an active surface 172 and a back surface 174 opposite to the active surface 172. The first insulating layer 110 covers the active surface 172 of the first chip 170 and exposes the back surface 174. The first stepped via 120 is connected between the first upper surface 112 and the active surface 172 of the first chip 170. The first patterned circuit layer 130 on the first upper surface 112 and the first chip 170 are connected. The solder balls are disposed on the first upper surface 112 and are electrically connected to the first pattern circuit layer 130. In this way, the semiconductor structure 100d can be connected to external electronic components through solder balls, and the first stepped via 120 can be used to electrically connect the first patterned circuit layer 130 and the first chip 170 in a stepped manner. The shape of the semiconductor chip can further increase the bonding force between the first chip 170, the first stepped via 120, and the first insulating layer 110, thereby improving the reliability of the semiconductor structure 100d.

FIG. 6 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention. It must be noted here that the semiconductor structure 100e of this embodiment is similar to the semiconductor structure 100 of FIG. 1, so this embodiment follows the component numbers and parts of the previous embodiment, in which the same reference numerals are used to indicate the same or similar Element, and description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiment, which is not repeatedly described in this embodiment. Referring to FIG. 6, differences between the semiconductor structure 100 e and the semiconductor structure 100 of FIG. 1 will be described below.

In this embodiment, the semiconductor structure 100e further includes a first chip 170 and a first reconfiguration circuit layer 190. The first wafer 170 includes an active surface 172 and a back surface 174 opposite to the active surface 172. The first insulating layer 110 covers the back surface 174 of the first wafer 170, and the first lower surface 114 of the first insulating layer 110 exposes the active surface 172. The first reconfiguration circuit layer 190 is disposed on the first lower surface 114 and is electrically connected to the active surface 172 of the first chip 170. The first stepped vias 120 may penetrate the first insulation layer 110 to connect the first patterned circuit layer 130 and the first reconfiguration circuit layer 190.

In this embodiment, the first stepped through hole 120 may be similar to the embodiment in FIG. 3 and further includes a base portion 128 which is disposed on the first lower surface 114 and the connection portion 124 is connected to the top cover portion 122 and the base portion. 128, and the minimum diameter of the base portion 128 is larger than the maximum diameter of the connecting portion 124. That is, in the case where the first step-shaped via 120 needs to penetrate the entire first insulating layer 110, in this embodiment, mechanical drilling or laser can be used from the first upper surface 112 and the first lower surface 114 to the first A core layer of an insulating layer 110 is drilled to form a top cover portion 122 and a base portion 128 respectively. Next, a laser drilling is used to form a connection portion 124 connected between the top cover portion 122 and the base portion 128. Of course, this embodiment is only used for illustration, and the present invention does not limit the number and direction of forming the first stepped through hole 120 by laser or mechanical drilling in stages.

In this embodiment, the semiconductor structure 100e may further include a second wafer 175, a second insulating layer 140, a second reconfiguration circuit layer 195, and a plurality of solder balls 185. The second wafer 175 includes an active surface 175a and a back surface 175b opposite the active surface 175a. The second insulating layer 140 includes a second upper surface 142 and a second lower surface 144 opposite to the second upper surface 142. The second insulating layer 140 covers the back surface 175b of the second wafer 175, and the second lower surface 144 exposes the active surface 175a of the second wafer 175. The second reconfiguration circuit layer 195 is disposed on the second lower surface 144 and is electrically connected to the active surface 175 a of the second chip 175. The solder ball 185 is connected between the first insulation layer 110 and the second reconfiguration circuit layer 195 to electrically connect the first patterned circuit layer 130 and the second reconfiguration circuit layer 195. In addition, the semiconductor structure 100 e may further include a plurality of solder balls 180 disposed on the first reconfiguration circuit layer 190 to electrically connect the first chip 170. In this way, the semiconductor structure 100e can be connected to another external electronic component through the solder ball 180.

In summary, the semiconductor structure of the present invention uses at least two laser processes or at least one mechanical drilling process plus at least one laser process to form stepped vias by drilling in stages to reduce each laser. The depth of the drilled holes can reduce the maximum diameter of the stepped vias without reducing the depth of the stepped vias, thereby increasing the density of the circuit layout of the semiconductor structure. In addition, because mechanical drilling has the advantages of fast speed and consistent hole diameter, using its advantages in combination with the laser process can achieve cost savings and size control. In addition, the stepped via formed by this process has a stepped appearance, and the stepped appearance can increase the bonding force between the stepped via and the insulating layer to prevent the stepped via and the insulating layer The occurrence of delamination between them can further improve the reliability of the semiconductor structure.

In addition, the insulating layer of the semiconductor structure of the present invention includes a commonly used insulating material or a selectively plated insulating material, which includes a non-conductive metal composite. In this way, the semiconductor structure of the present invention can take advantage of the selective plating characteristics of the insulating layer. The step-shaped vias and the patterned circuit layer are directly formed on the surface, which can effectively simplify the process steps of the semiconductor structure and improve the design flexibility.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

100, 100a ~ e‧‧‧ semiconductor structure

110‧‧‧first insulating layer

112‧‧‧First upper surface

114‧‧‧First lower surface

120‧‧‧The first stepped via

122‧‧‧Top cover

124‧‧‧Connection Department

126‧‧‧Sub-connection

128‧‧‧ base

130‧‧‧The first patterned circuit layer

140‧‧‧Second insulation layer

142‧‧‧second upper surface

144‧‧‧Second lower surface

150‧‧‧Second stepped via

160‧‧‧Second patterned circuit layer

170‧‧‧The first chip

172, 175a‧‧‧active surface

174, 175b‧‧‧ back

175‧‧‧Second Chip

180, 185‧‧‧ solder balls

190‧‧‧First reconfiguration line layer

195‧‧‧Second reconfiguration line layer

FIG. 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention. FIG. 3 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the invention. FIG. 5 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the invention. FIG. 6 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention.

Claims (14)

A semiconductor structure includes: a first insulating layer including a first upper surface and a first lower surface opposite to the first upper surface; a plurality of first stepped vias disposed in the first insulating layer to electrically Sexually communicate with the first upper surface and the first lower surface, wherein each of the first stepped through holes includes a top cover portion and a connection portion connected to the top cover portion, and the top cover portion is disposed on the first upper surface And a top surface of the top cover portion is coplanar with the first upper surface, a minimum diameter of the top cover portion is greater than a maximum diameter of the connection portion; and a first patterned circuit layer is disposed on the first The surface is electrically connected to the first stepped via hole, wherein the first stepped via hole further includes a base portion disposed on the first lower surface, and the connection portion is connected to the top cover portion and the base portion. And a minimum diameter of the base portion is larger than the maximum diameter of the connecting portion. The semiconductor structure according to item 1 of the scope of patent application, wherein a bottom surface of the first patterned circuit layer is lower than the first upper surface. The semiconductor structure according to item 1 of the scope of patent application, wherein the first stepped via hole further includes a sub-connection portion connected to the connection portion, and the connection portion is connected to the top cover portion and the sub-connection portion. And a minimum diameter of the connecting portion is larger than a maximum diameter of the sub-connecting portion. The semiconductor structure according to item 1 of the scope of patent application, wherein the material of the first insulating layer includes epoxy resin, polyester, acrylate, fluoropolymer, polyphenylene oxide, polyimide, phenolic Resin, polyfluorene, silicon polymer, BT resin (Bismaleimide-Triazine modified epoxy resin), cyanate polyester, polyethylene, polycarbonate resin, acrylonitrile-butadiene-styrene copolymer, polyterephthalene Ethylene formate (PET), polybutylene terephthalate (PBT), liquid crystal polymer (LCP), polyamidamine (PA), nylon 6, copolymerized polyoxymethylene (POM), polybenzene Sulfide (PPS), polycarbonate (PC), polymethacrylate (PMMA), ABS resin (Acrylonitrile Butadiene Styrene, ABS) or cyclic olefin copolymer (COC). The semiconductor structure according to item 1 of the scope of patent application, wherein the material of the first insulating layer includes a selectively electroplatable insulating material, which includes a non-conductive metal composite. The semiconductor structure according to item 5 of the scope of patent application, wherein the selectively plated insulating material includes epoxy resin, polyester, acrylate, fluoropolymer, polyphenylene oxide, polyimide, phenolic Resin, polyfluorene, silicon polymer, BT resin (Bismaleimide-Triazine modified epoxy resin), cyanate polyester, polyethylene, polycarbonate resin, acrylonitrile-butadiene-styrene copolymer, polyterephthalene Ethylene formate (PET), polybutylene terephthalate (PBT), liquid crystal polymer (LCP), polyamidamine (PA), nylon 6, copolymerized polyoxymethylene (POM), polybenzene Sulfide (PPS), polycarbonate (PC), polymethacrylate (PMMA), ABS resin (Acrylonitrile Butadiene Styrene, ABS) or cyclic olefin copolymer (COC). The semiconductor structure according to item 6 of the application, wherein the metal in the non-conductive metal composite includes zinc, copper, silver, gold, nickel, palladium, platinum, cobalt, rhodium, iridium, indium, iron, manganese, Aluminum, chromium, tungsten, vanadium, tantalum, titanium, or any combination thereof. The semiconductor structure according to item 1 of the scope of patent application, further comprising: a second insulating layer including a second upper surface and a second lower surface opposite to the second upper surface. The second insulating layer is based on the first Two lower surfaces are stacked on the first insulating layer; a second patterned circuit layer is provided on the second upper surface; and a plurality of second step-shaped vias are provided on the second insulating layer for electrical conduction. The first patterned circuit layer and the second patterned circuit layer. The semiconductor structure according to item 1 of the patent application, wherein a material of the first insulating layer includes silicon or glass. The semiconductor structure according to item 1 of the patent application scope further includes a first chip including an active surface and a back surface opposite to the active surface. The first insulating layer covers the active surface of the first wafer and exposes the active surface. On the back side, the first stepped via is connected between the first upper surface and the active surface to electrically connect the first patterned circuit layer and the first chip. The semiconductor structure according to item 1 of the patent application scope further includes a plurality of solder balls disposed on the first upper surface and electrically connected to the first pattern circuit layer. The semiconductor structure according to item 1 of the patent application scope further includes: a first wafer including a first active surface and a first back surface opposite to the first active surface, and the first insulating layer covers the first wafer The first back surface, and the first lower surface exposes the first active surface; and a first reconfiguration circuit layer disposed on the first lower surface and electrically connected to the first active surface, the first stepped shape A via hole penetrates the first insulation layer to connect the first patterned circuit layer and the first reconfiguration circuit layer. The semiconductor structure according to item 12 of the patent application scope further includes a plurality of solder balls disposed on the first reconfiguration circuit layer to electrically connect the first chip. The semiconductor structure according to item 12 of the scope of patent application, further comprising: a second wafer including a second active surface and a second back surface opposite to the second active surface; a second insulating layer including a second An upper surface and a second lower surface opposite to the second upper surface, the second insulating layer covers the second back surface of the second wafer, and the second lower surface exposes the second active surface; a second reconfiguration A circuit layer disposed on the second lower surface and electrically connected to the second active surface; and a plurality of solder balls connected between the first insulation layer and the second reconfiguration circuit layer to electrically connect the first A patterned circuit layer and the second reconfiguration circuit layer.