TWI626655B - Memory device, word line decoder and operating method of memory device - Google Patents

Abstract

A memory device, a word line decoder, and a method of operating a memory device. The word line decoder includes a number of word line drivers. Each word line driver has an input and an output. The output is electrically connected to one of the word lines. Each of the word line drivers includes a pull-up transistor, a pull-down transistor, and an intermediate transistor. The pull-up transistor provides a first word line voltage to one of the selected word lines. The pull-down transistor provides a second word line voltage to the remaining of the word lines that are not selected. The unselected voltage is higher than the selected voltage. The intermediate transistor is electrically connected to the input terminal and the pull-down transistor to reduce the unselected voltage supplied to the pull-down transistor.

Description

Memory device, word line decoder and memory device operation method

The present invention relates to a memory device, a word line decoder, and a method of operating a memory device.

With the development of storage technology, all kinds of memory are constantly being updated. In the memory, a plurality of word lines are electrically connected to a memory cell array. When programming or reading a memory, one of the word lines is selected and the remaining word lines are not selected. During the self-operation, the unselected word line is applied with 0V. In order to pull down the voltage applied to the unselected word line to 0V. The word line driver electrically connected to the unselected word line must be applied with a high voltage to turn on the NMOS transistor of the word line driver. Therefore, the NMOS transistor must withstand the gate stress.

Please refer to FIG. 1 , which is a schematic diagram of the NMOS transistor after receiving the gate high voltage. In the initial state, the NMOS transistor has an original current-voltage curve C1. After being subjected to a gate high voltage for a period of time, the NMOS transistor has a changed current-voltage curve C2. From the changed current-voltage curve C2 and the original current - Comparison of the voltage curve C1, the long-term gate high voltage has caused a significant increase in the off-current (Ioff) and caused a significant drop in the ON-current (Ion). Therefore, how to improve this situation has become an important issue.

The present invention relates to a memory device, a word line decoder, and a method of operating the same that utilizes an intermediate transistor to reduce the high voltage supplied to avoid gate stress.

According to an aspect of the invention, a memory device is proposed. The memory device includes a memory cell array and a word line decoder. The memory cell array includes a number of word lines. The word line decoder includes a number of word line drivers. Each word line driver has an input and an output. The output is electrically connected to one of the word lines. Each of the word line drivers includes a pull-up transistor, a pull-down transistor, and an intermediate transistor. The pull-up transistor is electrically connected to the input end and the output end. If the pull-up transistor is turned on by applying a selection voltage, the pull-up transistor provides a first word line voltage through the output terminal to one of the selected word lines. The pull-down transistor is electrically connected to the input end and the output end. If the pull-down transistor is turned on by applying an unselected voltage, the pull-down transistor provides a second word line voltage through the output terminal to the remaining selected word lines. The unselected voltage is higher than the selected voltage. The intermediate transistor is electrically connected to the input terminal and the pull-down transistor to reduce the unselected voltage supplied to the pull-down transistor.

According to another aspect of the present invention, a word line decoder is proposed. The word line decoder includes a number of word line drivers. Each of the word line drivers has an input and an output. The output is electrically connected to one of the plurality of word lines. Each of the word line drivers includes a pull-up transistor, a pull-down transistor, and an intermediate transistor. The pull-up transistor is electrically connected to the input end and the output end. If the pull-up transistor is turned on by applying a selection voltage, the pull-up transistor provides a first word line voltage through the output terminal to one of the selected word lines. The pull-down transistor is electrically connected to the input end and the output end. If the pull-down transistor is turned on by applying an unselected voltage, the pull-down transistor provides a second word line voltage through the output terminal to the remaining unselected word lines, and the unselected voltage is higher than The selection voltage. The intermediate transistor is electrically connected to the input terminal and the pull-down transistor to reduce the unselected voltage supplied to the pull-down transistor.

According to still another aspect of the present invention, a method of operating a memory device is presented. The memory device includes a memory cell array and a word line decoder. The memory cell array includes a plurality of word lines. The word line decoder includes a plurality of word line drivers. Each of the word line drivers includes a pull-up transistor, a pull-down transistor, and an intermediate transistor. The method includes the steps of: in one of the word line drivers, applying a selection voltage to the input terminal to turn on the pull-up transistor and turn off the pull-down transistor to make a first word A line voltage is supplied through the output to one of the selected word lines. The rest of the word line drivers In either one, by applying an unselected voltage to the input terminal, the pull-up transistor is turned off and the pull-down transistor is turned on, so that a second word line voltage is supplied through the output terminal to the unselected ones. One of the word lines. In each of the word line drivers, the intermediate transistor is electrically connected to the input terminal and the pull-down transistor to reduce the unselected voltage supplied to the pull-down transistor.

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

100‧‧‧ memory device

110‧‧‧ memory cell array

120‧‧‧ bit line decoder

130‧‧‧ character line decoder

131‧‧‧word line driver

1311‧‧‧Lifting the crystal

1312‧‧‧ Pull-down transistor

1313‧‧‧Intermediate transistor

BL‧‧‧ bit line

C1‧‧‧Original current-voltage curve

C2‧‧‧Changed current-voltage curve

D1, D2, D3‧‧‧ bungee

G1, G2, G3‧‧‧ gate

IN‧‧‧ input

OUT‧‧‧ output

P0‧‧‧ intermediate point

S1, S2, S3‧‧‧ source

S410, S420‧‧‧ process steps

Vdd‧‧‧ drive voltage

VS1‧‧‧ first voltage source

VS2‧‧‧second voltage source

VS3‧‧‧ third voltage source

Vpp‧‧‧first word line voltage

Vss‧‧‧second word line voltage

WL‧‧‧ character line

WL0‧‧‧No word line selected

WL1‧‧‧Selected word line

Vhigh‧‧‧ not selected voltage

Vhigh’‧‧‧voltage after falling

Vlow‧‧‧Select voltage

Vtn0, Vtn1‧‧‧ threshold voltage

FIG. 1 is a schematic view showing the NMOS transistor after receiving a gate high voltage.

2 is a schematic diagram of a memory device in accordance with an embodiment of the present invention.

FIG. 3A is a schematic diagram showing a word line driver electrically connected to a selected word line.

FIG. 3B is a schematic diagram of a word line driver electrically connected to an unselected word line.

Figure 4 is a flow chart showing the method of operation of the memory device.

Please refer to FIG. 2, which illustrates a schematic diagram of a memory device 100 in accordance with an embodiment of the present invention. The memory device 100 includes a memory cell array 110, a bit line decoder 120, and a word line decoder 130. Memory cell array 110 package A plurality of word lines WL and a plurality of bit lines BL are included. The bit line decoder 120 is configured to select one of the bit lines BL, and the word line decoder 130 is used to select one of the word lines WL.

The word line decoder 130 includes a plurality of word line drivers 131. Each word line driver 131 has an input terminal IN and an output terminal OUT. Each output terminal OUT is electrically connected to one word line WL. The word line driver 131 supplies the first word line voltage Vpp to the selected word line WL through the output terminal OUT, and provides the second word line voltage Vss through the output terminal OUT to the remaining word lines WL that are not selected. The first word line voltage Vpp is higher than the second word line voltage Vss. For example, the first word line voltage Vpp may be between 6V and 9V, such as 8V; the second word line voltage Vss may be 0V or 1V.

Please refer to Figures 3A and 3B. FIG. 3A is a schematic diagram showing the word line driver 131 electrically connected to a selected word line WL1. FIG. 3B is a schematic diagram showing the word line driver 131 electrically connected to the unselected word line WL0. The word line driver 131 includes a pull-up transistor 1311, a pull-down transistor 1312, and an intermediate transistor 1313. In one embodiment, the pull-up transistor 1311 is a P-type metal-oxide-semiconductor transistor (PMOS transistor), and the pull-down transistor 1312 is an N-type metal oxide semiconductor device. The crystal (N type Metal-Oxide-Semiconductor transistor, NMOS transistor), the intermediate transistor 1313 is an N-type metal oxide semiconductor transistor (NMOS). In another embodiment, the intermediate transistor 1313 can be a P-type metal oxide semiconductor transistor (PMOS). The gate G1 of the pull-up transistor 1311 is electrically connected to the input terminal IN, the source S1 of the pull-up transistor 1311 is electrically connected to the first voltage source VS1, and the drain D1 of the pull-up transistor 1311 is electrically connected to the output. End OUT. The drain D2 of the pull-down transistor 1312 is electrically connected to the output terminal OUT and the drain D1 of the pull-up transistor 1311. The source S2 of the pull-down transistor 1312 is electrically connected to the second voltage source VS2, and the gate of the pull-down transistor 1312 is pulled down. The pole G2 is electrically connected to the intermediate transistor 1313. The drain D3 of the intermediate transistor 1313 is electrically connected to the input terminal IN, the source S3 of the intermediate transistor 1313 is electrically connected to the gate G2 of the pull-down transistor 1312, and the gate G3 of the intermediate transistor 1313 is electrically connected to the gate Three voltage source VS3.

Please refer to Figures 3A and 3B and Table 1 below. Table 1 illustrates the operation of Figures 3A and 3B. As shown in FIG. 3A, when the pull-up transistor 1311 is turned on and the pull-down transistor 1312 is turned off, the first word line voltage Vpp is supplied to the selected word line WL1 through the output terminal OUT. In order to open the pull-up transistor 1311 and turn off the pull-down transistor 1312, a selection voltage Vlow is applied to the input terminal IN.

As shown in FIG. 3B, when the pull-up transistor 1311 is turned off and the pull-down transistor 1312 is turned on, the second word line voltage Vss is supplied to the unselected word line WL0 through the output terminal OUT. In order to turn off the pull-up transistor 1311 and turn on the pull-down transistor 1312, an unselected voltage Vhigh is applied to the input terminal IN.

The unselected voltage Vhigh is much higher than the selection voltage Vlow. In order to avoid gate voltage of the pull-down transistor 1312, an intermediate transistor 1313 is disposed between the input terminal IN and the pull-down transistor 1312 to lower the unselected voltage Vhigh.

As shown in FIG. 3B, the intermediate transistor 1313 is turned on by applying a driving voltage Vdd. The driving voltage Vdd is higher than the threshold voltage Vtn0 of the intermediate transistor 1313. At the intermediate point P0, the unselected voltage Vhigh has been lowered to a falling voltage Vhigh'. The voltage Vhigh' after the falling is equal to the value of the driving voltage Vdd minus the threshold voltage Vtn0 of the intermediate transistor 1313 (Vhigh' = Vdd - Vtn0).

Since the unselected voltage Vhigh has been lowered to the post-drop voltage Vhigh', the pull-down transistor 1312 can effectively avoid the gate high voltage. because Thus, the current-voltage curve of the pull-down transistor 1312 can be stably maintained. In this way, the OFF-current (Ioff) and the ON-current (Ion) can be maintained at normal levels.

In order to smoothly start the pull-down transistor 1312, the voltage Vhigh' after the falling is controlled to be higher than the threshold voltage Vtn1 of the pull-down transistor 1312. In an embodiment, the unselected voltage Vhigh may be equal to the first word line voltage Vpp, and the select voltage Vlow may be equal to the second word line voltage Vss. The first word line voltage Vpp is, for example, 8V, and the second word line voltage is, for example, 0V. The threshold voltage Vtn0 of the intermediate transistor 1313 is, for example, -1V to 2V, and the threshold voltage Vtn1 of the pull-down transistor 1312 is, for example, 1V. The driving voltage Vdd of the intermediate transistor 1313 is, for example, between 3V and 7V.

Please refer to FIG. 4 , which illustrates a flow chart of a method of operating the memory device 100 . The flowchart includes steps S410 and S420. Step S410 and step S420 can be performed simultaneously. In step S410, in one of the word line drivers 131, by applying a selection voltage Vlow to the input terminal IN, the pull-up transistor 1311 is turned on and the pull-down transistor 1312 is turned off, so that the first word line The voltage Vpp is supplied to the selected word line WL through the output terminal OUT.

In step S420, in any of the other word line drivers 131, by applying the unselected voltage Vhigh to the input terminal, the pull-up transistor 1311 is turned off and the pull-down transistor 1312 is turned on, so that the second word line voltage Vss Provided to the unselected word line WL through the output terminal OUT. The intermediate transistor 1313 serves to reduce the unselected voltage Vhigh supplied to the pull-down transistor 1312.

The above embodiment can effectively prevent the pull-down transistor 1312 from generating a gate high voltage. Therefore, the current-voltage curve of the pull-down transistor 1312 can be maintained and the reliability of the memory device 100 can be improved.

In the above, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the scope of the invention. Change and retouch. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims (9)

A memory device comprising: a memory cell array comprising a plurality of word lines; and a word line decoder comprising a plurality of word line drivers, wherein each of the word line drivers has an input And an output terminal, the output terminal is electrically connected to one of the word lines, and each of the word line drivers includes: a pull-up transistor electrically connected to the input end And the output terminal, if the pull-up transistor is turned on by applying a selection voltage, the pull-up transistor provides a first word line voltage through the output terminal to the selected word line One of the pull-down transistors electrically connected to the input terminal and the output terminal, and if the pull-down transistor is turned on by applying an unselected voltage, the pull-down transistor transmits the output The terminal provides a second word line voltage to the unselected remaining word lines, the unselected voltage is higher than the selection voltage; and an intermediate transistor electrically connected to the input terminal and the pull-down transistor to Lowering the supply to the pull-down transistor The unselected voltage; wherein one of the pull-up transistor and the pull-down transistor is a P-type metal-Oxide-Semiconductor transistor (PMOS transistor), the pull-up transistor And the other one of the pull-down transistors is an N-type metal-Oxide-Semiconductor transistor (PMOS transistor). In each of the word line drivers, the intermediate crystal system is continuously turned on. . The memory device of claim 1, wherein in each of the word line drivers, the intermediate transistor is applied with a driving voltage higher than a threshold voltage of the intermediate transistor; In the line driver, the difference between the driving voltage and the threshold voltage of the intermediate transistor is greater than a threshold voltage of the pull-down transistor. The memory device of claim 1, wherein in each of the word line drivers, the intermediate transistor is electrically connected to the input terminal and one of the pull-down transistors. A word line decoder includes a plurality of word line drivers, wherein each of the word line drivers has an input end and an output end, and the output end is electrically connected to one of the plurality of word line lines, and each The word line driver includes: a pull-up transistor electrically connected to the input end and the output end, and if the pull-up transistor is turned on by applying a selection voltage, the pull-up transistor The booster crystal provides a first word line voltage through the output terminal to one of the selected word line lines; a pull-down transistor electrically connected to the input terminal and the output End, if the pull-down transistor is turned on by applying an unselected voltage, the pull-down transistor provides a second word line voltage through the output terminal to the unselected remaining word lines, the unselected voltage Above the selection voltage; and an intermediate transistor electrically connected to the input terminal and the pull-down transistor to reduce the unselected voltage supplied to the pull-down transistor; Wherein one of the pull-up transistor and the pull-down transistor is a P-type metal-Oxide-Semiconductor transistor (PMOS transistor), and the pull-up transistor and the pull-down transistor The other one is a N-type metal-Oxide-Semiconductor transistor (NMOS transistor), and in each of the word line drivers, the intermediate crystal system is continuously turned on. The character line decoder of claim 4, wherein in each of the word line drivers, the intermediate transistor is applied with a driving voltage higher than a threshold voltage of the intermediate transistor; In the word line driver, a difference between the driving voltage and the threshold voltage of the intermediate transistor is greater than a threshold voltage of the pull-down transistor. The word line decoder of claim 4, wherein in each of the word line drivers, the intermediate transistor is electrically connected to the input terminal and one of the pull-down transistors. A method of operating a memory device, wherein the memory device comprises a memory cell array and a word line decoder, the memory cell array comprising a plurality of word line lines, the word line decoder comprising a plurality of word line drivers Each of the word line drivers includes a pull-up transistor, a pull-down transistor, and an intermediate transistor, the method comprising: among the word line drivers In one of the embodiments, by applying a selection voltage to the input terminal, the pull-up transistor is turned on and the pull-down transistor is turned off, so that a word line voltage is supplied through the output to one of the selected word lines; and in any of the remaining word line drivers, by applying an unselected voltage to the input Shutting down the pull-up transistor and turning on the pull-down transistor, such that a second word line voltage is supplied through the output terminal to one of the unselected word lines; wherein each of the word line drivers The intermediate transistor is electrically connected to the input terminal and the pull-down transistor to reduce the unselected voltage supplied to the pull-down transistor; wherein one of the pull-up transistor and the pull-down transistor is P type Metal-Oxide-Semiconductor transistor (PMOS transistor), the other of the pull-up transistor and the pull-down transistor is an N-type metal oxide semiconductor transistor (N type Metal -Oxide-Semiconductor transistor, PMOS transistor), in each of the word line drivers, the intermediate crystal system is continuously turned on. The method of operating a memory device according to claim 7, wherein in each of the word line drivers, the intermediate transistor is applied with a driving voltage higher than a threshold voltage of the intermediate transistor; In each of the word line drivers, a difference between the driving voltage and the threshold voltage of the intermediate transistor is greater than a threshold voltage of the pull-down transistor. The operating method of the memory device of claim 7, wherein in each of the word line drivers, the intermediate transistor is electrically connected to the input terminal and one of the gates of the pull-down transistor.