TWI584261B - Display apparatus - Google Patents

Description

Display device

The present disclosure relates to a display device.

Please refer to FIG. 11 and FIG. 12 at the same time. FIG. 11 is a partial schematic diagram showing a conventional liquid crystal display panel and its pixel data, and FIG. 12 is a schematic diagram showing a single linear afterimage of a conventional liquid crystal panel. The liquid crystal display panel 21 includes a first polarity data line 211, a second polarity data line 212, a main scan line 213, a sub-scanning line 214, and pixels 215(11) to 215(16). The pixels 215(11) to 215(16) are respectively located in the 11th to 16th rows of the liquid crystal display panel 21. The pixel 215 (11), the pixel 215 (13), and the pixel 215 (15) are coupled to the first polarity data line 211, the main scanning line 213, and the sub-scanning line 214, and the pixel 215 (12), pixel 215 (14) and the pixel 215 (16) are coupled to the second polarity data line 212, the main scan line 213, and the sub-scan line 214. The first polarity data D+ on the first polarity data line 211 is greater than or equal to the common voltage Vcom, and the second polarity data D- on the second polarity data line 212 is less than or equal to the common voltage Vcom.

However, when the first polarity data D+ of the write pixel 215 (14) is different from the first polarity data D+ of the write pixel 215 (12), and the second polarity data D of the pixel 215 (13) is written When the second polarity data D- of the write pixel 215 (11) is the same, a noise voltage is generated. Since the first polarity data D+ and the second polarity data D- are respectively written to the pixels 215 (13) and the pixels 215 (14), other pixels are turned on by the sub-scanning line 214, thereby causing noise. The voltage is written to other pixels. So, it will be like FIG. 12 illustrates a linear afterimage 210 displayed on the liquid crystal display panel 21.

The disclosure relates to a display device.

According to the present disclosure, a display device is proposed. The display device includes a liquid crystal display panel, a source driver, a gate driver, and a timing controller, and the liquid crystal display panel includes a first polarity data line, a second polarity data line, a main scan line, a sub-scan line, a first pixel, and a first Two pixels. The first pixel is coupled to the first polarity data line, the main scan line and the sub-scan line, and the second pixel is coupled to the second polarity data line, the main scan line and the sub-scan line. The source driver outputs the first polarity data to the first polarity data line, and outputs the second polarity data to the second polarity data line. The gate driver is coupled to the main scan line and the sub scan line. The timing controller controls the gate driver to alternately output the main scanning signal and the sub-scanning signal in each frame time, and the time difference between the adjacent main scanning signal and the sub-scanning signal is a delay time value. The main scanning signal controls the first pixel to write the first polarity data and the second pixel to write the second polarity data, and the sub-scanning line controls the first pixel and the second pixel to perform charge distribution.

According to the present disclosure, a display device is proposed. The display device includes a liquid crystal display panel, a source driver, a gate driver, and a timing controller, and the liquid crystal display panel includes a first polarity data line, a second polarity data line, a main scan line, a sub-scan line, a first pixel, and a first Two pixels. The first pixel is coupled to the first polarity data line, the main scan line and the sub-scan line, and the second pixel is coupled to the second polarity data line, the main scan line and the sub-scan line. The source driver outputs the first polarity data to the first polarity data line, and outputs the second polarity data to the second polarity data line. The source driver outputs the first polarity data to the first polarity The data line and output the second polarity data to the second polarity data line. The gate driver is coupled to the main scan line and the sub scan line. The timing controller controls the gate driver to alternately output the main scanning signal and the sub-scanning signal in each frame time, and the time difference between the adjacent main scanning signal and the sub-scanning signal is a delay time value. The main scanning signal controls the first pixel to write the first polarity data and the second pixel to write the second polarity data, and the sub-scanning signal controls the first pixel and the second pixel to perform charge distribution, and the sub-scanning signal enables the pair The scan line time is greater than the time that the main scan signal enables the main scan line.

In order to better understand the above and other aspects of the present disclosure, the following specific embodiments, together with the accompanying drawings, are described in detail below:

First embodiment

Please refer to FIG. 1 and FIG. 2 simultaneously. FIG. 1 is a schematic diagram showing a display device according to the first embodiment, and FIG. 2 is a partial schematic view showing the display panel according to the first embodiment. The display device 1 includes a liquid crystal display panel 11, a gate driver 12, a source driver 13, and a timing controller 14. The timing controller 14 controls the gate driver 12 and the source driver 13 to drive the liquid crystal display panel 11.

The liquid crystal display panel 11 includes a first polarity data line 111, a second polarity data line 112, a main scan line 113, a sub-scanning line 114, a first pixel 115, and a second pixel 116. The first pixel 115 is coupled to the first polarity data line 111, the main scanning line 113, and the sub-scanning line 114, and the second pixel 116 is coupled to the second polarity data line 112, the main scanning line 113, and the sub-scanning line 114. The gate driver 12 is coupled to the main scan line 113 and the sub-scan line 114. Source driver 13 The first polarity data line 111 and the second polarity data line 112 are coupled. The source driver 13 outputs the first polarity data D+ to the first polarity data line 111, and outputs the second polarity data D- to the second polarity data line 112.

The first pixel 115 further includes a first liquid crystal capacitor C _A1 , a first transistor TFT1, a second liquid crystal capacitor C _B1 , a second transistor TFT 2 , and a first dark region capacitor C _C1 . The first transistor TFT1 is controlled by the main scanning signal MS to electrically connect the first polarity data line 111 to the first liquid crystal capacitor C _A1 . The second transistor TFT2 is controlled by the main scanning signal MS to electrically connect the first polarity data line 111 to the second liquid crystal capacitor C _B1 . The third transistor TFT3 is controlled by the sub-scanning signal LCS to electrically connect the first dark region capacitor C _C1 to the second liquid crystal capacitor C _B1 for charge distribution.

The second pixel 116 includes a third liquid crystal capacitor C _A2 , a fourth transistor TFT 4 , a fourth liquid crystal capacitor C _B2 , a fifth transistor TFT 5 , a second dark region capacitor C _{C2 ,} and a sixth transistor TFT 6 . The fourth transistor TFT4 is controlled by the main scanning signal MS to electrically connect the second polarity data line 112 to the third liquid crystal capacitor C _A2 . The fifth transistor TFT 5 is controlled by the main scanning signal MS to electrically connect the second polarity data line 112 to the fourth liquid crystal capacitor C _B2 . The sixth transistor TFT6 is controlled by the sub-scanning signal LCS to electrically connect the second dark region capacitor C _C2 to the fourth liquid crystal capacitor C _B2 for charge distribution.

The timing controller 14 controls the gate driver 12 to alternately output the main scanning signal MS and the sub-scanning signal LCS in each frame time, and the time difference between the adjacent main scanning signal MS and the sub-scanning signal is a delay time value. The main scanning signal MS controls the first pixel 115 to write the first polarity data D+ to the first liquid crystal capacitor C _A1 and the second liquid crystal capacitor C _B1 , and controls the second pixel 116 to write the second polarity data D-to Three liquid crystal capacitors C _A2 and fourth liquid crystal capacitors C _B2 . The sub-scanning signal LCS controls the first pixel 115 and the second pixel 116 to perform charge distribution.

Please refer to FIG. 1 , FIG. 3 and FIG. 4 simultaneously. FIG. 3 is a timing diagram of the signal of the main scanning signal and the sub scanning signal according to the first embodiment in different frame times, and FIG. 4 is a schematic diagram. According to the first embodiment, a single linear afterimage is displayed in four frame times, and thus is divided into four linear afterimages to reduce the brightness thereof. Thus, since the brightness is lowered, the human eye is reduced in linearity. The feeling of afterimage. The sub-scanning signal LCS in each frame time is outputted by the delay time value Δt after the output of the main scanning signal MS, and the frame time has at least two different delay time values. For convenience of explanation, FIG. 3 illustrates the example of four frame time and four delay time values. The delay time Δt corresponds to the delay time values DT0 to DT3 at the frame times F(n) to F(n+3), respectively. The delay time values DT0 to DT3 are different from each other.

For example, the delay time value Δt is equal to the delay time value DT0 at the frame time F(n), and the delay time value DT0 is, for example, five scan line turn-on times. Since the sub-scanning signal LCS and the main scanning signal MS open two columns of pixels at a time, the pixels opened by the sub-scanning signal LCS are different from the pixels opened by the main scanning signal MS by the value of the scanning line on-time of 10 columns. When the second pixel 116 of the 24th column in the liquid crystal display panel 11 is controlled by the main scanning signal MS to write the second polarity data D- at the frame time F(n), the first pixel 115 of the 13th column and The second pixel 116 of the 14th column is controlled by the sub-scanning signal LCS for charge distribution at the frame time F(n).

Then, the delay time value Δt is equal to the delay time value DT1 at the frame time F(n+1), and the delay time value DT1 is, for example, when the six scan lines are turned on. between. Since the sub-scanning signal LCS and the main scanning signal MS turn on the two columns of pixels at a time, the pixels opened by the sub-scanning signal LCS are different from the pixels opened by the main scanning signal MS by the value of the scanning line on-time of 12 columns. When the second pixel 116 of the 24th column in the liquid crystal display panel 11 is controlled by the main scanning signal MS to write the second polarity data D- at the frame time F(n+1), the first pixel of the 11th column The second pixel 116 of the 115th and 12th columns is controlled by the sub-scanning signal LCS for charge distribution at the frame time F(n+1).

Subsequently, the delay time value Δt is equal to the delay time value DT2 at the frame time F(n+2), and the delay time value DT2 is, for example, 7 scan line turn-on times. Since the sub-scanning signal LCS and the main scanning signal MS open two columns of pixels at a time, the pixels opened by the sub-scanning signal LCS are different from the pixels opened by the main scanning signal MS by the value of the scanning line on-time of 14 columns. When the second pixel 116 of the 24th column in the liquid crystal display panel 11 is controlled by the main scanning signal MS to write the second polarity data D- at the frame time F(n+2), the first pixel of the ninth column The second pixel 116 of the 115th and the 10th column is controlled by the sub-scanning signal LCS at the frame time F(n+2) for charge distribution.

Then, the delay time value Δt is equal to the delay time value DT3 at the frame time F(n+3), and the delay time value DT3 is, for example, 8 scan line turn-on times. Since the sub-scanning signal LCS and the main scanning signal MS open two columns of pixels at a time, the pixels opened by the sub-scanning signal LCS are different from the pixels opened by the main scanning signal MS by 16 columns of scanning line on-time values. When the second pixel 116 of the 24th column in the liquid crystal display panel 11 is controlled by the main scanning signal MS to write the second polarity data D- at the frame time F(n+3), the first pixel of the seventh column The second pixel 116 of column 115 and column 8 is controlled by the sub-scanning signal LCS for charge distribution at frame time F(n+3).

The noise voltage generated by the data coupling effect will write different column pixels at different frame times. As a result, the original single linear residual image will be expanded as a linear afterimage 110a, a linear afterimage 110b, a linear afterimage 110c, and a linear afterimage 110d as shown in FIG. Since the brightness of the original single linear residual image is divided into four parts, the brightness of the afterimage is relatively lowered, so that the existence of the residual image is not perceived by the eye.

Please refer to FIG. 1 and FIG. 5 at the same time. FIG. 5 is a schematic diagram showing changes in transmittance of liquid crystal after voltage application. When a voltage 72 is applied to the liquid crystal display panel 11, the transmittance of the liquid crystal changes as shown by the curve 71. The liquid crystal retardation time T1 represents the time when the liquid crystal transmittance of the liquid crystal display panel 11 after applying the voltage 72 is from 0 to 10%. The steady-state time T2 indicates the transmittance of the liquid crystal after the application of the voltage 72 to the liquid crystal display panel 11 from 0 to 90%. The rise time T3 indicates the transmittance of the liquid crystal after the application of the voltage 72 to the liquid crystal display panel 11 from 10% to 90%.

Please refer to FIG. 1 , FIG. 5 , FIG. 6 and Table 1 at the same time. FIG. 6 is a schematic diagram showing the liquid crystal delay time T1, the steady-state time T2 and the rise time T3 of different voltage change intervals, and Table 1 is Different panel sizes. The steady state time T2 and the rise time T3 correspond to the left ordinate, and the liquid crystal delay time T1 corresponds to the right ordinate. The liquid crystal delay time T1 can be calculated from the steady state time T2 and the rise time T3. When the voltage variation interval is 1V~6V, the liquid crystal delay time T1 is equal to 3.2 milliseconds. When the voltage change interval is 1V~7V, the liquid crystal delay time T1 is equal to 2 milliseconds. When the voltage variation interval is 1V~8V, the liquid crystal delay time T1 is equal to 0.6 milliseconds.

The liquid crystal retardation time T1' represents a time when the transmittance of the liquid crystal is from 0 to 1%. When the voltage change interval is 1V~6V, the liquid crystal delay time T1', etc. At 320 microseconds. When the voltage variation interval is 1V to 7V, the liquid crystal delay time T1' is equal to 200 microseconds. When the voltage change interval is 1V~8V, the liquid crystal delay time T1 is equal to 60 microseconds.

When the picture frequency of the liquid crystal display panel 11 is 120 Hz, the single scanning line turn-on times of the resolution 4K2K, the resolution FHD, and the resolution HD are 3.5 microseconds, 7 microseconds, and 10 microseconds, respectively. When the picture frequency of the liquid crystal display panel 11 is 60 Hz, the single scanning line turn-on times of the resolution 4K2K, the resolution FHD, and the resolution HD are 7 microseconds, 14 microseconds, and 20 microseconds, respectively.

The upper limit of the different delay time values described above depends on the liquid crystal delay time T1' of the liquid crystal display panel 11. For example, when the resolution of the liquid crystal display panel 11 is 4K2K and the picture frequency is 120 Hz, the single scan line turn-on time is about 3.5 microseconds. 320 microseconds divided by 3.5 microseconds is about 91, and the upper limit of the different delay time values is 91. In other words, the original single linear afterimage can be expanded to a maximum of 91 darker linear afterimages.

Second embodiment

Please refer to FIG. 1 and FIG. 7 . FIG. 7 is a timing diagram of signals of different main frame signals and sub-scanning signals according to the second embodiment. The second embodiment is mainly different from the first embodiment in that the timing controller 14 controls the gate driver 12 to output the sub-scanning signal LCS at frame time F(n+4) to F(n+7), and the frame is The sub-scanning signals LCS of the time F(n+4) to F(n+7) are the same as the sub-scanning signals LCS of the frame times F(n) to F(n+3), respectively. The delay time value Δt corresponds to the delay time values DT4 to DT7 at the frame times F(n+4) to F(n+7), respectively. The delay time values DT4 to DT7 are different from each other, and the delay time values DT4 to DT7 are equal to the delay time values DT0 to DT3, respectively.

Third embodiment

Please refer to FIG. 1 and FIG. 8 . FIG. 8 is a timing diagram of the signal of the main scanning signal and the sub scanning signal according to the third embodiment at different frame times. The third embodiment is mainly different from the second embodiment in that the delay time value Δt corresponds to the delay time values DT0 to DT7 at the frame times F(n) to F(n+7), respectively. The delay time value DT0 is equal to the delay time value DT1, and the delay time value DT2 is equal to the delay time value DT3. The delay time value DT4 is equal to the delay time value DT5, and the delay time value DT6 is equal to the delay time value DT7. The delay time value DT0, the delay time value D2, and the delay time value D4 to the delay time value D6 are different from each other.

Fourth embodiment

Please refer to FIG. 1 and FIG. 9 . FIG. 9 is a timing diagram of signals of the main scanning signal and the sub-scanning signal according to the fourth embodiment. Fourth implementation The main difference between the example and the first embodiment is that the sub-scanning signal LCS enables the sub-scanning line 114 of the fourth embodiment to be longer than the main scanning signal MS enables the main scanning line 113. When the main scanning signal MS is disabled by the main scanning line 113, the sub-scanning signal LCS continues to enable the sub-scanning line 114. In other words, the sub-scan line 114 is enabled for a much longer time than the de-energized time.

Fifth embodiment

Referring to FIG. 1 and FIG. 10, FIG. 10 is a timing chart showing the main scanning signal and the sub-scanning signal according to the fifth embodiment. The fifth embodiment is mainly different from the fourth embodiment in that the sub-scanning signal LCS of the fifth embodiment includes a plurality of consecutive scanning pulses. Since the number of scan pulses included in the sub-scanning signal LCS is greater than the number of scan pulses included in the main scanning signal MS, the sub-scanning signal LCS enables the sub-scanning line 114 to be longer than the main scanning signal MS-enabled main scanning line. 113 time.

In summary, although the disclosure has been disclosed in the above embodiments, it is not intended to limit the disclosure. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the disclosure. Therefore, the scope of protection of this disclosure is subject to the definition of the scope of the appended claims.

1‧‧‧ display device

11, 21‧‧‧ LCD panel

12‧‧‧ gate driver

13‧‧‧Source Driver

14‧‧‧Timing controller

71‧‧‧ Curve

72‧‧‧ voltage

110a~110d, 210‧‧‧ linear residual image

111, 211‧‧‧ first polarity data line

112, 212‧‧‧second polarity data line

113‧‧‧Main scan line

114‧‧‧Sub Scan Line

115‧‧‧ first pixels

116‧‧‧Second pixels

215 (11), 215 (12), 215 (13), 215 (14), 215 (15), 215 (15) ‧ ‧ pixels

C _A1 ‧‧‧First LCD capacitor

C _B1 ‧‧‧Second liquid crystal capacitor

C _A2 ‧‧‧third liquid crystal capacitor

C _B2 ‧‧‧fourth liquid crystal capacitor

C _C1 ‧‧‧first dark area capacitor

C _C2 ‧‧‧second dark area capacitor

Fourth transistor TFT4, fifth transistor TFT5, and sixth transistor TFT6

D+‧‧‧First Polar Data

D-‧‧‧second polarity data

DT0~DT7‧‧‧ delay time value (and △t: delay time value)

F(n)~F(n+7)‧‧‧ Frame time

LCS‧‧‧Sub Scan Signal

MS‧‧‧ main scan signal

TFT1‧‧‧first transistor

TFT2‧‧‧second transistor

TFT3‧‧‧ third transistor

TFT4‧‧‧fourth transistor

TFT5‧‧‧ fifth transistor

TFT6‧‧‧ sixth transistor

T1‧‧‧ LCD delay time

T2‧‧‧ steady state time

T3‧‧‧ rise time

Vcom‧‧‧Common voltage

△t‧‧‧delay time value

1 is a schematic view showing a display device according to a first embodiment.

FIG. 2 is a partial schematic view showing the display panel according to the first embodiment.

FIG. 3 is a timing diagram showing the signal of the main scanning signal and the sub-scanning signal at different frame times according to the first embodiment.

Figure 4 is a schematic diagram showing the division of the luminance of a single linear afterimage into four linear afterimages in accordance with the first embodiment.

Figure 5 is a schematic diagram showing the change in transmittance of the liquid crystal after applying a voltage.

FIG. 6 is a schematic diagram showing the liquid crystal delay time T1, the steady state time T2, and the rise time T3 in different voltage change intervals.

FIG. 7 is a timing diagram showing the signal of the main scanning signal and the sub-scanning signal at different frame times according to the second embodiment.

Figure 8 is a timing diagram showing the timing of the main scanning signal and the sub-scanning signal in different frame times according to the third embodiment.

FIG. 9 is a timing chart showing the main scanning signal and the sub-scanning signal according to the fourth embodiment.

Figure 10 is a timing chart showing the main scanning signal and the sub-scanning signal according to the fifth embodiment.

Figure 11 is a partial schematic view showing a conventional liquid crystal display panel and its pixel data.

Figure 12 is a schematic diagram showing a single linear afterimage of a conventional liquid crystal panel.

F(n)~F(n+3)‧‧‧ Frame time

△t‧‧‧delay time

DT0~DT3‧‧‧ delay time value

Claims (10)

A display device comprising: a liquid crystal display panel comprising: a plurality of first polarity data lines; a plurality of second polarity data lines; a plurality of main scan lines; a plurality of sub-scan lines; a plurality of first pixels, each of the first pixels The first polarity data line, the main scan line and the sub-scan line are coupled to each other; the second pixel is coupled to the second polarity data line, the main scan line, and the sub-scan line a source driver for outputting the plurality of first polarity data to the corresponding first polarity data lines, and outputting the plurality of second polarity data to the corresponding second polarity data lines; a gate driver coupled The main scanning line and the sub-scanning lines; a timing controller for controlling the gate driver to alternately output a main scanning signal and a scanning signal in each frame time, and adjacent to the main scanning The time difference between the signal and the sub-scanning signal is a delay time value, and the main scanning signal controls the first pixel to write the first polarity data and the second pixel to write the second polarity data, and the pair Scan signal control Pixel and the second pixel charge sharing; wherein the plurality of frame time (frame time) having at least two different values of the delay time. The display device of claim 1, wherein the frame time includes a first frame time and a second frame time, The delay time value includes a first delay time value and a second delay time value, and the first frame time and the second frame time respectively correspond to the first delay time value and the second delay time value, the first A delay time value and the second delay time value are different from each other. The display device of claim 2, wherein the frame time includes a third frame time and a fourth frame time, the delay time values including a third delay time value and a fourth a delay time value, the third frame time and the fourth frame time respectively correspond to the third delay time value and the fourth delay time value, the first delay time value, the second delay time value, the first The three delay time values and the fourth delay time values are different from each other. The display device of claim 2, wherein the frame time includes a third frame time and a fourth frame time, the delay time values including a third delay time value and a fourth a delay time value, the third frame time and the fourth frame time respectively correspond to the third delay time value and the fourth delay time value, the third delay time value being the same as the first delay time value, and The fourth delay time value is the same as the second delay time value. The display device of claim 1, wherein the first pixel comprises: a first liquid crystal capacitor; and a first transistor controlled by the main scan signal to electrically connect the first polarity data Wire to the first liquid crystal capacitor; a second liquid crystal capacitor; a second transistor controlled by the main scan signal to electrically connect the first a first data capacitor to the second liquid crystal capacitor; a first dark region capacitor; and a third transistor controlled by the sub-scanning signal to electrically connect the first dark region capacitor to the second liquid crystal capacitor; The second pixel includes: a third liquid crystal capacitor; a fourth transistor controlled by the main scanning signal to electrically connect the second polarity data line to the third liquid crystal capacitor; a fourth liquid crystal capacitor; a fifth transistor controlled by the main scanning signal electrically connecting the second polarity data line to the fourth liquid crystal capacitor; a second dark region capacitor; and a sixth transistor controlled by the pair The scan signal is electrically connected to the second dark region capacitor to the fourth liquid crystal capacitor. The display device of claim 1, wherein the timing controller adjusts the delay time values according to a frame number. The display device of claim 1, wherein the upper limit of the delay time values depends on a liquid crystal delay time of one of the liquid crystal display panels. The display device according to claim 7, wherein the liquid crystal delay time is a time when the transmittance of the liquid crystal molecules is changed from 0 to 10% after the voltage is applied. The display device of claim 1, wherein the sub-scanning signal enables the sub-scanning line during each frame time The time is greater than the time at which the main scan signal enables the main scan line. The display device of claim 9, wherein when the main scanning signal disables the main scanning line, the sub scanning signal enables the sub scanning line, and the sub scanning signal includes A plurality of scan pulses.