TWI571997B - Semiconductor structure and manufacturing method for the same - Google Patents

Description

Semiconductor structure and method of manufacturing same

The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a memory and a method of fabricating the same.

In recent years, the structure of semiconductor elements has been constantly changing, and the memory storage capacity of the elements has also been increasing. Memory devices are used in many products, such as MP3 players, digital cameras, computer files, and the like. As applications increase, so does the demand for memory devices toward smaller sizes and larger memory capacities. In response to this demand, it is required to manufacture a memory device having a high component density and a small size.

Therefore, designers are all committed to developing a three-dimensional memory device that not only has many stacked planes but also achieves higher memory storage capacity, has a smaller size, and has good characteristics and stability.

According to an embodiment, a semiconductor structure is disclosed that includes a conductive layer, a conductive structure, and a dielectric layer. The conductive layer defines a plurality of adjacent first openings. A conductive structure surrounds a portion of the conductive layer between the first openings. Dielectric layer The conductive layer and the conductive structure are opened.

In accordance with another embodiment, a semiconductor structure is disclosed that includes stacked conductive stripes, a conductive configuration, and a conductive configuration. The conductive structure surrounds the conductive stripes. The dielectric layer separates the conductive stripes from the conductive structure.

According to still another embodiment, a method of fabricating a semiconductor structure is disclosed that includes the following steps. Several insulating layers and several conductive layers are stacked alternately. A plurality of first openings are formed through the insulating layer and the conductive layer. A portion of the insulating layer exposed by the first opening is removed to form a plurality of second openings having a size larger than the first opening in the insulating layer. A dielectric layer is formed to cover a portion of the conductive layer exposed by the first opening and the second opening. A plurality of electrically conductive structures are formed on the dielectric layer.

102‧‧‧Insulation

104‧‧‧ Conductive layer

106‧‧‧Semiconductor substrate

108‧‧‧hard mask

110‧‧‧ first opening

112‧‧‧ second opening

114‧‧‧First direction

116‧‧‧second direction

118‧‧‧Parts

120‧‧‧Insulation

122‧‧‧ dielectric layer

124‧‧‧Electrical structure

126‧‧‧First conductive part

128‧‧‧Second conductive part

130‧‧‧Insulated plug

132‧‧‧ third opening

134‧‧‧ Conductive stripes

136‧‧‧ third direction

138‧‧‧Electrically connected

P1, P2‧‧‧ spacing

FIGS. 1A through 5C illustrate a method of fabricating a semiconductor structure in accordance with an embodiment.

FIGS. 1A through 5C illustrate a method of fabricating a semiconductor structure in accordance with an embodiment. The reference numeral A is a top view of the semiconductor structure (the hard mask 108 is not shown), and the lines labeled B and C are respectively a cross-sectional view of the semiconductor structure along the BB line and the CC line.

Referring to FIGS. 1A to 1C, the insulating layer 102 and the conductive layer 104 are alternately stacked on the semiconductor substrate 106. The semiconductor substrate 106 can include a germanium substrate, an insulating layer overlying germanium (SOI), or other suitable material structure. Insulation layer 102 Oxides, nitrides, oxynitrides such as cerium oxide, cerium nitride, cerium oxynitride, or other suitable dielectric materials may be included. An etch process can be used to define a first opening 110 in the conductive layer 104 (e.g., undoped polysilicon) exposed from the topmost hard mask 108 (e.g., tantalum nitride) and the insulating layer 102 (e.g., tantalum oxide). The etching process includes, for example, wet etching, dry etching, or other suitable methods.

Referring to FIGS. 2A-2C, the portion of the insulating layer 102 exposed by the first opening 110 is removed to define a second opening 112 in the insulating layer 102, the size of which is larger than the first opening 110 of the conductive layer 104, and The first opening 110 is connected. The etching process used has a higher etch selectivity to the insulating layer 102 than the conductive layer 104 (ie, the etch rate of the etch process to the insulating layer 102 is higher than the conductive layer 104, or the conductive layer 104 is not substantially etched). ). For example, the oxide insulating layer 102 can be removed using a hydrofluoric acid dilute solution (DHF), a buffered oxide etchant (BOE), or other suitable etchant. In one embodiment, the pitch P1 of the first opening 110 in the first direction 114 is greater than the pitch P2 in the second direction 116, and the etching process control (eg, controlling the time of the etching process) is removed. The insulating layer 102 is of a material of a particular size, thereby leaving a portion 118 (Figs. 2A and 2C) of the insulating layer 102 between the first openings 110 in the first direction 114 and communicating with the second direction 116. The first openings (as shown in FIGS. 2A and 2B) are formed apart from each other in the first direction 114 (2A and 2C), and are simultaneously connected in the second direction 116 to be different. A second opening 112 in the form of an opening 110 (Figs. 2A and 2B). In an embodiment, after the second opening 112 is formed, the insulating layer 102 is left in the first opening 110, and the insulating portion between the four is adjacent Dividing 120 (Fig. 2A), the insulating portion 120 can support the upper and lower conductive layers 104 to avoid shorting or collapse of the conductive layer 104.

Referring to FIGS. 3A to 3C , a dielectric layer 122 is formed to cover all of the conductive layer 104 and the insulating layer 102 exposed by the first opening 110 and the second opening 112 . Filling the first opening 110 of the conductive layer 104 with the second of the insulating layer 102 with a conductive material (eg, P+ type polysilicon, N+ type polysilicon, TiN, TaN, W, Ti, Cu, or other conformal conductors) The opening 112 is formed to form the conductive structure 124 on the dielectric layer 122, wherein the conductive structure 124 includes a first conductive portion 126 filled in the first opening 110, and a second filled in the second opening 112 and connected to the first conductive portion 126 Conductive portion 128. The dielectric layer 122 over the hard mask 108 can be removed from the conductive material using a chemical mechanical polishing process. The second conductive portion 128 is disposed above and below the conductive layer 104. In addition, the dielectric layer 122 electrically isolates the conductive layer 104 from the conductive structure 124 and electrically isolates the conductive structures 124 at different locations in the first direction 114.

Referring to FIG. 3B, the conductive structure 124 surrounds the upper and lower surfaces and the opposite sidewalls of the conductive layer 104 between the first openings 110. A single second conductive portion 128 overlaps the first conductive portion 126 of the different first openings 110.

Referring to FIGS. 4A-4C, an insulating plug 130 is formed through the conductive layer 104 and the insulating layer 102 to electrically insulate the conductive structure 124. The method of forming the insulating plug 130 includes defining a third opening 132 in the conductive layer 104 and the insulating layer 102, and forming the third opening 132 with a dielectric material such as an oxide. The dielectric material above the hard mask 108 can be removed using a chemical mechanical polishing process. In one embodiment, the insulating plugs 130 are disposed between the first conductive portions 126 in the first direction 114 and at least adjacent to the dielectric layer 122 on the first conductive portions 126 (or in the first openings 110). A conductive stripe 134 extending in the first direction 114 is defined in the conductive layer 104 with the dielectric layer 122 (FIG. 4D, which only shows the element configuration in a single layer of the conductive layer 104). In other embodiments, the insulating plug 130 may further extend to contact the first conductive portion 126 without affecting the electrical conduction effects of the different layers of the conductive structure 124 in the third direction 136 (vertical direction).

The semiconductor structure of an embodiment is a three-dimensional stacked memory array in which conductive stripes 134 extending in a first direction 114 are used as bit lines and conductive structures 124 extending in a second direction 116 are used as word lines. For example, the dielectric layer 122 between the conductive strips 134 and the conductive traces 124 can be an ONO structure, an ONONO structure, an ONONONO structure, or a tunneling material/trapping material/blocking material (blocking) The material layer formed by the material is applied to the storage material of the NAND gate. For example, the first layer of oxide and nitride from the inside to the outside, and the oxide of the second layer (O1N1O2) are tunneling materials, the second layer of nitride (N2) is the trapping material, and the third layer is oxidized. The material (O3), or the third layer oxide/nitride or the fourth layer oxide (O3/N3/O4) is a barrier material. In one embodiment, the semiconductor structure uses a tantalum-alumina-nitride-oxide-silicon (TANOS) structure including a Si substrate, an oxide/tantalum nitride/alumina (OX/SiN). /Al2O3) Dielectric, and TaN gate.

As shown in FIG. 4B, the device has a conductive structure 124 (gate) surrounding A gate-all-around (GAA) structure of conductive strips 134 (bit line channels). This type of structure has excellent gate control capability and large cell current, which is superior to double gate or single gate devices. Moreover, since the bit line (the conductive stripe 134) is surrounded by the gate, the effect is less susceptible to other bit lines, so the coupling interference in the Z direction between the bit lines is lower.

In some comparative examples, the formation of bit lines is defined by patterning a stack of conductive layers and insulating layers to form elongated openings. In other words, the entire side wall is exposed to the opening during the formation of the bit line. However, a high aspect ratio bit line, which is open on both sides and not supported by other components, is susceptible to other stresses (eg, a liquid filled in the opening during the immersion cleaning step, The bending caused by the stress caused by the immersion and pulling action causes the structure to be damaged or even forms an undesired short circuit, which reduces the product yield.

In the embodiment of the present disclosure, the conductive strips 134 are formed by patterning openings (including the first opening 110 and the third opening 132), and the portion of the material used to form the conductive strips 134 is supported during the process. Compared with the comparative example, it has a relatively stable structural feature, is not prone to deformation, and has high product reliability.

Referring to FIGS. 5A-5C, in some embodiments, a plurality of conductive connections 138 extending in the second direction 116 and separated from each other, such as a word line connection, may also be formed on the conductive structure 124. Other suitable contact structures and interlayer dielectric layers (not shown) may also be formed.

The disclosure is not limited to the above embodiments illustrated by the drawings, and It can be adjusted according to actual needs or other designs.

For example, in an embodiment, the first conductive portion 126 (first opening 110) of the single layer in the conductive layer 104 is not limited to the 4 of the 2x2 illustrated above (the upper one is defined to extend toward the first direction 114) Conductive strips 134), and any other number can be used arbitrarily, for example, 64 of 9x8 (eight defined between the first direction 114 and electrically isolated from the insulating plug 130 by the dielectric layer 122) Conductive stripes 134), or 128 of 9x16, etc., wherein a single second conductive portion 128 extending in the second direction 116 (in 8 or 16) simultaneously overlaps with the nine first conductive portions 126 to form more An array device of memory cells.

In some embodiments, the first opening 110 (FIG. 1A) can be designed such that the pitch P1 in the first direction 114 is equal to the pitch P2 in the second direction 116, and thus the second formed after the etching process is performed. The openings 112 are interconnected not only in the second direction 116 (as shown in FIG. 2A) but also in the first direction 114 (not shown). Although the conductive structure 124 is connected to the first direction 114 and the second direction 116 at the same time (not shown), after the insulating plug 130 is formed, the conductive structure 124 can be electrically insulated from each other through the insulating plug 130, and A word line extending along the second direction 116 is defined so that a memory device of the desired electrical characteristics can still be formed. In this example, the etching process for forming the second opening 112 controls the insulating portion 120 between the adjacent openings of the first opening 110, the insulating portion 120 capable of supporting the upper and lower conductive portions. Layer 104 prevents the conductive layer 104 from being deformed by shorting or collapse.

In addition to the multilayer structure, the dielectric layer 122 can also use a single layer of junctions. Structure. The dielectric component of the embodiment may be made of an oxide, a nitride, an oxynitride such as hafnium oxide, tantalum nitride, or hafnium oxynitride, or other suitable materials. The conductive element may comprise a polycrystalline germanium, a metal such as titanium nitride (TiN), titanium (Ti), tantalum nitride (TaN), tantalum (Ta), gold, tungsten, or the like.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

102‧‧‧Insulation

104‧‧‧ Conductive layer

108‧‧‧hard mask

110‧‧‧ first opening

112‧‧‧ second opening

116‧‧‧second direction

122‧‧‧ dielectric layer

124‧‧‧Electrical structure

126‧‧‧First conductive part

128‧‧‧Second conductive part

136‧‧‧ third direction

Claims (10)

A semiconductor structure comprising: a conductive layer defining adjacent first openings; a conductive structure surrounding a portion of the conductive layer between the first openings; and a dielectric layer separating the conductive The layer and the electrically conductive structure. The semiconductor structure of claim 1, wherein the conductive structure comprises: a plurality of first conductive portions filling the first openings of the conductive layer; and a second conductive portion connecting the first portions a conductive portion disposed above and below the conductive layer. The semiconductor structure of claim 1, comprising: a plurality of the conductive structures; and a plurality of insulating plugs electrically insulating the conductive structures. The semiconductor structure of claim 1, further comprising a plurality of insulating plugs, wherein the conductive structure comprises a plurality of first conductive portions separated from each other, the insulating plugs being disposed in a first direction Between the first conductive portions, a conductive strip extending in the first direction is defined in the conductive layer with the dielectric layer. The semiconductor structure of claim 1, wherein the conductive structure surrounds the upper and lower surfaces and the opposite sidewalls of the conductive layer between the first openings. A semiconductor structure comprising: a plurality of stacked conductive stripes; a conductive structure surrounding the conductive stripes; and a dielectric layer separating the conductive stripes from the conductive structure. The semiconductor structure of claim 6, further comprising a plurality of insulating plugs defined by the insulating plugs and the dielectric layer. The semiconductor structure of claim 6, wherein the conductive strips extend in a direction perpendicular to an extending direction of the conductive structure, and the conductive strips are used as bit lines, and the conductive structures are used as characters. line. The semiconductor structure according to any one of claims 1 to 8, which is a three-dimensional stacked memory array having a Gate-all-around (GAA) structure. A method for fabricating a semiconductor structure includes: stacking a plurality of insulating layers and a plurality of conductive layers alternately; forming a plurality of first openings extending through the insulating layers and the conductive layers; removing the insulating layers by the first openings The exposed portion is formed with a plurality of second openings having a size larger than the first openings in the insulating layer; forming a dielectric layer covering the conductive layers exposed by the first openings and the second openings a portion; and forming a plurality of electrically conductive structures on the dielectric layer.