CN105280687B - Semiconductor structure and manufacturing method thereof - Google Patents

Abstract

The invention discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a conductive layer, a conductive structure, and a dielectric layer. The conductive layer defines a plurality of adjacent first openings. The conductive structure surrounds the portion of the conductive layer between the first openings. The dielectric layer separates the conductive layer and the conductive structure.

Description

Semiconductor structure and manufacturing method thereof

technical field

The present invention relates to a semiconductor structure and its manufacturing method, and in particular to a memory and its manufacturing method.

Background technique

In recent years, the structure of semiconductor devices has been constantly changing, and the memory storage capacity of the devices has also been increasing. Storage devices are used in many products, such as storage components in MP3 players, digital cameras, computer files, and so on. With the increase of applications, the demand for storage devices also tends to be smaller in size and larger in storage capacity. In response to this demand, it is necessary to manufacture memory devices with high device density and small size.

Therefore, designers are all devoting themselves to developing a three-dimensional storage device, which not only has many stacked planes to achieve higher memory storage capacity, but also has a smaller size and has good characteristics and stability.

Contents of the invention

According to an embodiment, a semiconductor structure is disclosed, which includes a conductive layer, a conductive structure, and a dielectric layer. The conductive layer defines a plurality of adjacent first openings. The conductive structure surrounds the portion of the conductive layer between the first openings. The dielectric layer separates the conductive layer from the conductive structure.

According to another embodiment, a semiconductor structure is disclosed, which includes a plurality of stacked conductive stripes, a conductive structure, and a conductive structure. A conductive construction surrounds the conductive stripe. The dielectric layer separates the conductive stripes and the conductive structures.

According to yet another embodiment, a method of fabricating a semiconductor structure is disclosed, which includes the following steps. A plurality of insulating layers and a plurality of conductive layers are stacked alternately. A plurality of first openings are formed to penetrate the insulating layer and the conductive layer. A portion of the insulating layer exposed by the first opening is removed to form a plurality of second openings in the insulating layer that are larger in size than the first openings. A dielectric layer is formed to cover the portion of the conductive layer exposed by the first opening and the second opening. A plurality of conductive structures are formed on the dielectric layer.

Description of drawings

1A to 5C illustrate a method for fabricating a semiconductor structure according to an embodiment.

【Symbol Description】

102: insulation layer

104: conductive layer

106: Semiconductor substrate

108: Hard mask

110: first opening

112: second opening

114: First Direction

116: Second Direction

118: part

120: insulation part

122: Dielectric layer

124: Conductive structure

126: first conductive part

128: second conductive part

130: insulating plug

132: The third opening

134: Conductive stripes

136: Third Direction

138: Conductive connection

P1, P2: Pitch

Detailed ways

1A to 5C illustrate a method for fabricating a semiconductor structure according to an embodiment. Wherein A is a top view of the semiconductor structure, and B and C are cross-sectional views of the semiconductor structure along BB and CC lines, respectively.

Referring to FIG. 1A to FIG. 1C , insulating layers 102 and conductive layers 104 are alternately stacked on a semiconductor substrate 106 . The semiconductor substrate 106 may include a silicon substrate, silicon-on-insulator (SOI), or other suitable material structures. The insulating layer 102 may include oxide, nitride, oxynitride, such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials. An etching process may be used to define the first opening 110 in the conductive layer 104 (eg, undoped polysilicon) and the insulating layer 102 (eg, silicon oxide) exposed by the topmost hard mask 108 (eg, silicon nitride). The etching process includes, for example, wet etching, dry etching, or other suitable methods.

Referring to FIGS. 2A to 2C , the portion of the insulating layer 102 exposed by the first opening 110 is removed to define a second opening 112 in the insulating layer 102, which is larger in size than the first opening 110 of the conductive layer 104 and communicates with the first opening 110. One opening 110 . Compared with the conductive layer 104, the etching process used has a higher etching selectivity for the insulating layer 102 (that is, the etching rate of the insulating layer 102 by the etching process is higher than that of the conductive layer 104, or substantially no etching. etch the conductive layer 104). For example, the oxide insulating layer 102 may be removed by dilute hydrofluoric acid (DHF), buffered oxide etchant (BOE), or other suitable etchant. In one embodiment, the pitch P1 of the first opening 110 in the first direction 114 is greater than the pitch P2 in the second direction 116, and the etching process is controlled (for example, the time of the isotropic etching process is controlled) removing material of a specified size from the insulating layer 102 , thereby leaving a portion 118 of the insulating layer 102 between the first openings 110 in the first direction 114 ( FIGS. 2A and 2C ), and communicating with the opening in the second direction 116 The first openings (as shown in FIG. 2A and FIG. 2B ) are formed to be separated from each other in the first direction 114 ( FIG. 2A and FIG. 2C ), and are simultaneously connected to different first openings 110 in the second direction 116 ( FIG. 2A and FIG. 2B) the second opening 112 in the form. In the embodiment, after the second opening 112 is formed, the insulating layer 102 is left in the insulating portion 120 ( FIG. 2A ) between adjacent four of the first openings 110 . layer 104, so as to prevent the conductive layer 104 from being deformed, shorted or collapsed.

Referring to FIGS. 3A to 3C , a dielectric layer 122 is formed to cover all the conductive layer 104 and the insulating layer 102 exposed by the first opening 110 and the second opening 112 . Fill the first opening 110 of the conductive layer 104 and the second opening 110 of the insulating layer 102 with a conductive material (such as P+ type polysilicon, N+ type polysilicon, TiN, TaN, W, Ti, Cu, or other conformal conductors). opening 112 to form a conductive structure 124 on the dielectric layer 122, wherein the conductive structure 124 includes a first conductive portion 126 filled in the first opening 110, and a second conductive portion 126 filled in the second opening 112 and connected to the first conductive portion 126. conductive portion 128 . The dielectric layer 122 and the conductive material above the hard mask 108 may be removed using a chemical mechanical polishing process. The second conductive portion 128 is disposed above and below the conductive layer 104 . In addition, the dielectric layer 122 electrically isolates the conductive layer 104 from the conductive structure 124 , and electrically isolates the conductive structure 124 at different positions in the first direction 114 .

Referring to FIG. 3B , the conductive structure 124 surrounds the upper and lower surfaces and the opposite sidewalls of the conductive layer 104 between the first opening 110 . A single second conductive portion 128 overlaps with the first conductive portions 126 in different first openings 110 .

Referring to FIGS. 4A to 4C , an insulating plug 130 is formed to pass through the conductive layer 104 and the insulating layer 102 to electrically insulate the conductive structure 124 . The method for forming the insulating plug 130 includes defining a third opening 132 in the conductive layer 104 and the insulating layer 102 , and filling the third opening 132 with a dielectric material (such as oxide). The dielectric material above the hard mask 108 may be removed using a chemical mechanical polishing process. In one embodiment, the insulating plug 130 is disposed between the first conductive parts 126 in the first direction 114, and at least adjacent to the dielectric layer 122 on the first conductive part 126 (or in the first opening 110), so as to Conductive stripes 134 extending toward the first direction 114 are defined in the conductive layer 104 together with the dielectric layer 122 ( FIG. 4D only shows the device configuration in a single layer of the conductive layer 104 ). In other embodiments, the insulating plug 130 may further extend to contact the first conductive portion 126 under the premise of not affecting the electrical conduction effect of different layers of the conductive structure 124 in the third direction 136 (vertical direction).

The semiconductor structure of the embodiment is a three-dimensional stacked memory array, wherein the conductive stripes 134 extending in the first direction 114 are used as bit lines, and the conductive structures 124 extending in the second direction 116 are used as word lines. For example, the dielectric layer 122 between the conductive stripes 134 and the conductive structure 124 can be an ONO structure, an ONONO structure, an ONONONO structure, or a tunneling material/trapping material/blocking material ) constitutes a material layer, which is applied to the storage material of a NAND gate (NAND). For example, the first layer of oxide and nitride from the inside to the outside, and the second layer of oxide (O1N1O2) are tunneling materials, the second layer of nitride (N2) is the capture material, and the third layer of oxide (O3), or the third layer of oxide/nitride or the fourth layer of oxide (O3/N3/O4) is the barrier material. In one embodiment, the semiconductor structure uses a titanium-alumina-nitride-oxide-silicon (TANOS) structure, which includes a Si substrate, oxide/silicon nitride/aluminum oxide (OX/SiN /Al ₂ O ₃ ) dielectric, and a TaN gate.

As shown in FIG. 4B , the device has a gate-all-around (GAA) structure in which a conductive structure 124 (gate) surrounds a conductive strip 134 (bit line channel). This structure has good gate control ability and large cell current, which is better than double gate or single gate devices. Moreover, because the bit lines (conductive stripes ( 134 ) are surrounded by the gate, they are less susceptible to the influence of other bit lines, so the coupling interference in the Z direction between the bit lines is relatively low.

In some comparative examples, the formation of the bit lines is defined by patterning the stack of conductive layers and insulating layers to form elongated openings. In other words, during the formation of the bit line, the entire sidewall will be exposed to the opening. However, high aspect ratio bitlines, which are open on both sides and not supported by other components, are susceptible to other stresses (such as liquid filling the opening during the immersion cleaning step, or Bending occurs due to the influence of stress caused by dipping and pulling actions, which damages the structure and even forms an undesired short circuit, reducing product yield.

In an embodiment of the present invention, the conductive stripes 134 are formed by patterning openings (including the first opening 110 and the third opening 132 ), and the material part used to form the conductive stripes 134 is supported during the process, so (relatively Compared with the comparative example), it has more stable structural characteristics, is less likely to be deformed, and has high product reliability.

Referring to FIGS. 5A to 5C , in some embodiments, a plurality of conductive connections 138 extending along the second direction 116 and separated from each other, such as word line connections, may also be formed on the conductive structure 124 .

Other suitable contact structures and interlayer dielectric layers (not shown) may also be formed.

The present invention is not limited to the embodiments described above with illustrations, and may be appropriately adjusted according to actual requirements or other designs.

For example, in the embodiment, the first conductive portion 126 (the first opening 110 ) of a single layer in the conductive layer 104 is not limited to the 2x2 four shown above (there is a definition extending toward the first direction 114 conductive strips 134), and other more numbers can be used arbitrarily, such as 64 of 9x8 (8 conductive strips extending toward the first direction 114 and electrically isolated from the insulating plug 130 by the dielectric layer 122 are defined between them. stripes 134), or 128 of 9x16, etc., wherein a single second conductive portion 128 extending toward the second direction 116 (in 8 or 16) overlaps with 9 first conductive portions 126 at the same time to form more storage Cell array device.

In some embodiments, the first opening 110 ( FIG. 1A ) can be designed such that the pitch P1 in the first direction 114 is equal to the pitch P2 in the second direction 116 , and therefore after performing the etching process,

The formed second openings 112 are not only connected to each other in the second direction 116 (as shown in FIG. 2A ), but also connected to each other in the first direction 114 (not shown). Although this will cause the conductive structure 124 to connect and extend in the first direction 114 and the second direction 116 at the same time (not shown), after the insulating plug 130 is formed, since the conductive structure 124 can be electrically insulated from each other through the insulating plug 130 , and define word lines extending along the second direction 116 , so a storage device with expected electrical characteristics can still be formed. In this example, the etching process used to form the second opening 112 is controlled to leave the insulating layer 102 between the adjacent four of the first opening 110 and the insulating portion 120, which can support the upper and lower parts. The conductive layer 104 is used to prevent the conductive layer 104 from being deformed, shorted or collapsed.

In addition to the multi-layer structure, the dielectric layer 122 can also use a single-layer structure. The material of the dielectric element in the embodiment may include oxide, nitride, oxynitride, such as silicon oxide, silicon nitride, or silicon oxynitride, or other suitable materials. The conductive element may comprise polysilicon, metals such as titanium nitride (TiN), titanium (Ti), tantalum nitride (TaN), tantalum (Ta), gold, tungsten, and other suitable materials.

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (8)

1. a kind of semiconductor structure, including：

One conductive layer defines adjacent multiple first openings；

One electricity conductive construction, around part of the conductive layer between these first openings；And

One dielectric layer separates the conductive layer and the electricity conductive construction；

Wherein, which includes：

Multiple first current-carrying parts fill these first openings of the conductive layer；And

One second current-carrying part connects these the first current-carrying parts, and configures the upper and lower in the conductive layer.

2. semiconductor structure according to claim 1, including：

Multiple electricity conductive constructions；And

Multiple insulated plugs, be electrically insulated these electricity conductive constructions.

3. semiconductor structure according to claim 1 further includes multiple insulated plugs, wherein the electricity conductive construction includes mutual Separated multiple first current-carrying parts,

Between these first current-carrying parts on a first direction of these insulated plugs configuration, with the dielectric layer in the conduction Go out the conductive stripe extended toward the first direction defined in layer.

4. semiconductor structure according to claim 1, the wherein electricity conductive construction be looped around the conductive layer between these first On upper and lower surface and opposing sidewalls between opening.

5. a kind of semiconductor structure, including：

Multiple conductive stripes of lamination；

One electricity conductive construction, around these conductive stripes；And

One dielectric layer separates these conductive stripes and the electricity conductive construction；

Wherein, the extending direction of these conductive stripes is perpendicular to the extending direction of the electricity conductive construction, these conductive stripes are to use Make bit line, which is used as wordline；

The electricity conductive construction includes：

Multiple first current-carrying parts, multiple first current-carrying part are separated from each other；And

One second current-carrying part connects these the first current-carrying parts.

6. semiconductor structure according to claim 5 further includes multiple insulated plugs, these conductive stripes are exhausted by these Edge plug is defined with the dielectric layer.

7. according to the semiconductor structure described in any one of claim 1-6, for circulating type grid (Gate-all- Around, GAA) structure 3-D stacks memory array.

8. a kind of manufacturing method of semiconductor structure, including：

The interaction multiple insulating layers of lamination and multiple conductive layers；

Multiple first openings are formed through these insulating layers and these conductive layers；

Remove the part that these insulating layers are exposed by these first openings, with formed in these insulating layers size be more than these the Multiple second openings of one opening；

It forms a dielectric layer and covers the part that these conductive layers are exposed by these first openings with these second openings；And

Multiple electricity conductive constructions are formed on the dielectric layer, the plurality of electricity conductive construction is filled in the first opening and absolutely of dielectric layer Second opening of edge layer.