TWI536747B - Analog-to-digital conversion apparatus and method thereof - Google Patents

Description

Analog digital conversion device and method thereof

The present invention relates to a continuous-approximation-register (SAR) analog-to-digital converter (ADC), and more particularly to an analog-to-digital converter and method thereof.

SAR ADCs have been widely used in many applications. The SAR ADC converts the analog input signal into digital output data. The SAR ADC has a SAR controller and a digital-to-analog converter (DAC). The SAR controller is used for continuous approximation, and the DAC is used to convert the digital code into a voltage. In order for a SAR ADC to have a high resolution conversion, a high resolution DAC is usually required. This requires more steps to update the digital code in the case of continuous approximation, ie, it takes a longer time to complete the continuous approximation, thus limiting the conversion speed of the SAR ADC. In short, the prior art is difficult to achieve while having high resolution and high conversion speed.

Accordingly, it would be desirable to provide an apparatus and method that provides a SAR ADC with an acceptable balance between resolution and conversion speed.

The analog-to-digital conversion apparatus and method of the present invention can allow a continuous-approximation-register (SAR) analog-to-digital converter to have an acceptable balance between conversion speed and resolution.

In an embodiment, an analog to digital conversion device includes a main analog to digital converter and a secondary analog to digital converter. The main analog-to-digital converter is used to convert the analog input signal into main digital data, and the auxiliary analog digital converter is used to convert the same analog input signal into auxiliary digital data. The main analog-to-digital converter has a first resolution and a first conversion speed, and the auxiliary analog-to-digital converter has a second resolution and a second conversion speed. Wherein the second resolution is lower than the first resolution, and the second conversion speed is faster than the first conversion speed.

The main analog-to-digital converter generates main digital data by performing a continuous progressive program. Here, the continuous progressive procedure includes a fast tracking step based on the value of the auxiliary digit data.

In an embodiment, an analog digital conversion method includes: converting an analog input signal into a main digital data, converting the same analog input signal into auxiliary digital data, and performing a fast tracking step including the value based on the auxiliary digital data. One of the first programs. Here, the main analog-to-digital converter has a first resolution and a first conversion speed, and the auxiliary analog-to-digital converter has a second resolution and a second conversion speed. Wherein the second resolution is lower than the first resolution, and the second conversion speed is faster than the first conversion speed.

In an embodiment, an analog-to-digital conversion method includes: receiving an analog input signal, sampling an analog input signal to generate a first voltage, and using a digital analog converter to generate a second voltage according to a digital code, according to the first The polarity of the difference between the voltage and the second voltage continuously updates the digital code to cause the second voltage to approximate the first voltage, and continuously updates the digital code by updating the digital code directly according to the output of the auxiliary digital analog converter step.

In some embodiments, a higher resolution but lower speed main analog digital converter utilizes a lower resolution but higher speed auxiliary analog to digital converter to initiate an analog input signal that is continuously progressively sampled by a continuous progressive program. .

In some embodiments, analog to digital conversion methods may include performing higher resolution but lower speed analog digital conversions and lower resolution but higher speed analog digital conversions, and utilizing lower resolution but higher speeds. The result of the analog-to-digital conversion accelerates the continuous progressive program by crossing at least one of the successive progressive programs having multiple steps. Among them, the analog conversion of higher resolution but lower speed is based on continuous progressive program.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The following detailed description refers to the various embodiments of the present invention The described embodiments are clear and fully disclosed so that those of ordinary skill in the art can. Different embodiments are not mutually exclusive, and some embodiments may be combined with one or more embodiments to become a new embodiment. Therefore, the following detailed description is not intended to limit the invention.

1 is a functional block diagram of an analog-to-digital conversion apparatus according to an embodiment of the present invention. Referring to FIG. 1, the analog-to-digital converter 100 includes a primary-to-digital converter (ADC) 110 and a secondary ADC 120.

The main ADC 110 receives an analog input signal V _IN and outputs main digital data D _OUT . The auxiliary ADC 120 receives the same analog input signal V _IN but outputs the auxiliary digital data D _AUX and a logic signal DONE. Here, the logic signal DONE is used to signal that the analog digital conversion execution is completed. The logic signal DONE from the secondary ADC 120 is provided to the primary ADC 110 to initiate an analog digital conversion of the primary ADC 110. The master digital data D _OUT from the primary ADC 110 and the secondary digital data D _AUX from the secondary ADC 120 are both digital representations of the same analog input signal V _IN .

However, primary ADC 110 and secondary ADC 120 have different resolutions of analog to digital conversion. In particular, the resolution of the secondary ADC 120 is lower than the resolution of the primary ADC 110. Since the resolution of the secondary ADC 120 is low, the secondary ADC 120 performs analog digital conversion faster than the primary ADC 110. After the auxiliary ADC 120 completes the analog digital conversion, the secondary ADC 120 asserts the logic signal DONE and provides the auxiliary digital data D _AUX to the primary ADC 110 as a rough estimate of the primary digital data D _OUT , thereby allowing the primary ADC 110 to hop Unnecessary conversion steps, thus increasing the overall conversion speed.

Here, the main ADC 110 can be a continuous-approximation-register (SAR) ADC. The main ADC 110 includes a sample-and-hold (S/H) circuit 111, a digital-to-analog converter (DAC) 112, a summing circuit 113, a comparator 114, and a A bootstrapped SAR controller 115 is activated.

The sample and hold circuit 111 samples the analog input signal V _IN to a first voltage V ₁ . The DAC 112 converts a digital code D into a second voltage V ₂ . The summing circuit 113 generates a third voltage V ₃ according to the first voltage V ₁ and the second voltage V ₂ . Here, the third voltage V ₃ represents a difference between the first voltage V ₁ and the second voltage V ₂ . The comparator 114 generates a decision signal D _X according to the detection result of the polarity of the third voltage V ₃ (ie, comparing the third voltage V ₃ with the ground level). The boot loadable SAR controller 115 receives the decision signal D _X , the auxiliary bit data D _{AUX ,} and the logic signal DONE , performs a continuous progressive program according to the decision signal D _X , the auxiliary bit data D _{AUX ,} and the logic signal DONE to continuously update the digital code. D generates the main digital data D _OUT based on the second voltage V ₂ gradually approaching the first voltage V ₁ and at the end of the continuous progressive program based on the final value of the digital code D. During execution of the continuous progressive program, when the logic signal DONE is pulled up, the load-loading SAR controller 115 is activated to directly update the digital code D with the auxiliary digit data D _AUX and skip at least one successive progressive step that should otherwise be performed.

In one embodiment, referring to FIG. 2, the functions of the sample and hold circuit 111, the digital analog converter 112, and the summing circuit 113 can be integrated and implemented by the digital analog conversion circuit 200 having the sample and hold function. The digital analog conversion circuit 200 includes a sampling switch 210, a capacitor array 220, and a DAC switching circuit 230.

For example, but not limited to, the capacitor array 220 includes eight capacitors C ₁ -C ₈ , and each of the capacitors C ₁ -C ₈ has a top plate and a bottom plate. The top plates of the capacitors C ₁ - C ₈ are connected to the common circuit node N _X , and the bottom plates of the capacitors C ₁ - C ₈ are connected to respective internal circuit nodes. For example, the bottom plates of the capacitors C ₁ -C ₈ are connected to the internal circuit nodes N ₁ -N _{8 , respectively} . DAC DAC switch circuit 230 includes eight switches 231 to 238, and the DAC switches 231 to 238 respectively correspond to the capacitance C ₁ ~ C _8. The digit code D is a combination of eight subcodes D ₁ to D ₈ . The subcodes D ₁ to D ₈ control the DAC switches 231 to 238, respectively.

In one embodiment, each of the subcodes D ₁ -D ₈ has three possible values: "-1", "0", "1". When the value of the subcode is "0", the corresponding DAC switch connects the corresponding internal circuit node to ground. When the value of the subcode is "1", the corresponding DAC switch connects the corresponding internal circuit node to the negative reference voltage -V _R . When the value of the subcode is "-1", the corresponding DAC switch connects the corresponding internal circuit node to the positive reference voltage V _R .

For example: When the subcode _{D 1 (D 2, D 3} ,,, or D ₈₎ a value of "0", the switch corresponding to the DAC 231 (or 232, 233,, 238) corresponding to the internal circuit node N ₁ (N ₂ , N ₃ , , , or N ₈ ) is connected to ground. When the value of the subcode D ₁ (D ₂ , D ₃ , , or D ₈ ) is "1", the corresponding DAC switch 231 (232, 233, , or 238) will correspond to the internal circuit node N ₁ ( N ₂ , N ₃ , , or N ₈ ) is connected to the negative reference voltage -V _R . When the value of the subcode D ₁ (D ₂ , D ₃ , , or D ₈ ) is "-1", the corresponding DAC switch 231 (232, 233, , or 238) will correspond to the internal circuit node N ₁ (N ₂ , N ₃ , , or N ₈ ) is connected to the positive reference voltage V _R .

At the beginning of the analog-to-digital conversion (executed by the main ADC 110 in the first diagram of the digital analog conversion circuit 200 in Fig. 2), all subcodes D ₁ to D _{8 are} reset to "0", so all internal Circuit nodes N ₁ ~N _{8 are} connected to ground.

During the sampling period (at this time, the sampling signal SAMP is pulled up), the common circuit node N _X is connected to the analog input signal V _IN via the sampling switch 210, and thus the analog input signal V _{IN is} sampled by the capacitors C ₁ to C ₈ .

In the case where the sampling signal SAMP is not pulled up, the sampling switch 210 is turned on, and the level of the analog input signal V _IN is held and stored on the capacitors C ₁ to C ₈ ; thus effectively implementing the sample and hold circuit in FIG. 1 111 features. In other words, the first voltage V ₁ in FIG. ₁ is implicit and stored on the capacitors C ₁ -C ₈ .

During the execution of the continuous progressive program, the subcodes D ₈ , D ₇ , D ₆ , D ₅ , D ₄ , D ₃ , D ₂ , D _{1 are} successively updated according to the value of the decision signal D _X (as shown in FIG. 1). So that the internal circuit nodes N ₈ , N ₇ , N ₆ , N ₅ , N ₄ , N ₃ , N ₂ , N _{1 are} conditionally switched to be connected to the positive reference voltage V _R or the negative reference voltage -V _R ; The function of the DAC 112 in Fig. 1 is effectively realized. In other words, the second voltage V _{2 in} FIG. 1 is implicit and stored on the capacitors C ₁ -C ₈ .

Since the first voltage V ₁ and the second voltage V ₂ are both implicit and stored on the capacitors C ₁ -C ₈ , they are implicitly added; thus effectively implementing the summing circuit 113 in FIG. 1 The function, and at the voltage level of the common circuit node N _X (hereinafter referred to as the common mode potential V _X ), realizes the output of the summing circuit 113 in Fig. 1, that is, the third voltage V ₃ .

Referring back to FIG. 1, in either embodiment, the secondary ADC 120 is used to accelerate the conversion of the primary ADC 110. Therefore, the analog-to-digital conversion of the auxiliary ADC 120 is performed faster than the main ADC 110.

In an embodiment, the secondary ADC 120 has a lower resolution than the primary ADC 110. For example, a lower resolution ADC uses a smaller capacitance to speed up comparison and settling, and it can be faster than a higher resolution ADC. The secondary ADC 120 has a lower resolution than the primary ADC 110 but is faster than the primary ADC 110 such that the logic signal DONE is pulled up before the primary ADC 110 completes the conversion.

In one embodiment, the secondary ADC 120 is a 4-bit ADC and therefore has a lower resolution than the 4 most significant bits (MSBs) of the primary ADC 110. That is, the auxiliary digit data D _{AUX is} a rough estimate of the subcodes {D ₈ , D ₇ , D ₆ , D ₅ } of the four most significant bits of the main ADC 110.

Figure 3 is a schematic diagram of an example waveform of the circuit shown in Figure 2. Referring to Figures 1, 2 and 3, during the sampling period in which the sampling signal SAMP is pulled up, the second voltage V ₂ is implicitly zero, and the first voltage V ₁ implicitly tracks the analog input signal V _IN (in this case Equal to the common mode potential V _X ). At time point 320 (when the sampling signal SAMP is not pulled), the first voltage V ₁ and therefore is maintained implicitly common mode potential V _X. Then, the polarity of the common mode potential V _X is resolved into the subcode D ₈ . At time 328, subcode D ₈ is resolved to -1 (because common mode potential V _X is negative) and updated, which causes DAC switch 238 to connect internal circuit node N ₈ to positive reference voltage V _R (eg, 2 is shown), thus making the common mode potential V _X higher. After each time the common mode potential V _X is stabilized in accordance with the value of the subcode D ₈ , the polarity of the common mode potential V _X is resolved into the subcode D ₇ . At time 327, subcode D ₇ is resolved to 1 (because the common mode potential V _X is positive) and updated, which causes DAC switch 237 to connect internal circuit node N ₇ to a negative reference voltage -V _R (eg, As shown in FIG. 2), thus enabling lower common mode voltage V _X. The secondary ADC 120 performs its analog digital conversion every time the value of the subcode D ₈ is stabilized. At time point 326, the logic signal DONE is pulled up and the value of the auxiliary bit data D _AUX is acceptable. At this moment, only the subcode D ₈ and the subcode D ₇ are parsed; however, the auxiliary digit data D _AUX (which is a rough estimate of the subcode {D ₈ , D ₇ , D ₆ , D ₅ }) is acceptable. time, can be used directly to digital data D _AUX auxiliary updated subcode _{{D 8, D 7, D} 6, D 5}. That is, the steps of parsing the subcodes D ₆ , D ₅ can be crossed, and these parsing steps are replaced with a "fast track" step based on the value of the auxiliary digit data D _AUX . Conversely, if the auxiliary digit data D _AUX does not exist or is not appropriate, then these parsing steps are necessary.

In an embodiment, the boot loader SAR controller 115 includes and uses the logic table shown in FIG. 4 to update the _subcodes according to the value of each of the auxiliary digit data D _AUX (the 4-digit number from 0 to 15). {D ₈ , D ₇ , D ₆ , D ₅ }.

In another embodiment, if there is an inconsistency between the logical table and the value that has been parsed in the continuous progressive program (ie, the subcode {D ₈ , D ₇ } mentioned in the foregoing embodiment), according to FIG. 4 The logical table shown cannot fully map the subcodes {D ₈ , D ₇ , D ₆ , D ₅ }. When the detected inconsistencies, will maintain the value parsed, and updates the remaining value (i.e., sub-code in the foregoing embodiment of _{{D 6, D 5})} , such that the minimum code facilitator {D _8, D ₇ The difference between D ₆ , D ₅ } and the auxiliary digit data D _AUX .

For example, if the subcode {D ₈ , D ₇ } has been resolved to {-1, 1}, but the auxiliary digit data D _AUX is 8 (the logical table according to Figure 5 should be mapped to subcode {D ₈ , D ₇ , D ₆ , D ₅ }={1, -1, -1, -1}), thus maintaining the subcode {D ₈ , D ₇ } as {-1, 1} and updating the subcode {D ₆ , D ₅ } is {-1, -1}. That is, the subcodes {D ₈ , D ₇ , D ₆ , D ₅ } are set to {-1, 1, -1, -1}, and the resolved values of the subcodes {D ₈ , D ₇ } are not changed. This result is most similar to the auxiliary digit data D _AUX of 8.

Although the difference between the auxiliary digital data D _AUX and the most significant bit that has been resolved by the primary ADC 110 may result in erroneous output data (ie, primary digital data D _OUT ), as long as the least significant bit of the primary ADC 110 ( In the embodiment of Fig. 2, the redundancy and the redundancy are implemented between the corresponding subcodes D ₁ to D ₄ ), and this error can be tolerated and corrected. The principle of using redundancy in the least significant bits to correct errors in the most significant bits is well known in the art and will not be described again.

The boot loadable SAR controller 115 shown in Fig. 1 is a finite state machine. Fig. 5 is a flow chart showing an embodiment of the control function of the boot loadable SAR controller 115 shown in Fig. 1. Referring to Fig. 5, after the ADC is started (step 501), the ADC initializes the digit code D, that is, sets the subcodes {D ₈ , D ₇ , , D ₁ } to 0 (step 503). The ADC then samples the analog input signal V _IN with a capacitance C ₁ - C ₈ (eg, by pulling up and then pulling up the sampled signal SAMP, as shown in FIG. 2) (step 505). Next, the ADC begins a continuous progressive process by setting an internal variable n to 8 (representing the number of capacitors used) (step 507).

Then, the ADC checks if the internal variable n is 0 (step 509); if the internal variable n is not 0, it indicates that the continuous progressive program has not been completed. And, the ADC checks if the internal variable n is greater than 4 and whether the logic signal DONE is pulled up (step 511). If the internal variable n is not greater than 4 or the logic signal DONE is not pulled up, the polarity of the decision signal D _X is detected (step 513) and the subcode D _{n is} updated based on the polarity of the decision signal D _X (step 515). If the internal variable n is greater than 4 and the logic signal DONE is also pulled up, the subcode {D ₈ , D ₇ , D ₆ , D ₅ } is updated directly based on the auxiliary digit data D _AUX (step 521) and the internal variable n is set to 5 (Step 522) to indicate that subcode D ₅ has been updated.

After the subcode D _n or the subcode {D ₈ , D ₇ , D ₆ , D ₅ } is updated (step 515 or step 522), the ADC waits for the capacitors C ₁ - C _{8 to} stabilize (step 517). The ADC then reduces the internal variable n (step 519), for example: the ADC subtracts the internal variable n by one. Next, the loop returns to check if the internal variable n is 0 (step 509); if the internal variable n is 0, it indicates that the continuous progressive program is completed. The ADC then calculates the value of the main digital data D _OUT based on the subcodes {D ₈ , D ₇ , D ₆ , D ₅ } (step 527). Next, the ADC returns to step 503 by looping to continue to perform the next analog-to-digital conversion.

In an embodiment, the value of subcode D ₀ will be included in the calculation of the master digital data D _OUT . In some embodiments, the master digital data D _OUT is calculated according to the following formula.

(1)

In other words, by the access control sub-code of which capacitor is connected to the discretion of the weight subcode weight _n-D, and the additional weight of the subcode D ₀ is set to 1/2 of the weight. If step 523 and step 525 are not used, then the weight of the extra subcode D ₀ in equation (1) is changed to zero.

The secondary ADC 120 can be implemented by any of the ADCs as long as the analog ADC is completed before the primary ADC 110 completes parsing the most significant bit that is expected to be resolved by the secondary ADC 120. When the auxiliary ADC 120 starts the analog-to-digital conversion, the logic signal DONE is not pulled up; when the secondary ADC 120 performs the analog-to-digital conversion, the logic signal DONE is pulled up.

In an embodiment, the secondary ADC 120 is a flash ADC.

In an embodiment, the secondary ADC 120 can also be a SAR ADC.

In an embodiment, the secondary ADC 120 may include a digital analog conversion circuit 200 as shown in FIG. 2, but with a smaller and lesser capacitance (so that analog digital conversion can be completed faster).

In one embodiment, the secondary ADC 120 performs the sample and hold function slightly faster than the primary ADC 110 to cause the analog to digital conversion to be completed faster.

While the present invention has been described above in the foregoing embodiments, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of patent protection shall be subject to the definition of the scope of the patent application attached to this specification.

100‧‧‧ analog digital converter
110‧‧‧Master digital analog converter
111‧‧‧Sampling and holding circuit
112‧‧‧Digital Analog Converter
113‧‧‧ total circuit
114‧‧‧ comparator
115‧‧‧Starting Loaded SAR Controller
120‧‧‧Secondary ADC
V _IN ‧‧‧ analog input signal
D _OUT ‧‧‧Master Digital Information
D _AUX ‧‧‧Auxiliary data
DONE‧‧‧ logic signal
V ₁ ‧‧‧First voltage
V ₂ ‧‧‧second voltage
V ₃ ‧‧‧ third voltage
V _X ‧‧‧ Common mode voltage
D _X ‧‧‧decision signal
D‧‧‧digit code
200‧‧‧Digital analog conversion circuit
210‧‧‧Sampling switch
220‧‧‧Capacitor array
230‧‧‧DAC Switch Circuit
231~238‧‧‧ DAC switch
C ₁ ~ C ₈ ‧‧‧ capacitor
N ₁ ~N ₈ ‧‧‧ internal circuit nodes
D ₁ ~D ₈ ‧‧‧ subcode
V _R ‧‧‧ positive reference voltage
-V _R ‧‧‧negative reference voltage
N _X ‧‧‧Common Circuit Node
SAMP‧‧‧Sampling signal
Starting at 501‧‧
503‧‧‧Initialization {D ₈ , D ₇ , , D ₁ } is 0
505‧‧‧Sampling V _IN on C ₁ ~C ₈
507‧‧‧Set n to 8
Is 509‧‧‧n 0?
Is 511‧‧‧n greater than 4 and is DONE 1?
513‧‧‧Detecting D _X
515‧‧‧Update D _n based on D _X
517‧‧‧ Waiting for capacitor stability
519‧‧‧n minus 1
521‧‧‧Updated based on D _AUX {D ₈ , D ₇ , , D ₁ }
522‧‧‧Set n to 5
523‧‧‧Detecting D _X
525‧‧‧Update D ₀ based on D _x
527‧‧‧ Calculate D _OUT based on {D ₈ , D ₇ , , D ₁ } or based on {D ₈ , D ₇ , , D ₀ }
n‧‧‧Internal variables
D ₀ ‧‧‧ subcode
D _n ‧‧‧ subcode
320~324, 326~328‧‧‧ time points

[FIG. 1] A schematic diagram of a continuous-approximation-register (SAR) analog-to-digital converter according to an embodiment of the present invention. [Fig. 2] A schematic diagram of an embodiment of a digital analog conversion circuit for realizing the integration function of the sample and hold circuit, the digital analog converter, and the summing circuit in Fig. 1. [Fig. 3] is a schematic diagram showing an example waveform of the digital analog conversion circuit in Fig. 2 in the example of the assistance of the analog analog-to-digital converters (ADC) receiving the auxiliary analog-to-digital converter. [Fig. 4] is a schematic diagram showing an embodiment of a logic table used when the primary ADC of Fig. 1 utilizes the output of the secondary ADC. [Fig. 5] is a flowchart showing the operation of the main ADC of Fig. 1.

100‧‧‧ analog digital converter

110‧‧‧Master digital analog converter

111‧‧‧Sampling and holding circuit

112‧‧‧Digital Analog Converter

113‧‧‧ total circuit

114‧‧‧ comparator

115‧‧‧Starting Loaded SAR Controller

120‧‧‧Secondary ADC

V _IN ‧‧‧ analog input signal

D _OUT ‧‧‧Master Digital Information

D _AUX ‧‧‧Auxiliary data

DONE‧‧‧ logic signal

V ₁ ‧‧‧First voltage

V ₂ ‧‧‧second voltage

V ₃ ‧‧‧ third voltage

D _X ‧‧‧decision signal

D‧‧‧digit code

Claims (11)

An analog-to-digital conversion device includes: a main analog-to-digital converter having a first resolution and a first conversion speed to convert an analog input signal into a main digital data based on a value of a complementary digital data; And a secondary analog-to-digital converter having a second resolution and a second conversion speed to convert the analog input signal into the auxiliary digital data; wherein the second resolution is lower than the first resolution, and The second conversion speed is faster than the first conversion speed; and wherein the main analog digital converter comprises: a boot load controller for executing a first program to update according to a decision signal and the auxiliary bit data a digit code and generating the main digit data based on the final value of the digit code at the end of the first program; a sample and hold circuit for sampling the analog input signal into a first voltage; a digital analog converter for Converting the digit code into a second voltage; a summing circuit for generating a third voltage, wherein the magnitude of the third voltage is equal to the first voltage The difference between the second voltage; and a comparator for generating the decision signal based on the polarity of the third voltage. The analog digital conversion device of claim 1, wherein the comparator compares the third voltage with a ground level to generate the decision signal. The analog-to-digital conversion device of claim 1, wherein the auxiliary analog output further outputs a logic signal, and the boot load controller directly updates the digital code using the auxiliary digital data when the logic signal is pulled up And crossing at least one parsing step of at least one digit of the digit code. The analog digital conversion device of claim 3, wherein the boot load controller directly updates the digital code using the auxiliary bit data based on a value of a logical table. The analog digital conversion device of claim 1, wherein the boot load controller includes a finite state mechanism. The analog digital conversion device of claim 1, wherein the auxiliary analog digital converter is a fast analog analog converter or a continuous progressive register analog digital converter. An analog digital conversion method includes: converting a analog input signal into a main digital data, wherein the main analog digital converter has a first resolution and a first conversion speed; and converting the analog input signal into the auxiliary digital data The secondary analog-to-digital converter has a second resolution and a second conversion speed; and executing a first program, wherein the first program includes a fast tracking step based on the value of the auxiliary digit data; wherein the second The resolution is lower than the first resolution, and the second conversion speed is faster than the first conversion speed; and wherein the performing step of the first program comprises: Updating a digit code according to a decision signal and the auxiliary digit data; generating the main digit data based on the final value of the digit code at the end of the first program; sampling the analog input signal into a first voltage; converting the digit code Forming a second voltage; generating a third voltage, wherein the third voltage represents a difference between the first voltage and the second voltage; and generating the decision signal based on a polarity of the third voltage. The analog digital conversion method of claim 7, wherein the step of generating the decision signal comprises comparing the third voltage with a ground level to generate the decision signal. The analog digital conversion method of claim 7, wherein the updating of the digital code comprises: directly updating the digital code using the auxiliary digital data when the logic signal is pulled up; and crossing at least one digit of the digital code An analytical step. The analog digital conversion method of claim 9, wherein the updating of the digital code comprises directly updating the digital code using the auxiliary bit data based on a value of a logical table. An analog digital conversion method includes: receiving an analog input signal; sampling the analog input signal to generate a first voltage; and using a digital analog converter to generate a second voltage according to a digital code; And continuously updating the digital code according to a polarity of the difference between the first voltage and the second voltage to cause the second voltage to approximate the first voltage; and directly updating the digit according to an output of the auxiliary digital analog converter The code is passed over the successive update steps of the digital code.