TWI530953B - 3d memory and decoding technologies - Google Patents

Description

3D memory and decoding technology

This invention relates to high density memory devices, and more particularly to memory cells configured with multiple planes to provide a three dimensional (3D) array memory device.

As the critical dimensions of integrated circuits shrink to the limits of existing memory cell technology, designers are looking for techniques for stacking multi-plane memory cells to achieve greater memory capacity and lower implementations. Cost per bit (costs per bit). For example, in "512-Mb PROM With a Three-Dimensional Array of Diode/Anti-fuse Memory cells" IEEE J. of Solid-State Circuits, vol. 38, no. 11 Nov. 2003. Cross-points array technology has been used for anti-fuse memory. In the design described by Johnson et al., memory elements at cross-points provide multiple layers of word lines and bit lines. The memory component includes a p+ polysilicon anode connected to the word line, and an n-polysilicon cathode connected to the bit line, and the anode and cathode are separated by an anti-fuse material.

In the flow described by Johnson et al., each memory layer requires several critical lithography steps. Therefore, the number of critical lithography steps required to fabricate the device must be multiplied by the number of layers implemented. However, the critical lithography step is expensive, so the use of critical lithography should be minimized when manufacturing integrated circuits. Therefore, although using a 3D array achieves a higher The benefits of density, but higher manufacturing costs, limit the use of this technology.

A US patent co-pending application describing a three-dimensional anti-fuse memory technology application filed on April 27, 2009, with application number 12/430,290, entitled "INTEGRATED CIRCUIT" 3D MEMORY ARRAY AND MANUFACTURING METHOD", which is hereby incorporated by reference in its entirety herein.

The structure of an ideal three-dimensional integrated circuit memory is to provide a structure with high density and low manufacturing cost, and includes reliable and very small memory components.

The memory device on the integrated circuit described herein includes a three-dimensional (3D) memory array of two-cell unit structures including a programmable and erasable resistor element ( Resistance elements). The 3D array includes a plurality of patterned conductor layers, and the conductor layers are separated from each other by an insulating layer. An array of access devices is included on the integrated circuit, and an array of access devices is configured to provide access to individual columns that extend into the 3D array. The patterned conductive layers include left and right conductors adjacent to the cylinder. This defines the left and right interface regions between the cylinder and the adjacent left and right conductors. Memory elements are provided in the left and right interface areas, and each memory element includes programmable and erasable elements. If necessary, the composition also includes a rectifier or Other switches. In the example described herein, the programmable element includes a transition metal oxide, and the programmable element is characterized by built-in self switching, thereby providing dual functions of the memory element and the switch.

The apparatus described herein includes a row decoder circuit and a column decoder circuit coupled to an array of access devices and configured to select individual pillars in the array of conductive pillars. . Also, left and right planar decoding circuits are coupled to the left and right conductors of the plurality of patterned conductor layers. The decoding circuit is configured to apply a bias voltage, which in turn causes current flow in the selected cell, and to an unselected cell to reverse bias to the rectifier.

In the structure described herein, the pillars of the array can comprise a semiconductor material, and the first conductivity type of semiconductor material is electrically communicated to the respective access device. Also, the left and right conductors include a semiconductor material having a second conductivity type such that the rectifying means in each memory element includes a p-n junction. In other embodiments, the pillars comprise a combination of metal or metal with other conductors or semiconductor materials.

The left and right conductors on each side of the layer have landing areas that are not overlaid with the left and right conductors in the overlapping overlying patterned conductor layers. Wires, such as metal plugs, extend through the vias to a plurality of patterned conductor layers and contact the landing zone. For example, the left and right connection points in the patterned metal layer The connectors are connected to the wires in the vias and are then connected to the decoding circuitry, while the left and right conductive systems are above the plurality of patterned conductor layers.

The invention also describes a method of making a memory device. The formation of a plurality of patterned conductor layers is first formed by forming a plurality of blanket layers of conductive material, and the blanket layer of insulating material forms a stack between the layers of conductive material blanket. The stack is then etched to define the left and right conductors to form trenches in the stack. A layer of memory material is deposited or formed on the sidewalls of the trench, and then the trench is filled with a conductive material such as a doped semiconductor. Second, the conductive material in the trench is patterned to form a pillar. The insulating material is then filled between the pillars.

The programmable memory cell can be edited by programming a resistive memory device in the interface region by applying a bias voltage between the pillar in the desired plane and the selected left and right conductors. Element). The fairing provides isolation between memory cells of different layers within the column, and the fairing is established by p-n junctions or otherwise in the interface region. When the memory component has a threshold characteristic, the switching function can be provided by the memory component itself, while no additional components are needed for the memory cell to provide rectification or switching functionality.

In order to make the above-mentioned contents of the present invention more comprehensible, the preferred embodiments are described below, and the detailed description is as follows:

A detailed description of the embodiments of Figs. 1 to 19 of the present invention is provided below.

Figure 1 is a schematic diagram of a 3D memory structure showing a 110 slice, 112 slice, and 114 slice in the X-Z plane of the 3D structure. In the schematic shown, there are nine two-cell unit structures 120-128, each unit structure has two memory cells, and the memory cells have separate (serial) stylization. Components and left and right terminals. Embodiments of a 3D memory device can include a plurality of twin cell structures on each slice. A left plane decoder 104, a right plane decoding device 105, and a columnar access device array 106 are used. The device includes an array of cells configured for left decoding and right decoding. Conductive columns of two-cell unit structures on the Z-direction column (eg, twin cell structure 120, twin cell structure 123, twin cell structure 126), via conductive pillars (eg, The post 130) is coupled to an access device on a pillar access device array 106, for example, an integrated circuit substrate underneath the structure. Similarly, a pillar for the twin cell structure 121, the twin cell structure 124, and the twin cell structure 127 is coupled to the columnar access device array 106 via the pillar 131, and the corresponding access is performed. Access device. A pillar for the twin cell structure 122, the twin cell structure 125, and the twin cell structure 128 is coupled to the columnar access device array 106 via the pillars 132.

Left-hand word line conductors (eg, electrical conductors) of a twin cell structure in a particular layer (eg, twin cell structure 120, twin cell structure 121, twin cell structure 122) on slice 110, slice 112, and slice 114 141), Department It is coupled to a driver selected by the left side planar decoding device 104. Similarly, the right side of the twin cell structure in the section 110, the facet 112, and the particular level on the facet 114 (eg, the twin cell structure 120, the twin cell structure 121, the twin cell structure 122) A wire conductor (e.g., electrical conductor 142) is coupled to a driver selected by the right side planar decoding device 105. The left word line conductor 143 and the right word line conductor 144 in the double cell structure 123, the twin cell structure 124, and the twin cell structure 125 are respectively coupled to the left side planar decoding device 104 and the right plane. Decoding device 105. The left word line conductor 145 and the right word line conductor 146 in the double cell structure 126, the twin cell structure 127, and the double cell structure 128 are respectively coupled to the left side planar decoding device 104 and the right side plane. Decoding device 105.

The twin cell structure 120-dual cell structure 128 includes a programmable element, such as a transition metal oxide, and each cell, if desired, includes a switch such as a rectifying device as shown in FIG. A memory cell composed of a transition metal oxide material is, for example, a resistive random access memory (ReRAM). Transition metal oxide materials include tung sten oxide, titanium oxide, nickel oxide, aluminum oxide, copper oxide, zirconium oxide, oxidation Niobium oxide, tantalum oxide titanium nitride oxide, chromium doped SrZrO ₃ , chromium doped SrTiO ₃ , Barium calcium manganese oxide (PCMO, PrCaMnO), barium calcium manganese oxide (LaCaMnO), and the like.

Memory cells can also be provided by other two-terminal resistance-change memory devices, such as phase change memory, conduction bridge memory, and Spin Torque Transfer Memory (STT memory), etc.

The pillars and the left and right conductors can be composed of a conductive metal or a metal-like material, including, for example, titanium nitride (TiN), yttrium (Yb), tantalum (Tb), yttrium (Y), and lanthanum (La). ), strontium (Sc), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), niobium (Nb), chromium (Cr), vanadium (V), zinc (Zn) ), tungsten (W), molybdenum (Mo), copper (Cu), ruthenium (Re), ruthenium (Ru), cobalt (Co), nickel (Ni), rhodium (Rh), lead (Pd), platinum (Pt ) and its compounds and alloy materials. Additionally, semiconductors can be used in some embodiments.

The switching element of the memory cell may be composed of a metal-oxide diode, a tunneling diode or other diode structure. Built-in self-switching is used by using the nonlinear IV relationship of the memory as described below. A more detailed twin cell structure is provided below.

As can be seen, when blocking the flow of current in other cells in the array, a voltage can be applied to cause current to flow through the corresponding cylinder (e.g., cylinder 130) and a selected left and right conductivity on the selected plane. Between the body (such as one of the electrical conductor 143 and the electrical conductor 144), it is established to read an individual cell (such as one of the twin cells in the twin cell structure 123). Current path.

In the Z-direction column (eg, the twin cell structure 120, the twin cell structure 123, the twin cell structure 126), the double cell The bottom of the array of conductive pillars of the meta-structure 120-twin cell structure 128 is coupled to the columnar access device array 106 via the corresponding pillar 130, the pillar 131, and the pillar 132. The access device is, for example, an integrated circuit substrate that is implemented under the structure.

The access device in the pillar access device array 106 selectively couples a Z-axis direction column of the twin cell structure 120-dual cell structure 128 to a complex number extending in the Y-axis direction A corresponding one of the bit line 134, the bit line 135, and the bit line 136. The bit lines in the plurality of bit lines 134, the bit lines 135, and the bit lines 136 are coupled to a column decoder 109.

The gate of the transistor in the array of columnar access devices 106 is coupled to select lines 137, select lines 138, and select lines 139 that extend in the X-axis direction. The select line 137, the select line 138, and the select line 139 are coupled to a slice decoder 108.

FIG. 2 is a schematic diagram showing the structure of a 3D memory of layers 266, 267, and 268 in the X-Y plane of the 3D structure. The left side plane decoding device 104 and the right side plane decoding device 105 are shown in the figure. Each level on the schematic includes nine twin cell structures. Each layer in the examples can include many cells. The front row of the unit structure in the 266 layer in the schematic diagram includes a twin cell structure 120, a twin cell structure 121, and a twin cell structure 122, corresponding to the top column of the slice depicted in FIG. 1 ( Top row). Although the array may be larger, for example, it includes 1000 by 1000 (1000 x 1000) twin cells per plane, or more than two twin cells. In the X-Y arrangement of the layer unit structure, two-cell unit structures 220-twin The balance of the meta structure 225 is shown as 3 by 3 (3-by-3). As shown in Fig. 2, a left conductor element 141 is provided to be connected to rows in alternate pairs by using a forked conductor 141-L. The left side conductor between. Similarly, the right conductor element 142 interleaved to the left conductor element 141 is connected to each other using a forked conductor 141-R The right conductor between the rows of the other alternating pairs. As described below, the left and right conductors can be separated from each other on each plane and connected to the overlapping connectors by vias instead of being connected to the plane in a forked manner. .

Figure 3A shows the structure of the twin cell. The symbols 120 representing the unit structure used in FIGS. 1 and 2 may include a left side conductor 141-L, a right side conductor 142-R, and a cylinder 130 as shown. The dielectric insulator 310 is separated from the dielectric insulator 320 by a column. The memory elements 330, 340 include a layer of programmable material centered on opposite sides of the cylinder 130, and respective surfaces on opposite sides of the cylinder 130 and corresponding left conductors 141-L and right conductors Between 142-R. Thus, the structural unit provides two memory cells, including cells 1 (CELL 1) and cells 2 (CELL 2) as indicated, each cell comprising a programmable element and a rectifier.

When the pillar 130 includes an electrical conductor such as a metal, a metal nitride, a doped polysilicon, and other electrical conductors, the electrical conductor 141-L and the electrical conductor 142-R in this example can include a transition metal such as tungsten ( Tungsten). in In some embodiments, a rectifying device for the p-n junction of the memory cell is disposed in the interface region on the opposite side of the memory device using p-type and n-type semiconductors.

The rectifying means can be implemented by a p-n junction between the conductor and the cylinder. For example, a rectifying device based on a solid electrolyte, such as a germanium silicid or other suitable material, can be used to provide a rectifying device. For other representative solid electrolyte materials, see U.S. Patent No. 7,382,647 to Gopalakrishnan.

The memory cell forms an interface region at the intersection of the pillar 130 and the left conductor 141-L or the right conductor 142-R, and the memory cell may include tungsten oxide or a side wall layer of the aforementioned metal oxide. ). In other embodiments, other memory elements may be used including anti-fuse memory cells, while anti-fuse memory cells include ceria, silicon oxynitride or have thickness 5 to 10 nm high resistance ruthenium dioxide. Other antifuse materials that can be used, such as silicon nitride, aluminum oxide, tantalum oxide, magnesium oxide, and the like.

Bias voltages are applied to the cell structure, including the right word line voltage V _WL -R, the left word line voltage V _WL -L , and the column voltage V _B .

FIG. 3B is a side view of two unit cells of two layers in a 3D array, wherein a two-unit cell of the top layer includes a left side conductor 141-L and is connected to the pillar 130. A side wall memory element 340, a memory element 330 on the opposite side of the pillar 130, and a right side conductor 142-R. Two-unit cell pack in the second layer A double cell is included, and the dual cell includes a left side conductor 143-L, a side wall memory element 341 connected to the column 130, a memory element 331 disposed on the opposite side of the column 130, and a right side conductive Body 144-R. In some embodiments, more than two layers can be used, such as 8 layers, 16 layers, and the like. The memory element 340 is located above the memory element 341, and both the memory element 340 and the memory element 341 are disposed on the sidewall of the cylinder 130. Similarly, the memory component 330 is located above the memory component 331, and the memory component 330 and the memory component 331 are disposed on the sidewalls of the pillar 130.

Figure 4 illustrates a partial 3D structure including a memory cell array as described in Figures 1-3. 4 shows a three-layer patterned conductor layer, wherein a top level includes a patterned electrical conductor 410-conductor 412 extending in the X-axis direction, and a next level includes a patterned electrical conductor 413-conductor 415 The next lower level includes a patterned electrical conductor 416 - electrical conductor 418. In this example, the programmable element on the top layer is on the metal oxide structure 425-metal oxide structure 430, and the metal oxide structure 425-metal oxide structure 430 is formed on the patterned conductor 410. On the opposite side of the conductor 412. A programmable element on metal oxide structure 431 - metal oxide structure 432 is formed on the opposite side of patterned conductor 415, and a programmable element on metal oxide structure 433 - metal oxide structure 434 is formed in the pattern The conductor 418 is on the opposite side. Similar programmable elements are likewise formed on the sides of other patterned electrical conductors in the structure. The 3D structure includes an array of conductive pillars, while the array of conductive pillars includes a cylinder 81-cylinder 84 on the back of the illustrated structure, and a cylinder 493, a cylinder 495, and a pillar 497 in front of the illustrated structure. Absolutely The edge cylinder is formed on the opposite side of the cylinder. Therefore, insulating pillars 492, insulating pillars 494, insulating pillars 496, and insulating pillars 498 are shown on the opposite sides of the cylinder 493, the cylinder 495, and the cylinder 497.

Figure 4 illustrates another implementation of an access transistor that requires the pillar to include a doped semiconductor and serve as channel regions for the vertical select transistors. Select lines 137, select lines 138, and select lines 139 are located below the memory cube 102 and extend in the X-axis direction, while select lines 137, select lines 138, select lines 139 are selected transistors ( Select transistors). The pillars extend through select line 137, select line 138, and select line 139 to bit line 134, bit line 135, and bit line 136 that extend in the X-axis direction. In other embodiments, select transistors may be formed on the source/deuterium terminals and channels of the substrate, or other means.

5 is a cross-sectional view of the Y-Z plane of the structure as in FIG. 4, showing the twin cell structure 500, the twin cell structure 502, and the twin cell structure 504 along the column 497. Where appropriate, the numbers in Figure 4 are reused in Figure 5.

The twin cell structure 500 includes a left cell 500-L and a right cell 500-R. The left cell 500-L as a memory element includes an electrical conductor 418 and a metal oxide structure 433. The right cell 500-R as a memory element includes an electrical conductor 417 and a metal oxide structure 435.

The twin cell structure 502 includes a left cell 502-L and a right cell 502-R. The left cell 502-L as a memory element includes an electrical conductor 415 and a metal oxide structure 431. The right cell 502-R as a memory element includes an electrical conductor 414 and Metal oxide structure 437.

The twin cell structure 504 includes a left cell 504-L and a right cell 504-R. The left cell 504-L, which is a memory element, includes an electrical conductor 412 and a metal oxide structure 429. The right cell 504-R as a memory element includes an electrical conductor 411 and a metal oxide structure 439.

Each of the word lines is separated by an insulating material such as silicon nitride or hafnium oxide. Thus, the unit cells of the two Z-axis directions are provided by the twin structural unit 500, the twin structural unit 502, and the twin structural unit 504.

The selection line 137 surrounds the cylinder 497 and extends into and out of the section as shown in FIG. A gate dielectric 520 separates the pillar 497 from the selection line 137.

6 to 12 illustrate the manufacturing process of each stage of the above-described manufacturing 3D structure. Fig. 6 is a view showing an array of contacts for connecting a 3D structure on the surface 600 of the integrated circuit substrate. The contact array includes contacts (e.g., contacts 601 - 604) that are coupled to individual access devices and that can be connected to the posts in the 3D structure. Individual access devices can be formed on the substrate, and can include, for example, MOS transistors, and the MOS transistors have a gate coupled to the word line disposed in the X-axis direction, coupled to the set The source of the source line in the Y-axis direction, and the drain of the coupling to the contact (such as contact 601 - contact 604). The individual access devices are selected by biasing the word lines and source lines in a suitable particular operation. In some embodiments, the access device can include vertical, surrounding gate transistors, and the source/turner terminal of the upper end of the wraparound gate transistor is coupled to the post.

7 is a side cross-sectional view showing the first stage of the manufacturing process, in which an alternating insulating material layer 721, an insulating material layer 723, an insulating material layer 725, an insulating material layer 727, and an electrical conductor are formed on the substrate 720. A side cross-sectional view of a multilayer stack of materials, such as a conductor material layer 722, a conductor material layer 724, a conductor material layer 726, and a conductor material layer 728, wherein the insulating material layer is, for example, cerium oxide or The tantalum nitride layer, such as a metal (such as tungsten, n+ polysilicon or other doped semiconductors, metal nitrides or combinations of metals and other metal nitride conductors). In a representative configuration, the alternating layers of insulating material may be about 50 nanometers thick, and the alternating layers of conductive material may have a thickness of about 50 nanometers. At the top of alternating layers 728, a layer of hard mask material 729 (e.g., tantalum nitride) can be formed.

Figure 8 illustrates a layout view using the results of the first lithography process, the lithography process defines a pattern of trenches, and patterning the stack by etching a multilayer stack of materials as shown in Figure 6 The patterned etch of the stack is formed to form trenches 845 - trenches 848. The lithography process exposes contacts (e.g., contacts 604) that are coupled to individual access devices in the column access circuits. Anisotropic reactive ion etching techniques can be used to etch through a conductive layer and a tantalum oxide or tantalum nitride layer with a high aspect ratio. The trenches have side walls 830 - sidewalls 833, while sidewalls 830 - sidewalls 833 are exposed at the layers of electrical conductor material in the various layers of the structure. In a representative configuration, the width of the trench 845-trench 848 can be, for example, about 70 nanometers.

Figure 9 shows the later stages of the process, in contact with the conductor material. The trenches 845 of the layers - the trenches 848 sidewalls, form a metal oxide memory material 940 - metal oxide memory material layer 943. For example, when the conductor layer includes tungsten or other metal suitable for forming a metal oxide memory material, the metal oxide memory material may be formed by deposition, or by oxidizing a metal for the conductive layer. The process after forming the metal oxide memory material can include depositing a thin protective layer, such as a p-type polysilicon on a metal oxide material, and then using an anisotropic etch process from the bottom of the trench 845-trench 848 The end removes all memory material and finally exposes the contacts (eg, contact 604).

Figure 10 shows the next stage of the process, in which the trenches between the patterned conductors are filled with a material that is a cylinder, such as a p-type polysilicon or metal, and a filled trench 1050-groove. The stage after 1053. In other constructions, the trench can be lined with a doped semiconductor and then filled with metal to improve the electrical conductivity of the structure, thereby providing a rectifying device at the interface region of the structure.

Figure 11 shows the definition of the cylinder pattern using the second lithography process. Patterned etch of the filled trenches using a selective anisotropic etching process for the material of the pillar to define a conductive pillar (cylinder 1150-a, cylinder 1150-b) , cylinder 1150-c, cylinder 1151-a, cylinder 1151-b, cylinder 1151-c, cylinder 1152-a, cylinder 1152-b, cylinder 1152-c, cylinder 1153-a, column The body 1153-b and the cylinder 1153-c), and the vertical openings are formed between the conductive columns. The conductive posts are connected to the contacts, including contacts 604 (not shown, see Figures 8 and 9), and then to the individual access devices below. Next, a dielectric insulating material, such as cerium oxide, is filled between the cylinders to form between the cylinders. An insulator column (such as insulator 1120) is formed.

Figure 12 illustrates a top view of the configuration of the contacts to the left and right conductor lines on a plurality of planes. The left side conductors 1261-1, the conductors 1261-2, the conductors 1261-3 and the conductors 1263-1, the conductors 1263-2, the conductors 1263-3, and the right side conductors 1260- on each layer 1. The conductor 1260-2, the conductor 1260-3, the conductor 1262-1, the conductor 1262-2, the conductor 1262-3 and the conductor 1264-1, the conductor 1262-2, and the conductor 1264-3 have Configured as a stair-step pattern, or a landing zone of other patterns (labeled "L" or "R") such that the landing zone on each layer is not to any left side of the layered patterned conductor layer and The right side conductors are stacked. Contact plugs or other conductive lines (not shown) extend through a plurality of conductor layers and then contact the landing zone. The overlying patterned connection layer includes left side contacts 1228, contacts 1229, contacts 1230 and right side contacts 1225, contacts 1226, contacts 1227 on a plurality of patterned conductor layers, and is in contact with the wires ( Conductive lines), and this wire is in contact with the landing zone of the left and right conductors. The left and right contacts are routed to the left and right plane decoding circuits (not shown).

Figure 13 is a plan view showing a level in another embodiment. The layout shows that the left side conductor 1260-3 and the right side conductor 1264-3 in the top layer of Fig. 4 are coupled to the extension. Extensions 1350 and extensions 1351 (also referred to as spacers) connect the left and right conductors to the left side plane decoding device and the right side plane decoding device. It can be seen that the left side conductor 1261-3 is coupled to the left side conductor 1263-3 to extend The portion 1351 is such that the extension portion can be connected to the contact plug on the landing region 1353 by laminating overlying patterned conductor layers to the connection decoding device circuit. Similarly, the right side conductor 1260-3, the right side conductor 1262-3 and the right side conductor 1264-3 are coupled to the extension 1350 so that the extension can be connected to the contact plugs on the landing area 1352. This is connected to the decoding device circuit.

Figure 14 illustrates an embodiment of an access device array, and the access device array is suitable for use as a pillar access device array as shown in Figure 1. As shown in Fig. 14, the access layer 1104 implemented on the substrate includes an insulating material 1410 having an upper surface, and an array of contacts (e.g., contacts 1412) is exposed on the upper surface of the insulating material. Contact points for individual pillars are provided on the upper surface of the drain contacts 1408, and the upper surface of the drain contacts 1408 is coupled to the MOS transistor in the access layer (MOS transistors) drain terminals 1436. Access layer 1104 includes a semiconductor body having source regions 1442 and a drain region 1436 on access layer 1104. Polycrystalline germanium word line 1434 is disposed over the gate dielectric layer and between source region 1442 and drain region 1436. As shown in the embodiment, source region 1442 is shared by adjacent MOS transistors to form dual transistor structure 1448. The source contact 1440 in the substrate 1438 is between the word lines 1434 and the source contact 1440 is in contact with the source region 1442. The source contacts 1440 can be connected to bit lines (not shown) in the metal layer, and the bit lines are perpendicular to the word lines, and in the columns of drain contacts 1408 between. Silicide caps 1444 covering word lines 1434. Dielectric layer 1445 covers word line 1434 and telluride cover 1444. Isolation trenches 1446 separate the dual transistor structures 1448 from adjacent dual crystal structures. In this case, the transistor acts as an access device. Individual pillars can be coupled to contacts 1412 and individually selected by controlling the bias of source contact 1440 and word line 1412. Of course, other structures can be used to implement an array of access devices, including, for example, a vertical MOS device array.

Figure 15 is a graph of current versus voltage for a transition metal oxide memory device, which may include, for example, tungsten oxide. The IV curve 1500 shows a non-linear characteristic that can be substituted for the individual switching elements of the memory cell. It can be seen that below the threshold voltage V _T , the metal oxide material is essentially blocking current and is in a closed state, but when it is above a threshold voltage V _T , the metal oxide material The current is allowed to flow, so it is on. Therefore, self-switching can be built in accordance with metal oxides and other memory materials having such characteristics.

Figure 16 is a diagram showing an alternative structure of the two unit structures shown in Figure 3B, a metal oxide memory cell technique, as described in U.S. Patent No. 8,279,656, the disclosure of which is incorporated herein by reference. Has been fully elaborated. Figure 16 shows a side view of the dual cells in the two layers of the 3D array (using the same number in Figure 3B where appropriate), wherein the double cells at the top end include the left conductor 141-L, The side memory device 340 is connected to the column 130, the memory element 330 on the opposite side of the column 130, and the right side conductor 142-R. The dual cells in the second layer include a left side conductor 143-L, a side memory element 341 connected to the cylinder 130, a memory element 331 on the opposite side of the cylinder 130, and a right side conductor 144-R. Another option as shown in Fig. 16 is to use the conductor 141-L of the multilayer conductor, the conductor 142-R, the conductor 143-L and the conductor 144-R, and the multilayer conductor includes different oxidizable materials ( A lining of a oxidizable material, such as titanium nitride (TiN), which is slower to oxidize than a bulk material, such as tungsten. When the conductor layer is oxidized to form a memory element, the tungsten core is oxidized to a depth deeper than the bulk of the conductor layer (in this example, the depth is expressed in the horizontal direction), in this manner, When the memory cell is formed, the upper end region 340-u of the sidewall, the upper end region 340-1 and the lower end region 341-u, the lower end region 341-1, the upper end region 330-u, the upper end region 330-1, the lower end region 331-u, and The intersection region of the lower end region 331-1 forms titanium oxynitride (TiNO _x ). In the example of the titanium nitride outer liner, it can be seen that the pillar 130 can also include a titanium nitride (TiN) outer liner 130-a and The tungsten core of the outer liner 130-b.

As noted above, in some embodiments, there can be more than two layers, such as 8 layers, 16 layers, and the like. The memory element 340 is above the memory element 341, and both are disposed on the side wall of the cylinder 130. Similarly, the memory component 330 is above the memory component 331, and both are disposed on the sidewalls of the cylinder 130.

Figures 17 and 18 show another arrangement of decoding circuitry for providing left layer decoding and right layer decoding for left and right conductors in the memory structure described herein (level Decoding). In Fig. 17, a 3D array is schematically represented by a layer 1750-layer 1752, including interleaved left and right conductors, an even number of conductors 141 and an odd number of conductors 142 for layer 1750, for layer 1751 The even number of electrical conductors 143 and the odd number of electrical conductors 144 are an even number of electrical conductors 145 and odd electrical conductors 146 for layer 1752. The decoding circuitry includes a transistor having a gate, a source and a drain, wherein the gate is coupled to the even/odd select line 1710 and the even/odd select line 1711, and the source is coupled to the layer select Line 1720, layer select line 1722 and layer select line 1723, and at contact 1701 - contact 1706, the drain is coupled to pads at different layers.

In Fig. 18, a 3D array is schematically represented by a layer 1850 - layer 1852, including interleaved left and right conductors, an even conductor 141 and an odd conductor 142 for layer 1850 and an even number for layer 1851 The conductor 143, and the odd conductor 144, are an even conductor 145 and an odd conductor 146 for the layer 1852. The decoding circuitry includes a transistor having a source, a gate, and a drain, wherein the source is coupled to the even/odd select line 1810 and the even/odd select line 1811, and the gate is coupled to the layer select line 1820, layer select line 1822 and layer select line 1823, and at junction 1801-contact 1806, the drain is coupled to pads at different layers.

When using a level select and even/odd selection line on a selected pillar to select a particular cell, apply the appropriate bias to read, program, or erase the selected column and odd/even selection. On the line, the decoding method of accessing a specific cell can include opening a slice select line (slice select) coupled to the column in an access circuit Line) and column select line to select a particular pillar.

Figure 19 is a simplified block diagram of an integrated circuit in accordance with an embodiment of the present invention. The integrated circuit 1875 implemented as described herein includes a 3D dual cell structure metal oxide memory array 1860 on a substrate. At the bus 1865, addresses are provided to a column decoder/page buffer circuits 1863, a slice decoder 1861, and a left/right plane decoding device 1858. For an array embodiment similar to that shown in FIG. 1, an access device array for individual pillars is located below the array 1860, and the access device array is coupled to a slice decoder 1861. And column decoder/page buffer circuits 1863. Via the data-in line 1871 from the input/output ports on the integrated circuit 1875, or from other internal or external data sources to the integrated circuit 1875, to the line decoding Column decoder/page buffer circuits 1863 are provided to provide data. In the illustrated embodiment, other circuitry 1874 is included on the integrated circuit, such as a general purpose processor or special purpose application circuitry, or a system integrated chip (system-on-a-chip). The functional combination module, the combination module is supported by the memory cell array. Via data decoder line/page buffer circuits 1863 from the integrated circuit 1875, data output line (data-out line) 1872, or other data to internal or external data. The data destinations are then passed to the integrated circuit 1875 to provide data.

The controller implemented in this example, a bias arrangement state machine 1869, can control the application of bias arrangement supply voltages by generating or providing a voltage in block 1868, for example An application that reads, edits, or erases voltage. The controller can be implemented using dedicated logic circuitry as is known in the art. In an alternate embodiment, the controller includes a general purpose processor that can be implemented on the same integrated circuit, and the integrated circuit executes the computer program to control the operation of the device. In other embodiments, a combination of special-purpose logic circuitry and a general purpose processor can be used for the implementation of the controller.

Especially when the physical limitations of the memory element size have been reached for a particular plane, three-dimensional stacking is an effective way to reduce the cost per bit of the semiconductor memory. Prior to the prior art of 3D arrays, several critical lithography steps were required to fabricate elements of the smallest feature size at each stack layer. In addition, the number of driver transistors for the memory array must also be multiplied by the number of planes.

The techniques disclosed herein include high density 3D arrays and require only a critical lithography step to pattern all layers. In the patterning step, each layer can share a memory via and a layer interconnect. In addition, the layers can share the word line and bit line decoding means to improve the area penalty caused by the multilayer structure of the prior art. A unique two-cell structure for metal oxides and other programmable resistive memories is described here, on both sides of each memory cartridge (two sides of a Memory pillar) also provides a data site. An array of access devices is used to select individual memory cartridges. The left and right word lines are used to select individual cells in the selected plane.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

81, 82, 83, 84, 130, 131, 132, 493, 495, 497, 1150-a, 1150-b, 1150-c, 1151-a, 1151-b, 1151-c, 1152-a, 1152- b, 1152-c, 1153-a, 1153-b, 1153-c‧‧‧ cylinder

102‧‧‧Memory Cube

104‧‧‧Left plane decoding device

105‧‧‧Right plane decoding device

106‧‧‧Room Access Array

108‧‧‧chip decoding device

109‧‧‧ column decoding device

110, 112, 114‧‧ ‧ facets

120, 121, 122, 123, 124, 125, 126, 127, 128, 220, 221, 222, 223, 224, 225, 500, 502, 504 ‧ ‧ twin cell structure

130-a, 130-b‧‧‧ lining

134, 135, 136‧‧ ‧ bit line

137, 138, 139‧‧‧ selection line

141, 141-L, 141-R, 142, 142-R, 143, 143-L, 144, 144-R, 145, 146, 410, 411, 412, 413, 414, 415, 417, 418, 1260- 1, 1260-2, 1260-3, 1261-1, 1261-2, 1261-3, 1262-1, 1262-2, 1262-3, 1263-1, 1263, 2, 1263-3, 1264-1, 1264-2, 1264-3‧‧‧Electrical conductor

266, 267, 268, 1750, 1751, 1752, 1850, 1851, 1852‧ ‧ layers

310, 320‧‧‧ dielectric insulator

330, 331, 340, 341‧‧‧ memory components

330-1, 330-u, 340-1, 340-u‧‧‧ upper area

331-1, 331-u, 341-1, 341-u‧‧‧ lower end area

425, 426, 427, 428, 429, 430, 431, 432, 433, 434, 435, 437, 439‧‧‧ metal oxide structures

492, 494, 496, 498‧‧ ‧ insulation columns

500-L, 502-L, 504-L‧‧‧ left cell

500-R, 502-R, 504-R‧‧ ‧ right cell

520‧‧‧ gate dielectric layer

600‧‧‧ surface of the substrate

601, 602, 603, 604, 1225, 1226, 1227, 1228, 1229, 1230, 1412, 1701, 1702, 1703, 1704, 1705, 1706, 1801, 1802, 1803, 1804, 1805, 1806 ‧ ‧ contacts

720‧‧‧Substrate

721, 723, 725, 727‧‧ ‧ layers of insulating material

722, 724, 726, 728‧‧‧ conductor material layer

729‧‧‧Hard mask material layer

830, 831, 832, 833 ‧ ‧ side walls

845, 846, 847, 848, 1050, 1051, 1052, 1053, 1446‧‧‧ trenches

940, 941, 942, 943‧‧‧ metal oxide memory material layer

1104‧‧‧ access layer

1120‧‧‧Insulator

1350, 1351‧‧‧ extension

1352, 1353‧‧‧ Landing area

1408‧‧‧汲 contact

1410‧‧‧Insulation materials

1412, 1434‧‧‧ character line

1436‧‧‧Bungee area

1438‧‧‧Substrate

1440‧‧‧Source contact

1442‧‧‧ source area

1444‧‧‧ Telluride cover

1445‧‧‧ dielectric layer

1448‧‧‧Double crystal structure

1500‧‧‧IV curve

1710, 1711, 1810, 1811‧‧‧ even/odd selection lines

1720‧‧‧Selection line

1722, 1723, 1820, 1822, 1823‧‧‧ layer selection line

1858‧‧‧Left/Right Plane Decoding Device

1860‧‧‧Array

1861‧‧‧ chip device

1863‧‧‧ line decoding device / page buffer circuit

1865‧‧ ‧ busbar

1868‧‧‧ Block

1871‧‧‧Data input line

1872‧‧‧Data output line for input/output

1874‧‧‧Other circuits

1875‧‧‧ integrated circuit

FIG. 1 is a schematic diagram of an X-Z plane slice view of a 3D memory structure according to an embodiment of the invention.

2 is a schematic diagram of an X-Y plane of a 3D memory structure in accordance with an embodiment of the present invention.

Figure 3A shows the structure of the twin cell in the 3D memory structure as in Figures 1 and 2.

Figure 3B depicts a side view of two layers of memory cells on a cylinder in one embodiment.

4 is a partial perspective view of a 3D memory structure in accordance with an embodiment of the invention.

Fig. 5 is a cross-sectional view showing the Y-Z in the structure of Fig. 4.

6 to 11 are flow charts showing the manufacturing steps of fabricating a 3D memory structure in accordance with an embodiment of the present invention.

FIG. 12 is a view showing a layout of a 3D memory structure in an X-Y plane according to an embodiment of the invention.

Figure 13 is a schematic diagram showing the layout of a forked left/right conductor with shared pad structures.

Figure 14 is a schematic diagram showing an embodiment of a representative array of columnar access devices on a substrate.

Figure 15 is a graph showing the IV of a metal oxide memory device.

Figure 16 is a side elevational view of two layers of memory cells on a cylinder in another embodiment.

Figure 17 is a schematic diagram showing one layer and a left/right decoding device in an example of an implementation.

Figure 18 is a schematic diagram showing one of the layers and the left/right decoding device in another example of the implementation.

Figure 19 is a simplified diagram of an integrated circuit including a 3D, twin cell structured memory array.

102‧‧‧Memory Cube

104‧‧‧Left plane decoding device

105‧‧‧Right plane decoding device

106‧‧‧Room Access Array

108‧‧‧chip decoding device

109‧‧‧ column decoding device

110, 112, 114‧‧ ‧ facets

120, 121, 122, 123, 124, 125, 126, 127, 128‧‧‧ double cell structure

130, 131, 132‧‧‧ columns

134, 135, 136‧‧ ‧ bit line

137, 138, 139‧‧‧ selection line

141, 142, 143, 144, 145, 146‧‧‧ electrical conductors

Claims (23)

A memory device includes: a plurality of bit lines disposed on a first plane; a plurality of selection lines disposed on a second plane, the second plane being parallel to the first plane; an access device An array of a plurality of patterned conductor layers separated from each other by a plurality of insulating layers to form an array of access devices, the patterned conductor layers including a plurality of left side conductors and a plurality of right side conductors; Extending through the patterned conductor layers, the plurality of pillars in the array contacting the corresponding access devices in the access device array, and defining a left interface region and a right interface region, The left and right interface regions are disposed between the pillars and the adjacent left and right conductors, and are on the corresponding patterned conductor layers of the patterned conductor layers, wherein the first plane And the second plane is located on the same side of the array of conductive pillars; and a plurality of memory components are disposed in the left interface region and the right interface regions, each of the memories It includes a programmable memory and an erasable memory material material. The memory device of claim 1, comprising: a plurality of row decoding circuits and a plurality of column decoding circuits coupled to the access device array, the access An array of devices is disposed in the array of conductive pillars and used to select a cylinder; a plurality of left plane decoding circuits and a plurality of right plane decoding circuits coupled to the left side conductors and the right side conductors in the plurality of storage conductor layers to turn on a selected cell current, and The current in an unselected cell is turned off, the selected cell line being in the left interface region and the right interface region of a selected patterned conductor layer. The memory device of claim 1, wherein the pillar of the array of conductive pillars comprises: an electrical conductor electrically connected to a corresponding access device; and a memory material layer Between the conductor and the patterned conductor layer, wherein the programmable element in each of the memory elements includes an active region disposed on the memory material layer in the left and right interface regions . The memory device of claim 1, wherein the access device of the access device array comprises: a transistor having a gate, a first end point and a second end point; And the access device array includes a bit line, a word line, the bit line is coupled to the first end, the word line is coupled to the gate, and wherein the second end The system is coupled to a column corresponding to one of the arrays of conductive pillars. The memory device of claim 1, wherein accessing the device in one of the access device arrays comprises: a vertical transistor having a first source/deuterium extremity coupled to a corresponding conductor post in the array of conductor posts; and the array comprising: a source line or a bit A line, coupled to the source/deuterium extreme of the vertical transistor, and a word line, provides a surrounding gate structure. The memory device of claim 1, wherein the electrode material of the access device in the array of access devices comprises a metal, a metal nitride or a combination of a metal and a metal nitride, And the patterned conductor layers comprise a metal and a transition metal oxide, the transition metal oxide being in the interface regions, and the transition metal oxide has built-in self-switching characteristics. The memory device of claim 1, wherein the left side conductors and the right side conductors in the patterned conductor layers are configured to contact a corresponding left side plane decoding circuit and Right side plane decoding circuit. The memory device of claim 1, wherein the access device array is located below the patterned conductor layers. The memory device of claim 1, wherein: The left side conductors and the right side conductors in each layer have a plurality of landing areas, and the landing areas are not overlaid by any of the left side conductors and the right side conductors. And the right conductive system are located in the layered patterned conductor layers; and, comprising: a plurality of wires extending through the conductor layers and contacting the landing areas; and the left side conductors and the The right side conductor is disposed above the patterned conductor layers and connected to the wires; and the left side plane decoding circuit and the right side plane decoding circuits are coupled to the left side conductors and the right side Electrical conductor. The memory device of claim 1, wherein the memory elements comprise a transition metal oxide, and the transition metal oxide has a built-in self-switching feature. A memory device includes: a plurality of bit lines disposed on a first plane; a plurality of selection lines disposed on a second plane, the second plane being parallel to the first plane; a cylinder selection The device array, the access device in the array is disposed at a plurality of intersections of the corresponding bit lines and the selection lines, and each of the column selection devices has a first end point and a second end a third endpoint, the first endpoint is connected to the bit line at the corresponding intersection, and the second endpoint is connected to a selection line at the corresponding intersection; An array of conductive pillars, the plurality of pillar systems in the array being coupled to the third end of the corresponding access device, the access device being in the array of access devices, wherein the first plane and the second The plane is on the same side of the array of conductive pillars; a 3D array of sidewall memory elements, including a transition metal oxide, and the transition metal oxide has built-in self-switching, the sidewalls in the 3D array The memory components are disposed on the sides of the pillars in the array and include the sidewall memory components, the sidewall memory components are on each of the pillars, the sidewall memory components in the 3D array, The device includes a programmable memory material and an erasable memory material; the complex pair word line structure is orthogonal to the array of conductive pillars, and each pair of word line structures is configured in a corresponding 3D array. And a pair of given word line structures in the layer, including: a first word line structure, including a first group of character lines coupled to a first character of the layer On the line mat, in the first group of the word a line connected to the sidewall memory elements, the sidewall memory elements being located between alternating rows of the pillars in the array of conductive pillars; a second word line structure comprising a second set of characters The line is coupled to a second element line pad of the layer and interleaved to the word line of the first group of word lines, and each of the word lines in the first group of word lines is connected to The sidewall memory components, the sidewall memory components are located between alternating rows of the pillars in the array of conductive pillars. The memory device according to claim 11 of the patent application, comprising: An address decoding circuit is coupled to the bit lines for accessing a column of columns, the address decoding circuit being coupled to the selection lines for accessing a column Slice of conductive pillars, the slice of conductive pillars is orthogonal to the column, and the address decoding circuit is coupled to the word line structures for accessing the 3D array A layer of cells in the middle. The memory device of claim 11, wherein the sidewall memory elements in the 3D array comprise: a plurality of twin cell structures disposed on each of the pillars, at a given column The twin cell structure on the body includes: a memory element along the first side, connected to the word line, the word line is on the first group of word lines of the layer; and along the first A second memory element, on the opposite side, is coupled to the word line, the word line being on the second set of word lines of the layer. The memory device of claim 11, wherein the sidewall memory components comprise: a programmable resistive memory material. The memory device of claim 11, wherein the sidewall memory components comprise a programmable resistor and a metal oxide memory material, the metal oxide memory material being characterized by built-in Self-switching. The memory device of claim 11, wherein the sidewall memory components comprise the programmable resistor and a tungsten monoxide memory material. The memory device of claim 11, further comprising: a controller to edit and erase a plurality of selected memory cells. A method for manufacturing a memory device, comprising: forming a plurality of bit lines, wherein the bit lines are disposed on a first plane; forming a plurality of selection lines, the selection lines are disposed on a second plane, and the a second plane parallel to the first plane; forming an array of access devices; forming a plurality of patterned conductor layers separated from each other by a plurality of insulating layers and the array of access devices, the patterns The conductor layer includes a plurality of left conductors and a right conductor; forming an array of conductive pillars extending through the patterned conductor layers, and the plurality of pillars in the array are in contact with the array of access devices Corresponding access devices, and defining a plurality of interface areas on the left side and the right side, the interface areas are between the pillars and the left side conductors and the right side conductors, and are in the patterns And corresponding to the patterned conductor layer of the conductor layer, wherein the first plane and the second plane are on the same side of the array of conductive pillars; A plurality of memory elements are formed in the left and right interface regions, each of the memory elements including: a transition metal oxide by oxidizing the left and right conductors in each layer. The manufacturing method of claim 18, wherein forming a plurality of patterned conductor layers comprises: forming a plurality of conductive material blanket layers; forming a plurality of insulating material blanket layers on the conductive layers Between the material blanket layers to form a stack; etching the stack includes etching the blanket layers to define the left and right conductors. The manufacturing method of claim 19, wherein the step of etching the stack comprises etching a plurality of trenches through the patterned conductor layers, and forming the conductive pillar array comprises: forming a transition metal oxide Laying on the sidewalls of the plurality of trenches; filling the trenches over the transition metal oxide on the sidewalls of the trenches with an electrode material; and patterning the electrode material in the trenches to form the These columns are listed. The manufacturing method according to claim 20, wherein the electrode material comprises a metal nitride. The manufacturing method as described in claim 18, comprising: Patterning the conductor layers such that the left and right conductors of each layer have a plurality of landing zones that are not stacked by any of the left and right conductors, and are tied to the layers Patterning the conductive layer; forming a plurality of through holes to expose the landing regions, forming a plurality of conductive lines in the through holes, and forming a plurality of connection points on the patterned conductive layers, and The wires are in contact with the wires, and the connection points are connected to the decoding circuit. The manufacturing method of claim 18, wherein the transition metal oxide is in the interface regions and has a built-in self-switch.