CN103811495A - Three-dimensional memory device and manufacturing method thereof - Google Patents

Abstract

The invention discloses a three-dimensional (3D) memory device and a manufacturing method thereof, wherein the three-dimensional memory device is based on a conductive column array and a plurality of patterned conductive layers, and the patterned conductive layers comprise: left and right conductors abut the pillars in the left and right interface regions. The memory elements in the left and right interface regions are comprised of programmable transition metal oxides or programmable resistive materials, the transition metal oxides being characterized by a built-in self-switching behavior. The pillars can be selected using two-dimensional decoding, and the left and right conductors in the plurality of planes can be selected using decoding in a third dimension, which is combined with the left and right selections.

Description

Three-dimensional memory device and manufacturing method thereof

technical field

The present invention relates to high density memory devices, and more particularly to memory cells configured with multiple planes to provide a three-dimensional (3D) array memory device and method of manufacturing the same.

Background technique

As the critical dimensions of integrated circuits shrink to the limits of existing memory cell technologies, designers have been looking for techniques for stacking multiple planes of memory cells to achieve larger storage capacities and achieve more Low cost per bit. For example, in "512-Mb PROM With a Three-Dimensional Array of Diode/Anti-fuse Memory cells" IEEE J.of Solid-State Circuits, vol.38, no.11Nov.2003. published by Johnson et al. Point array (cross-points array) technology has been used in anti-fuse memory (anti-fuse memory). In the design described by Johnson et al., memory elements at cross-points provide multiple layers of word and bit lines. The memory element includes a p+ polysilicon anode connected to a word line, and an n- polysilicon cathode connected to a bit line, and the anode and cathode are separated by an anti-fuse material.

In the flow described by Johnson et al., multiple critical lithography steps are required for each memory layer. Therefore, the number of critical photolithographic steps required to fabricate the device must be multiplied by the number of layers implemented. However, critical lithography steps are expensive, so the use of critical lithography should be minimized when manufacturing integrated circuits. Therefore, although the use of 3D arrays achieves the benefits of higher density, the higher manufacturing cost limits the use of this technology.

A co-pending application for a U.S. patent describing 3D antifuse memory technology, filed April 27, 2009, application number 12/430,290, entitled "INTEGRATED CIRCUIT 3D MEMORY ARRAY ANDMANUFACTURING METHOD", this application is hereby incorporated by reference as if fully set forth.

An ideal 3D integrated circuit memory structure would provide a structure with high density and low manufacturing cost, and include reliable and very small memory elements.

Contents of the invention

The memory devices on integrated circuits described herein include three-dimensional (3D) memory arrays of two-cell unit structures including programmable and erasable resistance elements. The 3D array includes a plurality of patterned conductor layers, and the conductor layers are separated from each other by insulating layers. An array of access devices is included on the integrated circuit configured to provide access to individual pillars extending to the 3D array. The patterned conductive layers include left and right conductive layers adjacent to the pillars. This defines left and right interface regions between the pillar and adjacent left and right electrical conductors. Memory elements are provided in left and right interface areas, and each memory element includes programmable and erasable elements. If necessary, the composition also includes rectifiers or other switches. In the example described here, the programmable element includes a transition metal oxide, and the programmable element is characterized as having built in self switching, thereby providing dual functions of a memory element and a switch.

The devices described herein include row decoder circuits and column decoder circuits coupled to an array of access devices and configured to select individual ones in the array of conductive posts. column. And, the left plane and the right plane decoding circuits are coupled to the left and right conductors in the plurality of patterned conductor layers. Configure the decode circuit to apply a bias, which in turn causes current flow in the selected cell, and to the unselected cell to reverse the bias to the rectified device (rectifier).

In the configurations described herein, the pillars of the array can comprise semiconductor material having a first conductivity type in electrical communication with corresponding access devices. Also, the left and right conductors comprise a semiconductor material having a second conductivity type such that the rectifying means in each memory element includes a p-n junction. In other embodiments, the posts comprise metal or a combination of metal and other conductive or semiconducting materials.

On the left and right conductor landing areas of each layer, the landing areas do not overlap with the left and right conductors in the overlapping patterned conductor layers (overlaid). Wires, such as metal plugs, extend through the vias to the plurality of patterned conductor layers and contact the landing pads. For example, the left and right connectors in the patterned metal layer are connected to the wires in the through hole, and then connected to the decoding circuit, and the left and right conductors are located in multiple above the patterned conductor layer.

This disclosure also describes methods of fabricating memory devices. A plurality of patterned conductor layers are formed, firstly, by forming a plurality of blanket layers of conductive material, and blanket layers of insulating material are stacked between blanket layers of conductive material. Then, the stack is etched to define left and right conductors to form trenches in the stack. A layer of memory material is deposited or formed on the sidewall of the trench, and then the trench is filled with a conductive material, such as a doped semiconductor. Next, pattern the conductive material in the trenches to form the pillars. Then, insulating material is filled between the pillars.

Programmable memory cells can be programmed by applying a bias between the pillars in the desired plane and the selected left and right conductors to program the programmable resistance memory element in the interface region element). The rectifying means provide isolation between memory cells of different layers within the column, and the rectifying means are established in the interface region, by p-n junctions or otherwise. When the memory element has a threshold characteristic, the switching function can be provided by the memory element itself, and no additional elements are required for the memory cell to provide rectification or switching functions.

In order to make the above content of the present invention more obvious and understandable, the following preferred embodiments are specifically cited below, and in conjunction with the accompanying drawings, the detailed description is as follows:

Description of drawings

FIG. 1 is a schematic diagram of an X-Z plane slice view of a 3D memory structure according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of an X-Y plane of a 3D memory structure according to an embodiment of the present invention.

FIG. 3A illustrates a double memory cell structure in the 3D memory structure shown in FIG. 1 and FIG. 2 . FIG. 3B shows a side view of two layers of memory cells on a pillar in one embodiment.

FIG. 4 is a partial perspective view of a 3D memory structure according to an embodiment of the invention.

FIG. 5 shows a Y-Z sectional view of the structure in FIG. 4 .

6 to 11 are flow charts showing the manufacturing steps of manufacturing a 3D memory structure according to an embodiment of the present invention.

FIG. 12 shows an X-Y plane layout view of a 3D memory structure according to an embodiment of the present invention.

FIG. 13 is a schematic diagram of a forked left/right conductor layout with shared pad structures.

14 is a schematic diagram of an embodiment of a representative array of columnar access devices on a substrate.

FIG. 15 is a graph illustrating an IV curve of a metal oxide memory device.

FIG. 16 shows a side view of two layers of memory cells on a pillar in another embodiment.

FIG. 17 is a schematic diagram of a layer and a left/right decoding device in an implementation example.

FIG. 18 is a schematic diagram of a layer and a left/right decoding device in another implementation example.

19 is a simplified diagram of an integrated circuit including a 3D, dual memory cell structure memory array.

[Description of main component symbols]

81, 82, 83, 84, 130, 131, 132, 493, 495, 497, 1150-a, 1150-b, 1150-c, 1151-a, 1151-b, 1151-c, 1152-a, 1152- b, 1152-c, 1153-a, 1153-b, 1153-c: cylinder

102: Storage Cube

104: left plane decoding device

105: Right plane decoding device

106: columnar access device array

108: slice decoding device

109: column decoding device

110, 112, 114: facets

120, 121, 122, 123, 124, 125, 126, 127, 128, 220, 221, 222, 223, 224, 225, 500, 502, 504: double storage unit structure

130-a, 130-b: outer lining

134, 135, 136: bit lines

137, 138, 139: selection line

141, 141-L, 141-R, 142, 142-R, 143, 143-L, 144, 144-R, 145, 146, 410, 411, 412, 413, 414, 415, 417, 418, 1260- 1, 1260-2, 1260-3, 1261-1, 1261-2, 1261-3, 1262-1, 1262-2, 1262-3, 1263-1, 1263-2, 1263-3, 1264-1, 1264-2, 1264-3: Conductor

266, 267, 268, 1750, 1751, 1752, 1850, 1851, 1852: layers

310, 320: Dielectric insulator

330, 331, 340, 341: memory elements

330-l, 330-u, 340-l, 340-u: upper area

331-l, 331-u, 341-l, 341-u: lower area

425, 426, 427, 428, 429, 430, 431, 432, 433, 434, 435, 437, 439: metal oxide structures

492, 494, 496, 498: insulating post

500-L, 502-L, 504-L: left cell

500-R, 502-R, 504-R: right cell

520: gate dielectric layer

600: Surface of the substrate

601, 602, 603, 604, 1225, 1226, 1227, 1228, 1229, 1230, 1412, 1701, 1702, 1703, 1704, 1705, 1706, 1801, 1802, 1803, 1804, 1805, 1806: contact

720: Substrate

721, 723, 725, 727: layer of insulating material

722, 724, 726, 728: conductor material layer

729: Hard mask material layer

830, 831, 832, 833: side walls

845, 846, 847, 848, 1050, 1051, 1052, 1053, 1446: channels

940, 941, 942, 943: layers of metal oxide memory material

1104: access layer

1120: Insulator

1350, 1351: extension

1352, 1353: Landing area

1408: drain contact

1410: insulating material

1412, 1434: word line

1436: Drain region

1438: Substrate

1440: Source contact

1442: source region

1444: Silicide Cover

1445: dielectric layer

1448: Two-transistor structure

1500: IV curve

1710, 1711, 1810, 1811: Even/odd selection line

1720: select line

1722, 1723, 1820, 1822, 1823: layer selection line

1858: Left/Right Plane Decoding Device

1860: array

1861: Chip decoding device

1863: Row decoding device/page buffer circuit

1865: bus

1868: Block

1871: Data input line

1872: Data output line for input/output

1874: Other Circuits

1875: Integrated circuits

Detailed ways

A detailed description of the embodiment of the present invention with reference to FIGS. 1 to 19 is provided below.

FIG. 1 is a schematic diagram of a 3D memory structure, which shows slices 110 , 112 , and 114 on the X-Z plane of the 3D structure. In the schematic diagram shown, there are nine two-cell unit structures 120-128, each unit structure having two memory cells with separate programmable elements and Left endpoint and right endpoint (terminals). Embodiments of the 3D memory device can include many dual memory cell structures per slice. Using the left plane decoder 104, the right plane decoder 105, and the columnar access device array 106, the device includes a memory cell array (array of cells), which is configured for left decoding and right decoding . Conductive pillars of double memory cell structures (two-cell unit structures) on the Z-direction row (column) (such as double memory cell structure 120, double memory cell structure 123, double memory cell structure 126), via conductive pillars (such as Pillars 130) are coupled to access devices on a pillar access device array 106, eg, implemented on an integrated circuit substrate beneath the structure. Similarly, the pillars (pillar) for the double storage unit structure 121, the double storage unit structure 124, and the double storage unit structure 127 are coupled to the columnar access device array 106 via the pillar 131, and the corresponding access device (access device). The pillars for the dual memory cell structure 122 , the dual memory cell structure 125 , and the dual memory cell structure 128 are coupled to the pillar access device array 106 via the pillar 132 .

On the cut plane 110, on the cut plane 112 and the specific layer on the cut plane 114 (such as the double memory cell structure 120, the double memory cell structure 121, and the double memory cell structure 122), the left word line conductors (such as conductors) of the double memory cell structure 141 ), coupled to the driver selected by the left plane decoding device 104 . Similarly, in the section 110, the section 112, and the specific layer (particular level) on the section 114 (such as the double storage unit structure 120, the double storage unit structure 121, and the double storage unit structure 122), the right side word of the double storage unit structure A wire (such as the conductor 142 ) is coupled to a driver selected by the right plane decoding device 105 . The left word line conductor 143 and the right word line conductor 144 in the layer including the double memory cell structure 123, the double memory cell structure 124, and the double memory cell structure 125 are respectively coupled to the left plane decoding device 104 and the Right plane decoding device 105 . The left word line conductor 145 and the right word line conductor 146 in the layer including the double memory cell structure 126, the double memory cell structure 127, and the double memory cell structure 128 are respectively coupled to the left plane decoding device 104 and the Right plane decoding device 105 .

Dual memory cell structure 120 - dual memory cell structure 128 includes a programmable element, such as a transition metal oxide, and if desired, each memory cell includes a switch such as a rectifying device as shown in FIG. 1 . A memory cell made of transition metal oxide material is, for example, a resistive random access memory (ReRAM). Transition metal oxide materials include tungsten oxide, titanium oxide, nickel oxide, aluminum oxide, copper oxide, zirconium oxide, niobium oxide (niobium oxide), tantalum oxide titaniumnitride oxide, chromium doped strontium zirconium oxide (chromium doped SrZrO ₃ ), chromium doped strontium titanium oxide (chromium doped SrTiO ₃ ), praseodymium calcium Manganese oxide (PCMO, PrCaMnO), lanthanum calcium manganese oxide (LaCaMnO), etc.

The memory cell can also be composed of other two-terminal resistance-change memory devices, such as phase change memory, conduction bridge memory, and spin torque transfer memory. (Spin Torque Transfer memory, STT memory) and so on.

The pillars and the left and right conductors can be composed of conductive metals or metal-like materials, including: titanium nitride (TiN), ytterbium (Yb), terbium (Tb), yttrium (Y), lanthanum (La), scandium (Sc), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), neodymium (Nb), chromium (Cr), vanadium (V), zinc (Zn), tungsten (W), molybdenum (Mo), copper (Cu), rhenium (Re), ruthenium (Ru), cobalt (Co), nickel (Ni), rhodium (Rh), lead (Pd), platinum (Pt) and its compounds and alloy materials. Additionally, semiconductors may be used in some embodiments.

The switching elements of the memory cells may be composed of metal-oxide diodes, tunneling diodes, or other diode structures. As described below, built-in self-switching is achieved by using the memory's non-linear IV relationship. A more detailed dual memory cell structure is provided below.

As can be seen, while blocking the flow of current in other memory cells in the array, a voltage can be applied to cause current to flow through the corresponding pillar (such as pillar 130) and a selected left side of the selected plane. Between the right side conductor (such as conductor 143, one of conductor 144), set up (established) in order to read individual memory unit (individual cell) (as in double memory cell structure 123 in double memory cell) One of them) the current path.

In the Z-direction column (Z-direction column) (such as double memory cell structure 120, double memory cell structure 123, double memory cell structure 126), the conductive column array (array) of double memory cell structure 120-double memory cell structure 128 of conductive pillars) are coupled to corresponding access devices on the columnar access device array 106 via corresponding pillars 130, 131, and 132, such as an integrated circuit substrate implemented under the structure.

The access device in the columnar access device array (pillar access device array) 106 selectively couples a column in the Z-axis direction of the double memory cell structure 120-double memory cell structure 128 to a plurality of rows extending in the Y-axis direction Corresponding bit lines among the bit line 134 , the bit line 135 , and the bit line 136 . One of the plurality of bit lines 134 , 135 , 136 is coupled to a column decoder 109 .

The gates of the transistors in the columnar access device array 106 are coupled to select lines 137 , 138 , and 139 extending in the X-axis direction. The selection line 137 , the selection line 138 , and the selection line 139 are coupled to the slice decoder 108 .

FIG. 2 is a schematic diagram of a 3D memory structure showing levels 266 , 267 , and 268 on the X-Y plane of the 3D structure. The left plane decoding device 104 and the right plane decoding device 105 are shown in the figure. Each level on the schematic diagram includes nine double memory cell structures. Each layer in an embodiment may include many cells. On the schematic diagram, the front row (front row) of the unit structure in the 266 layer includes a double storage unit structure 120, a double storage unit structure 121 and a double storage unit structure 122, corresponding to the top row (top row) of the slice (slice) shown in FIG. 1 row). Although the array may be larger, for example including 1000 by 1000 (1000 x 1000) dual memory cells per plane, or more. In the X-Y arrangement of layer unit structures, the balance of two-cell unit structures 220-225 is shown as 3 by 3 (3-by-3). As shown in Figure 2, left conductor element (left conductor element) 141 is arranged to utilize forked conductor (forkedconductor) 141-L, is connected to every other pair of (alternating pairs) row (rows) between left conductor. Likewise, the right conductor element (right conductor element) 142 of the left conductor element (left conductorelement) 141 that is interleaved (interleaved) is to use forked conductor (forked conductor) 141-R, is connected to every other pair Right conductor between rows of (other alternating pairs). As described below, the left and right conductors can be separated from each other on each plane and connected to the overlying connectors through vias instead of being connected in a fork on the plane.

FIG. 3A shows a dual memory cell structure. The symbol 120 used to represent the unit structure in FIG. 1 and FIG. 2 may include a left conductor 141 -L, a right conductor 142 -R, and a column 130 as shown in the figure. The dielectric insulator 310 separates the pillar from the dielectric insulator 320 . The memory elements 330, 340 include layers of programmable material that are located on opposite sides of the pillar 130, and the respective surfaces on the opposite sides of the pillar 130 are electrically conductive to the corresponding left conductor 141-L and the right conductor 141-L. Between body 142-R. Therefore, this structural unit provides two storage units, including storage unit 1 (CELL 1) and storage unit 2 (CELL 2) as shown in the figure, and each storage unit includes a programmable element and a rectifier (rectifier).

When the posts 130 include conductors such as metals, metal nitrides, doped polysilicon, and other conductors, the conductors 141-L and 142-R in this example can include transition metals such as tungsten ( tungsten). In some embodiments, rectifying means for the p-n junction of the memory cell are provided in the interface region using p-type and n-type semiconductors on opposite sides of the memory element.

The rectifying means can be implemented by a p-n junction between the conductor and the pillar. For example, a rectifying device based on a solid electrolyte, such as germanium silicide or other suitable materials, may be used to provide the rectifying device. For other representative solid electrolyte materials (solid electrolyte materials), please refer to US Patent No. 7,382,647 by Gopalakrishnan.

The memory cell is formed at the interface region at the intersection of the pillar 130 and the left conductor 141-L or the right conductor 142-R, and the memory cell may include a sidewall layer of tungsten oxide or the aforementioned metal oxide ( side wall layer). In other embodiments, other memory elements may be used including anti-fuse memory cells comprising silicon dioxide, silicon oxynitride or having a thickness of 5 to 10nm and high resistance silicon dioxide. Other antifuse materials that can be used, such as silicon nitride, aluminum oxide, tantalum oxide, magnesium oxide, etc.

Apply bias voltages (Bias voltages) to the cell structure, including the right word line voltage VWL-R, the left word line voltage VWL-L, and the pillar voltage VB.

FIG. 3B shows a side view of two unit cells in two layers in a 3D array, wherein the top layer (top) double-unit (two-unit) cell includes a left conductor 141-L and is connected to a pillar 130. The memory element 340 on the side wall of the pillar 130, the memory element 330 on the opposite side of the pillar 130, and the right conductor 142-R. The two-unit cell in the second layer includes a two-unit cell, and the two-unit cell includes a left conductor 143-L, a side wall memory element 341 connected to the pillar 130, a memory element 341 located on the The memory element 331 on the opposite side of the pillar 130, and the right conductor 144-R. In some embodiments, there can be more than two layers, eg, 8 layers, 16 layers, etc. The memory element 340 is located above the memory element 341 , and both the memory element 340 and the memory element 341 are disposed on the sidewall of the pillar 130 . Likewise, the memory element 330 is located above the memory element 331 , and both the memory element 330 and the memory element 331 are disposed on the sidewall of the pillar 130 .

FIG. 4 shows a partial 3D structure, which includes the memory cell array as described in FIGS. 1-3 . Figure 4 shows three layers of patterned conductor layers, wherein the top level (top level) includes a patterned conductor 410-conductor 412 extending in the X-axis direction, and the next level (next level) includes a patterned conductor 413-conductor 415, the next lower level includes patterned conductors 416-418. In this example, the programmable elements at the top layer (top) are located on the metal oxide structure 425-metal oxide structure 430, and the metal oxide structure 425-metal oxide structure 430 is formed on the patterned conductor 410- The conductor 412 is on the opposite side. The programmable elements on the metal oxide structure 431-metal oxide structure 432 are formed on the opposite side of the patterned conductor 415, and the programmable elements on the metal oxide structure 433-metal oxide structure 434 are formed on the patterned conductor. body 418 on the opposite side. Similar programmable elements are likewise formed on the sides of other patterned conductors in the structure. The 3D structure includes a conductive pillar array, and the conductive pillar array includes pillars 81 - 84 at the back of the icon structure, and pillars 493 , 495 , and 497 at the front of the icon structure. The insulating pillars are formed between the pillars and on the opposite side thereof. Thus, insulating pillars 492 , 494 , 496 , and 498 are shown on opposite sides of pillars 493 , 495 , and 497 .

FIG. 4 shows another implementation of access transistors that requires pillars to include doped semiconductors and serve as channel regions for vertical select transistors. Select lines (select lines) 137, select lines 138 and select lines 139 are located below the storage cube (memory cube) 102 and extend in the X-axis direction, and select lines 137, select lines 138 and select lines 139 serve as select transistors (select gates of transistors). The pillars extend through select line 137 , select line 138 and select line 139 to bit line 134 , bit line 135 and bit line 136 extending in the X-axis direction. In other embodiments, select transistors may be formed on the source/drain terminals and the channel of the substrate, or otherwise.

FIG. 5 is a cross-sectional view of the Y-Z plane of the structure shown in FIG. 4 , along the dual memory cell structure 500 including the pillar 497 , the dual memory cell structure 502 and the dual memory cell structure 504 . Numbering from FIG. 4 is repeated in FIG. 5 where appropriate.

The dual memory cell structure 500 includes a left cell 500-L and a right cell 500-R. The left cell 500 -L as a memory element includes a conductor 418 and a metal oxide structure 433 . The right cell 500 -R as a memory element includes a conductor 417 and a metal oxide structure 435 .

The dual memory cell structure 502 includes a left cell 502-L and a right cell 502-R. Left cell 502 -L as a memory element includes electrical conductor 415 and metal oxide structure 431 . Right cell 502 -R, which is a memory element, includes electrical conductor 414 and metal oxide structure 437 .

The dual memory cell structure 504 includes a left cell 504-L and a right cell 504-R. Left cell 504 -L, which is a memory element, includes electrical conductor 412 and metal oxide structure 429 . The right cell 504 -R, which is a memory element, includes a conductor 411 and a metal oxide structure 439 .

Each layer in the wordlines is separated by an insulating material such as silicon nitride or silicon dioxide. Therefore, two Z-axis columns of memory cells are provided by the twin structural unit 500 , the twin structural unit 502 and the twin structural unit 504 .

Selection line 137 surrounds cylinder 497 and extends into and out of the cross-section as shown in FIG. 5 . A gate dielectric 520 separates the pillar 497 from the select line 137 .

FIG. 6 to FIG. 12 illustrate the various stages of the manufacturing process for manufacturing the above-mentioned 3D structure. FIG. 6 illustrates an array of contacts for connecting 3D structures on a surface 600 of an integrated circuit substrate. The contact array includes contacts (eg, contacts 601-604) that are coupled to individual access devices and can be connected to posts in the 3D structure. Individual access devices can be formed on the substrate, and may include, for example, metal oxide semiconductor transistors (MOS transistors), and the metal oxide semiconductor transistors have a gate coupled to a word line disposed in the X-axis direction, coupled to a disposed Sources of the source lines in the Y-axis direction, and drains coupled to contacts (such as contacts 601 - 604 ). Individual access devices are selected by biasing the word and source lines for the appropriate particular operation. In some embodiments, the access device can include vertical, surrounding gate transistors with upper source/drain terminals coupled to the pillars.

7 shows a side cross-sectional view in the first stage of the manufacturing process for forming alternating (alternating) insulating material layers 721, insulating material layers 723, insulating material layers 725, insulating material layers 727 and conductor materials on a substrate 720. (conductor material) layer 722, conductor material layer 724, conductor material layer 726, conductor material layer 728 after the side cross-sectional view of the multilayer stack of materials (multilayerstack of materials), wherein the insulating material layer is for example silicon dioxide or nitrogen Silicon oxide, and the conductor material layer is, for example, metal (such as tungsten, n+ polysilicon or other doped semiconductors, metal nitride or a combination of metal and other conductors such as metal nitride). In a representative configuration, the alternating layers of insulating material can be about 50 nanometers thick, and the alternating layers of conductive material can be about 50 nanometers thick. On top of the alternating layers 728, a layer 729 of hard mask material (eg, silicon nitride) can be formed.

FIG. 8 shows a layout view using the result of the first photolithography process, which defines the pattern of trenches, and by etching the multi-layer stack material as shown in FIG. A patterned etch of the stack is formed to form trenches 845-848. The photolithography process exposes contacts (eg, contacts 604 ) that are coupled to individual access devices in the pillar access circuits. Anisotropic reactive ion etching techniques can be used to etch through conductive layers and silicon oxide or silicon nitride layers with high aspect ratios. The trench has sidewalls 830-833 where the layers of conductive material are exposed in the various layers of the structure. In a representative structure, the width of channels 845-848 may be, for example, about 70 nanometers.

Figure 9 shows a later stage in the flow process, for forming a metal oxide memory material layer (metal oxide memory material) 940-metal oxide memory material layer on the sidewall of the channel 845-channel 848 contacting the conductor material layer The stage after 943. For example, when the conductor layer includes tungsten or other metal suitable for forming a metal oxide memory material, the metal oxide memory material can be formed by deposition, or via oxidation of the metal used for the conductive layer. The flow after forming the metal oxide memory material may include depositing a thin protective layer, such as p-type polysilicon on the metal oxide material, and then using an anisotropic etch process from the bottom of the channel 845 to the channel 848 All memory material is removed from the end, and finally the contacts (such as contacts 604) are exposed.

Figure 10 shows the next stage of the process, which is after filling the trenches between the patterned conductors with material as pillars, such as p-type polysilicon or metal, and forming the filled trenches 1050-1053 stage. In other structures, the channel can be lined with a doped semiconductor and then filled with a metal to improve the conductivity of the structure and provide a rectifying device at the interface region of the structure.

FIG. 11 shows a pattern of pillars defined using a second photolithography process. A patterned etch of the filled trenches is performed using an anisotropic etch process selective to the material of the pillars to define the conductive pillars (pillar 1150-a, pillar 1150- b, cylinder 1150-c, cylinder 1151-a, cylinder 1151-b, cylinder 1151-c, cylinder 1152-a, cylinder 1152-b, cylinder 1152-c, cylinder 1153-a, pillars 1153-b and pillars 1153-c), and vertical openings are generated between the conductive pillars. The conductive studs are connected to contacts, including contact 604 (not shown, see FIGS. 8 and 9 ), and then to individual access devices below. Next, a dielectric insulating material, such as silicon dioxide, is filled between the pillars to form insulator rows (eg, insulator 1120 ) between the pillars.

Figure 12 illustrates a top view of an arrangement for making contacts to left and right conductor lines on multiple planes. Left conductors (conductors) 1261-1, conductors 1261-2, conductors 1261-3 and conductors 1263-1, conductors 1263-2, conductors 1263-3 and right conductors on each layer Conductor 1260-1, Conductor 1260-2, Conductor 1260-3, Conductor 1262-1, Conductor 1262-2, Conductor 1262-3 and Conductor 1264-1, Conductor 1264-2, Conductor 1264 -3 have landing areas (marked as "L" or "R") configured in a stair-step pattern, or other pattern, so that the landing areas on each layer are not conductive by the layered pattern Any left and right conductors in the bulk layer are laminated. Contact plugs or other conductive lines (not shown) extend through the various layers of electrical conductors and then contact the landing pads. The stacked (overlying) patterned connection layer includes left contact 1228, contact 1229, contact 1230 and right contact 1225, contact 1226, contact 1227 on a plurality of patterned conductor layers, and is in contact with conductive lines (conductive lines ), and this wire is the landing area that touches the left and right conductors. The left and right contacts are routed to left and right plane decoding circuits (not shown).

FIG. 13 shows a layout diagram of a layer (level) in another embodiment. The layout diagram shows that the left conductor 1260-3 and the right conductor 1264-3 in the top layer of FIG. Extensions 1350 and extensions 1351 (also called pads) are used to connect the left and right conductors to the left plane decoding device and the right plane decoding device. It can be seen that the left conductor 1261-3 and the left conductor 1263-3 are coupled to the extension 1351, so that the extension can be connected to the contact plug on the landing area 1353, through the laminated patterned conductor layer ( overlyingpatterned conductor layers) to the circuit of the decoding device. Similarly, the right conductor 1260-3, the right conductor 1262-3 and the right conductor 1264-3 are coupled to the extension 1350, so that the extension can be connected to contact plugs on the landing area 1352. , thereby connecting to the decoding device circuit.

FIG. 14 illustrates an embodiment of an access device array suitable for use as a pillar access device array shown in FIG. 1 . As shown in FIG. 14, the access layer 1104 implemented on the substrate includes an insulating material 1410 having an upper surface, and an array of contacts (such as contacts 1412) is exposed on the upper surface of the insulating material. Contacts for individual pillars are provided on top surfaces of drain contacts 1408 coupled to MOS transistors in the access layer. Drain terminals 1436 . The access layer 1104 includes a semiconductor body having source regions 1442 and a drain region 1436 on the access layer 1104 . A polysilicon wordline 1434 is disposed on the gate dielectric layer between the source region 1442 and the drain region 1436 . As shown in the embodiment, the source region 1442 is shared by adjacent MOS transistors to form a dual transistor structure 1448 . A source contact 1440 within substrate 1438 is located between word lines 1434 , and source contact 1440 is in contact with source region 1442 . Source contacts 1440 can be connected to bit lines (not shown) on the metal layer that are perpendicular to the word lines and between columns of drain contacts 1408 . Silicide caps 1444 cover the word lines 1434 . A dielectric layer 1445 covers the word lines 1434 and the silicide cap 1444 . Isolation trenches 1446 separate two-transistor structures 1448 from adjacent two-transistor structures. In this example, transistors act as access devices. Individual pillars can be coupled to contacts 1412 and individually selected by controlling the bias voltages of source contacts 1440 and word lines 1412 . Of course, other structures can be used to implement the access device array, including, for example, a vertical MOS device array.

FIG. 15 is an IV curve diagram of current versus voltage of a transition metal oxide memory device, which may include, for example, tungsten oxide. The IV curve 1500 shows non-linear characteristics, which can be used to replace the individual switching elements of the memory cell. It can be seen that below the threshold voltage (threshold voltage) VT, the metal oxide material essentially blocks the current and is in an off state, but when it is above the threshold voltage (threshold voltage) VT, the metal oxide material allows the current Circulation, so it is open. Therefore, self-switching can be built in based on metal oxides and other memory materials with this property.

FIG. 16 shows an alternative structure to the two cell structure shown in FIG. 3B, deploying metal oxide memory cell technology as described in US Pat. No. 8,279,656, which is hereby incorporated by reference as if incorporated herein. fully elaborated. Figure 16 shows a side view of a twin cell in two layers of a 3D array (using the same numbering as in Figure 3B where appropriate), where the top twin cell includes a left conductor 141-L, a connection To the side wall memory element 340 of the pillar 130, the memory element 330 on the opposite side of the pillar 130, and the right conductor 142-R. The dual unit cell at the second level includes left conductor 143-L, sidewall memory element 341 connected to pillar 130, memory element 331 on the opposite side of pillar 130, and right conductor 144-R. Another option as shown in Figure 16 is to use conductor 141-L, conductor 142-R, conductor 143-L, and conductor 144-R of multilayer conductors comprising different oxidizable materials Liner (liner) of (oxidizable material), such as titanium nitride (TiN), the oxidation speed of titanium nitride is slower than bulk material (bulk material), and the bulk material referred to here is tungsten, for example. When the conductor layer is oxidized to form a memory element, the tungsten core is oxidized deeper than the bulk of the conductor layer (the depth referred to in this example is expressed along the horizontal direction), in this way , when forming a memory cell, in the upper end region 340-u, upper end region 340-l and lower end region 341-u, lower end region 341-l, upper end region 330-u, upper end region 330-l, lower end region 331-u of the sidewall The intersection region of u and the lower end region 331-1 forms titanium oxynitride (TiNOx). Tungsten core with outer lining 130-b.

As noted above, in some embodiments, there can be more than two layers, such as 8 layers, 16 layers, etc. The memory element 340 is above the memory element 341 , and both are disposed on the sidewall of the pillar 130 . Likewise, the memory element 330 is above the memory element 331 , and both are disposed on the sidewall of the pillar 130 .

17 and FIG. 18 show another arrangement of the decoding circuit. The decoding circuit is provided for left-layer decoding and right-layer decoding of the left conductor and the right conductor in the memory structure described herein. Code (level decoding). In FIG. 17, the 3D array is schematically represented by layer 1750-layer 1752, including interleaved (interleaved) left conductors and right conductors, for layer 1750, even conductors 141 and odd conductors 142, for layer 1751: The even-numbered conductors 143 and the odd-numbered conductors 144 are the even-numbered conductors 145 and the odd-numbered conductors 146 for the layer 1752 . The decoding circuit includes a transistor having a gate, a source and a drain, wherein the gate is coupled to the even/odd selection line 1710 and the even/odd selection line 1711, and the source is coupled to the layer selection line 1720 , layer selection line 1722 and layer selection line 1723 , and at contact 1701 - contact 1706 , the drain is coupled to pads in different layers.

In FIG. 18, the 3D array is schematically represented by layer 1850-layer 1852, including interleaved (interleaved) left and right conductors, for layer 1850, even conductors 141 and odd conductors 142, for layer 1851, even conductors Body 143 , and odd numbered conductor 144 , for layer 1852 are even numbered conductor 145 and odd numbered conductor 146 . The decoding circuit (decoding circuit) includes a transistor, and the transistor has a source, a gate, and a drain, wherein the source is coupled to the even/odd selection line 1810 and the even/odd selection line 1811, and the gate is coupled to the layer selection line 1820 , layer select line 1822 and layer select line 1823 , and at contact 1801 - contact 1806 , the drain is coupled to pads in different layers.

When using the level select and even/odd select lines on selected pillars to select specific memory cells, apply the appropriate bias to read, program, or erase the selected pillars and odd /even select line, the decode method for accessing a specific cell (specific cell) can include, in the access circuits (access circuits), the slice select line (slice select line) and the row select line coupled to the column are turned on (column select line) to select a particular pillar.

Figure 19 is a simplified block diagram of an integrated circuit in accordance with an embodiment of the present invention. An integrated circuit 1875 implemented as described herein includes a 3D dual memory cell structure metal oxide memory array 1860 on a substrate. In bus 1865, addresses are provided to column decoder/page buffer circuits 1863, slice decoder 1861 and left/right plane decoder 1858. For an embodiment of an array like that shown in FIG. 1 , an array of access devices for individual pillars is located below array 1860, and the array of access devices is coupled to slice decoder 1861 And row decoder/page buffer circuit (column decoder/page buffer circuits) 1863. Via a data-in line (data-in line) 1871 from an input/output port (input/output ports) on the integrated circuit 1875, or from other data sources inside or outside to the integrated circuit 1875, and then to the row decoding device /page buffer circuit (column decoder/page buffer circuits) 1863 to provide data. In the illustrated embodiment, other circuitry 1874 is included on the integrated circuit, such as a general purpose processor or special purpose application circuitry, or to provide system-on-a-chip functionality Combination module, the combination module is supported by the memory cell array. Via the line decoder/page buffer circuit (column decoder/page buffer circuits) 1863 on the integrated circuit 1875, to the data output line (data-out line) 1872 of the input/output terminal, or to other internal or external data The destinations (data destinations) go to the integrated circuit 1875 to provide data.

The controller implemented in this example, bias arrangement state machine (bias arrangement state machine) 1869 can control the application of bias arrangement supply voltages (bias arrangement supply voltages) through the generation or provision of voltage in block 1868, such as application of read, program or erase voltages. The controller can be implemented using dedicated logic circuits known in the art. In alternative embodiments, the controller includes a general purpose processor, which may be implemented on the same integrated circuit that executes the computer program that controls the operation of the device. In other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor may be used for controller implementation.

Three-dimensional stacking is an effective way to reduce the cost per bit of semiconductor memory, especially when the physical limitations of memory element size have been reached for a specific plane. Prior art for 3D arrays required several criticallithography steps to fabricate minimum feature size devices at each stack layer. In addition, the number of driver transistors used in the memory array must be multiplied by the number of planes.

The technology disclosed in the present invention includes high density 3D arrays and requires only one critical lithography step to pattern all layers. In the patterning step, the layers are shareable memory vias and layer interconnects. In addition, each layer can share word line and bit line decoding device, so as to improve the problem of area penalty caused by the multi-layer structure in the prior art. A unique two-2-cell cell structure is described here for metal oxide and other programmable resistive memories that also provide data locations on two sides of a memory pillar (data site). An array of access devices is used to select individual memory cylinders. The left and right word lines are used to select individual memory cells in a selected plane.

To sum up, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (23)

1. a storage arrangement, comprising:

One access device array;

Multiple pattern conductive body layers, by multiple insulating barriers separately, to form this access device array, the plurality of pattern conductive body layer comprises multiple left sides electric conductor and multiple right sides electric conductor each other;

One conductive pole array, extend through the plurality of pattern conductive body layer, multiple cylinders in array, to contact the plurality of access device corresponding in this access device array, and define left side interface zone and right side interface zone, the plurality of left side and right side interface zone are arranged between the plurality of cylinder and adjacent left side electric conductor and right side electric conductor, and are on pattern conductive body layer corresponding in the plurality of pattern conductive body layer; And

Multiple memory components, are arranged in the plurality of left side interface zone and the plurality of right side interface zone, and every the plurality of memory component comprises a programmable storage material and an erasable memory material.

2. storage arrangement according to claim 1, comprising:

Multiple array decoding circuits (row decoding circuits) and multiple column decode circuitry (columndecoding circuits), be couple to this access device array, this access device array is arranged in this conductive pole array, and in order to select a cylinder; And

Multiple left plane decoding circuits and multiple right plane decoding circuit, be couple to the plurality of left side electric conductor and the plurality of right side electric conductor deposited in conductor layer the plurality of, to open the electric current of a selected memory cell (selected cell), and being closed in an electric current for selected memory cell (unselected cell) not, this selected memory cell is this Yu Gai right side, boundary zone, left side interface zone that is arranged in a selected pattern conductive body layer.

3. storage arrangement according to claim 1, wherein comprises at a cylinder of this conductive pole array:

One electric conductor is the access device that is electrically connected at a correspondence; And

One storage material layer, is between this electric conductor and the plurality of pattern conductive body layer, wherein comprises an active area at this programmable element of each this memory component, is arranged on this storage material layer in the plurality of left side and right side interface zone.

4. storage arrangement according to claim 1, wherein, at an access device of this access device array, comprising:

One transistor, has a grid, one first end points and one second end points; And

This access device array comprises a bit line, a word line, and this bit line is coupled to this first end points, and this word line is coupled to this grid, and wherein this second end points is coupled to the cylinder in a correspondence of this conductive pole array.

5. storage arrangement according to claim 1, wherein, at an access device of this access device array, comprising:

One vertical transistor, has one first source/drain end points, and this end points is coupled in this conductor pin array a corresponding conductor pin; And

This array, comprising:

One source pole line or a bit line, be coupled to this source/drain end points of this vertical transistor, and

One word line, provides a circulating type grid structure (surrounding gate structure).

6. storage arrangement according to claim 1, wherein at this electrode material of this access device of this access device array, comprise the composition of a metal, a metal nitride or a metal and metal nitride, and the plurality of pattern conductive body layer, comprise a metal and a transition metal oxide, this transition metal oxide is in the plurality of boundary zone, and this transition metal oxide has the characteristic of built-in self-switch.

7. storage arrangement according to claim 1, the wherein the plurality of left side electric conductor in the plurality of pattern conductive body layer and the plurality of right side electric conductor, is to be configured to touch corresponding a left side plane decoding circuit and right side plane decoding circuit.

8. storage arrangement according to claim 1, wherein this access device array is positioned at below the plurality of pattern conductive body layer.

9. storage arrangement according to claim 1, wherein:

The plurality of left side electric conductor in every one deck and the plurality of right side electric conductor, there are multiple touch-down zones, the plurality of touch-down zone is not by any the plurality of left side electric conductor and right side electric conductor institute stacking (overlaid), and the plurality of left side electric conductor and right side electric conductor are to be arranged in stacking the plurality of pattern conductive body layer; And, comprising:

Many wires, extend through the plurality of conductor layer and are contacted with the plurality of touch-down zone; And

The plurality of left side electric conductor and the plurality of right side electric conductor, be arranged on the top of the plurality of pattern conductive body layer, and be connected to the plurality of wire; And

The plurality of left side plane decoding circuit and the plurality of right side plane decoding circuit, be coupled to the plurality of left side electric conductor and the plurality of right side electric conductor.

10. storage arrangement according to claim 1, wherein the plurality of memory component comprises and crosses metal oxide, and this transition metal oxide has the feature of built-in self-switch.

11. 1 kinds of storage arrangements, comprising:

Multiple bit lines, is arranged in one first plane;

Select line, be arranged in one second plane, and this second plane parallel is in this first plane for many;

One cylinder choice device array, access device in array is the multiple crosspoints that are configured in corresponding the plurality of bit line and the plurality of selection line, often this cylinder choice device, there is one first end points, one second end points and one the 3rd end points, this first end points is this bit line being connected in this corresponding crosspoint, and this second end points is to be connected in one of this corresponding crosspoint to select line;

One conductive pole array, the multiple cylinders in array are the 3rd end points that are connected in corresponding access device, this access device is in access device array;

The 3D array of one sidewall memory component (sidewall memory elements), comprise transition metal oxide, and this transition metal oxide has built-in self-switch, the plurality of sidewall memory component in 3D array is to be configured in the side of the plurality of cylinder in array and to comprise the plurality of sidewall memory component, the plurality of sidewall memory component is on each cylinder, this sidewall memory component in 3D array, comprises a programmable storage material and an erasable memory material; And

Multipair word line structure, is to be orthogonal to this conductive pole array, and this every pair word line structure is that to be configured in 3D array corresponding layer upper, and the word line structure of a pair of given (given) in one deck, comprising:

One first word line structure, comprise that one first group of word line is coupled on the one first word line pad of this layer, at this every word line of first group, be to be connected in the plurality of sidewall memory component, the plurality of sidewall memory element is to be located between the alternate row of the plurality of cylinder in this conductive pole array;

One second word line structure, comprise that one second group of word line is coupled on one second yuan of line pad of this layer, and crisscross this word line of this first group of word line, every word line in this first group of word line, be connected to the plurality of sidewall memory component, the plurality of sidewall memory component is to be located between the alternate row of the plurality of cylinder in this conductive pole array.

12. storage arrangements according to claim 11, comprising:

One bit address decoding circuit (address decoding circuitry), be coupled to the plurality of bit line, for access one cylinder row, this address decoding circuitry, be coupled to the plurality of selection line, for access one cylinder sheet (slice of conductive pillars), this cylinder sheet (slice of conductive pillars) is orthogonal to this row, and this address decoding circuitry is coupled to the plurality of word line structure, for being accessed in one deck memory cell of this 3D array.

13. storage arrangements according to claim 11, the wherein the plurality of sidewall memory component in this 3D array, comprising:

Multiple double memory cell structures, are arranged on this cylinder, and this double memory cell structure on a given cylinder, comprising:

Along a memory component of the first side, be connected to this word line, this word line is on this first group of word line of this layer; And

The one second memory element of tossing about along a second-phase, is connected to this word line, and this word line is on this second group of word line of this layer.

14. storage arrangements according to claim 11, wherein the plurality of this sidewall memory component, comprising: a programmable resistance memory material.

15. storage arrangements according to claim 11, wherein the plurality of sidewall memory component, comprises a programmable resistance and a metal-oxide memory material, this metal-oxide memory material is characterized by has built-in self-switch.

16. storage arrangements according to claim 11, wherein the plurality of sidewall memory component, comprises this programmable resistance and a tungsten oxide storage material.

17. storage arrangements according to claim 11, further comprise:

One controller (controller), to edit and to wipe multiple selected memory cells.

The manufacture method of 18. 1 kinds of storage arrangements, comprising:

Form an access device array;

Forming multiple pattern conductive body layers (patterned conductorlayers), is to be separated from each other, and by multiple insulating barriers and this access device array, the plurality of pattern conductive body layer comprises multiple left sides electric conductor and right side electric conductor;

Form a conductive pole array, extend through the plurality of pattern conductive body layer, multiple cylinders in array, to contact the plurality of access device corresponding in this access device array, and define the interface zone on multiple left sides and right side, the plurality of interface zone is between the plurality of cylinder and the plurality of left side electric conductor and the plurality of right side electric conductor, and is on the corresponding pattern conductive body layer of the plurality of pattern conductive body layer; And

Forming multiple memory components, is the interface zone on the plurality of left side and right side, and each the plurality of memory component comprises: a transition metal oxide is the plurality of left side and the right side electric conductor in every one deck by oxidation.

19. manufacture methods according to claim 18, wherein form multiple desiring to make money or profit conductor layers, comprising:

Form multiple electric conducting materials (conductive material) blanket coating;

Form multiple insulating material blanket coating between the plurality of electric conducting material blanket coating, to form a lamination;

This lamination of etching, comprises that the plurality of blanket coating of etching is to define the plurality of left side and right side electric conductor.

20. manufacture methods according to claim 19, the wherein step of this lamination of etching, comprises by the multiple raceway grooves of the plurality of pattern conductive body layer etching, and the step that forms this conductive pole array comprises:

Forming a transition metal oxide, is in multiple trench sidewalls;

On this transition metal oxide with the plurality of raceway groove of an electrode material filling in the plurality of trench sidewalls; And

Patterned electrodes material in the plurality of raceway groove, to form those cylinder row.

21. manufacture methods according to claim 20, wherein this electrode material, comprises a metal nitride.

22. manufacture methods according to claim 18, comprising:

The plurality of conductor layer of patterning, makes to have multiple touch-down zones at the plurality of left side and the right side electric conductor of every one deck, and the plurality of touch-down zone is not stacked by any the plurality of left side and right side electric conductor institute, is to be arranged in stacked the plurality of pattern conductive body layer;

Form multiple perforations to expose the plurality of touch-down zone,

Form many wires (conductive lines) in the plurality of perforation, and

Form multiple tie points on the plurality of pattern conductive body layer, and contact with the plurality of wire in the plurality of perforation, the plurality of tie point is connected to decoding circuit.

23. manufacture methods according to claim 18, wherein this transition metal oxide is in the plurality of boundary zone, and has built-in self-switch.

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