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TWI484610B - 半導體結構之製法與導電凸塊 - Google Patents

半導體結構之製法與導電凸塊 Download PDF

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Publication number
TWI484610B
TWI484610B TW101124582A TW101124582A TWI484610B TW I484610 B TWI484610 B TW I484610B TW 101124582 A TW101124582 A TW 101124582A TW 101124582 A TW101124582 A TW 101124582A TW I484610 B TWI484610 B TW I484610B
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Taiwan
Prior art keywords
metal layer
melting point
fabricating
semiconductor structure
structure according
Prior art date
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TW101124582A
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English (en)
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TW201403773A (zh
Inventor
詹前峰
詹慕萱
林畯棠
賴顗喆
Original Assignee
矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW101124582A priority Critical patent/TWI484610B/zh
Priority to US13/677,904 priority patent/US8952537B2/en
Publication of TW201403773A publication Critical patent/TW201403773A/zh
Priority to US14/616,078 priority patent/US9349705B2/en
Application granted granted Critical
Publication of TWI484610B publication Critical patent/TWI484610B/zh

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    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/18, H10D48/04 and H10D48/07, with or without impurities, e.g. doping materials
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Description

半導體結構之製法與導電凸塊
本發明係關於半導體結構，特別是關於一種堆疊式半導體結構之製法與導電凸塊。
於一般覆晶封裝(Flip Chip Package)製程中，如第1A圖所示，於一半導體晶片11之銲墊110上形成銲錫材料(圖略)，且於一封裝基板12之電性接觸墊120上形成預銲錫(圖略)，以藉由銲錫材料與預銲錫相接而對位接合該半導體晶片11與封裝基板12，再回銲該銲錫材料與預銲錫以形成銲錫凸塊10。之後，使用底膠13形成於該半導體晶片11之下表面與封裝基板12之上表面之間，以包覆該些銲錫凸塊10，俾完成覆晶式半導體封裝件1之製程。利用凸塊作為電性連接之元件，其具有縮短電性傳導路徑、提昇效能、提供散熱路徑及縮小封裝件體積等優點，因而成為封裝之趨勢。
然而，該銲錫材料經回銲後，該銲錫凸塊10之體積及高度之平均值與公差控制不易，且該銲錫凸塊10之坍塌範圍要精準控制；當該銲錫凸塊10之坍塌範圍較廣時，相鄰之銲錫凸塊10容易相接觸，導致發生接點橋接(bridge)現象，而形成短路。又該銲錫凸塊10之體積及高度之平均值與公差過大時，該銲錫凸塊10所排列成之柵狀陣列(grid array)容易產生共面性(coplanarity)不良，而導致產品失效，進而造成信賴性問題。因此，該半導體晶片11 難以達到凸塊細間距(fine pitch bump joint)的要求。
有鑑於此，遂發展出一種覆晶凸塊技術，如第1B圖所示，係先於半導體晶片11’之銲墊110上依序形成凸塊底下金屬層101與銅柱(Cu pillar)100，再於該銅柱100上形成銲錫材料102，以利用銅材不會於回銲製程中改變形狀之特性，而控制凸塊的高度與體積，使該半導體晶片11’較易於達到細間距的要求。
再者，隨著電子產品輕薄短小的發展趨勢，晶片上各I/O間的距離將越來越接近，且在一定面積上整合更多晶片與功能遂成為封裝技術之趨勢，因而發展出三維(3D)晶片堆疊技術。
目前一般具有銅柱100之凸塊製程係利用熱壓接合(Thermal compression bonding,TCB)方式，將銅柱100上之銲錫材料102與預銲錫(圖略)進行回銲以形成銲接凸塊10’，故需要極高的壓合力及溫度進行熱壓接合製程。
再者，當製程能力提升，電子元件(如半導體晶片11’)大幅縮小，電子元件受到電阻、電容所引起的傳導延遲更加顯著(即阻容延遲)，隨著阻容延遲(RC delay)增加，線路間產生串音(cross talk)與電容耦合的作用嚴重影響訊息傳送速度與品質。因此，藉由使用低介電係數材質，可避免阻容延遲之影響。
惟，於半導體製程中，需使用低介電係數材質，而其材料特性係為硬且脆，故使用現行熱壓接合方式及凸塊材質，將因壓合力過大及溫度過高，而造成低介電係數材質 (即半導體晶片11’)碎裂(crack)S。
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種導電凸塊，係用於形成於具有銲墊之半導體基板上，該導電凸塊包括：第一金屬層，係形成於該銲墊上；第二金屬層，係形成於該第一金屬層上；以及第三金屬層，係形成於該第二金屬層上，且該第二金屬層之熔點高於該第三金屬層之熔點。
前述之導電凸塊中，該第一金屬層之熔點係大於該第二金屬層之熔點與第三金屬層之熔點。
本發明復提供一種半導體結構之製法，係包括：提供一具有複數第一銲墊與導電凸塊之半導體基板，該導電凸塊係具有第一金屬層、第二金屬層與第三金屬層，該第一金屬層係形成於該第一銲墊上，而該第二金屬層係形成於該第一金屬層上，且該第三金屬層係形成於該第二金屬層上，又該第二金屬層之熔點高於該第三金屬層之熔點；提供一接置件，加熱至第一溫度區間，以熔化該第三金屬層，使該第三金屬層結合於該接置件上；以及加熱至第二溫度區間，以熔化該第二金屬層，使該第二金屬層與第三金屬層形成合金部，以令該第一金屬層及合金部構成導電體，俾供接合該接置件與半導體基板。
前述之製法中，該半導體基板係為低介電係數 (low-k)材質。
前述之製法中，該接置件係為低介電係數(low-k)材質。
前述之製法中，該接置件係為半導體基板或封裝基板。
前述之製法中，該接置件上具有銲錫材料，以結合該第三金屬層，且該銲錫材料與第三金屬層係為相同材質。
前述之製法中，該合金部之熔點為197至213℃。
前述之製法中，復包括形成導電柱於該第二銲墊與該銲錫材料之間，以當熔化該第二金屬層後，該導電柱連結該合金部。
前述之製法中，復包括形成膠體於該接置件與半導體基板之間，以包覆該些導電體。例如，係於熔化該第二金屬層之後，形成該膠體。或者，先形成該膠體於該接置件上，再將該半導體基板壓合於該膠體上，使該些導電凸塊嵌入該膠體中。亦可，先形成該膠體於該半導體基板上，以包覆該些導電凸塊，再將該接置件壓合於該膠體上。
前述之製法與導電凸塊中，該第二金屬層係無鉛材質，如錫銀或錫銀銅，且該第二金屬層之熔點為200至250℃。
前述之製法與導電凸塊中，該第三金屬層係無鉛材質，如鉍、銦，且該第三金屬層之熔點為70至160℃。
另外，前述之製法與導電凸塊中，復包括形成阻障層於該第一金屬層與該第二金屬層之間，使該導電體復具有 形成於該第一金屬層與該合金部之間的該阻障層。
由上可知，本發明之半導體結構之製法與導電凸塊，係藉由該導電凸塊具有三種不同熔點的金屬材質，以當加熱至第一溫度區間時，僅對該第三金屬材與銲錫材料熔化接合，再經加熱至第二溫度區間使該第二金屬層與第三金屬材及銲錫材料融成一體之合金部，以令該第一金屬層及合金部構成導電體，故相較於習知技術，本發明不僅能避免該低介電係數材質之半導體基板碎裂，且能增強導電體之可靠度。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2D圖係為本發明半導體結構2之製法之第一實施例之剖面示意圖。
如第2A圖所示，提供一半導體基板21、複數導電凸塊3與一接置件22。
所述之半導體基板21具有複數第一銲墊210及第一絕緣保護層211，且該第一絕緣保護層211外露該些第一銲墊210以供承載該導電凸塊3。
所述之接置件22具有複數第二銲墊220及第二絕緣保護層221，且該第二絕緣保護層221外露該些第二銲墊220以供形成銲錫材料222。
於本實施例中，該半導體基板21與接置件22係為低介電係數(low-k)材質之晶片。
再者，於其它實施例中，該接置件22亦可為封裝基板，以進行覆晶製程。
本發明所提供之導電凸塊3係具有一第一金屬層30、第二金屬層31與第三金屬層32。於本實施例中，係於該些第一銲墊210上形成凸塊底下金屬層(UBM)300，再形成該導電凸塊3於該凸塊底下金屬層300上，又該凸塊底下金屬層300之材質係為鈦/銅。
所述之第一金屬層30係為銅材，且藉由電鍍方式形成於該第一銲墊210上。
所述之第二金屬層31係形成於該第一金屬層30上，且該第二金屬層31係含有如錫銀或錫銀銅之無鉛材質。
所述之第三金屬層32係形成於該第二金屬層31上， 且該第三金屬層32係含有如鉍、銦、錫之無鉛材質，又該第二金屬層31之熔點高於該第三金屬層32之熔點，且該第一金屬層30之熔點係大於該第二金屬層31之熔點與第三金屬層32之熔點。
於本實施例中，該第二金屬層31之熔點為200至250℃，例如，Sn-Ag熔點為217℃，而該第三金屬層32之熔點為70至160℃，例如，Sn-Bi熔點為138℃。
再者，該第三金屬層32與銲錫材料222之特性相似，例如，兩者均屬低熔點溫度，故兩者可為相同材質，即該銲錫材料222之材質可為Sn-Bi合金。
又，於該第一金屬層30與該第二金屬層31之間可具有阻障層33。於本實施例中，該阻障層33之材質係為鎳材。
另外，如第2A’圖所示，可形成一導電柱223與阻障層224於該第二銲墊220與該銲錫材料222之間。於本實施例中，該導電柱223與該第一金屬層30之材質相同，即該導電柱223之材質為銅材。
如第2B圖所示，進行熱壓接合(Thermal compression bonding,TCB)製程，即加熱至第一溫度區間，以將該銲錫材料222與該第三金屬層32相結合，令該半導體基板21與接置件22相疊置。
於本實施例中，當熱壓接合製程之溫度超過138℃(即Sn-Bi熔點)時，該銲錫材料222與該第三金屬層32(例如，Sn-Bi、Sn-In或Sn-In-Bi)將自然結合。
再者，當進行熱壓接合製程時，僅以低溫與較低壓力對低熔點材質(即該第三金屬層32與銲錫材料222)進行接合，以避免低介電係數材質(如半導體基板21)碎裂(crack)。
如第2C圖所示，進行回銲(reflow)製程，即加熱至第二溫度區間，以熔化該第二金屬層31，使該第二金屬層31、第三金屬層32與銲錫材料222形成合金部34，而令該第一金屬層30、阻障層33及合金部34構成導電體20，俾供接合該半導體基板21與接置件22。
於本實施例中，當回銲製程之溫度超過217℃(即Sn-Ag熔點)時，該第二金屬層31與上述新合金(銲錫材料222與該第三金屬層32)將結合成該合金部34(例如，Sn-Bi-Ag或Sn-In-Ag-Bi)。
再者，當進行回銲製程時，係以高溫使高熔點材質熔化，而使高熔點材質與低熔點材質融合成一合金材，即介面合金共化物(Intermetallic Compound,IMC)，經回銲製程之介面合金共化物為高溫熔點材質，因而能提高該導電體20與晶片間之結合力，例如本實施例之合金部34之熔點為197至213℃。
又，該合金部34之熔點與該第二金屬層31之熔點(如Sn-Ag之熔點)相近，以利於通過信賴性之測試。
另外，若接續第2A’圖之製程，當熔化該第二金屬層31後，該導電柱223(或阻障層224)將連結該合金部34。
如第2D圖所示，形成膠體23(如填充底膠)於該半 導體基板21與接置件22之間，以包覆該些導電體20。
本發明主要藉由導電凸塊3具有兩種不同熔點之銲錫材料(即第二金屬層31與第三金屬層32)，當進行熱壓接合製程時，僅對低溫熔點材質(即第三金屬層32與銲錫材料222)先進行欲接合(pre-bonding)，因而不需太強之壓合力及高溫，故能避免該低介電係數材質之半導體基板21碎裂。
再者，藉由進行高溫之回銲製程，使高溫熔點材質(即第二金屬層31)熔化而能與低溫熔點材質融合成合金材，故能增加該導電體20之可靠度。
第3A至3C圖係為本發明半導體結構之製法之第二實施例之剖面示意圖。本實施例與第一實施例之差異僅在於膠體23之成形步驟，其它製程大致相同，故不再贅述相同處。
如第3A圖所示，形成膠體23於該接置件22上，以包覆該些銲錫材料222。
如第3B圖所示，將該半導體基板21壓合於該膠體23上，使該些導電凸塊3嵌入該膠體23中，而令該第三金屬層32置於該銲錫材料222上，再進行熱壓接合製程，以結合該第三金屬層32與銲錫材料222。
如第3C圖所示，進行回銲製程，以形成導電體20，俾供接合該半導體基板21與接置件22。
第4A至4C圖係為本發明半導體結構之製法之第三實施例之剖面示意圖。本實施例與第二實施例之差異僅在於 膠體23之成形步驟，其它製程大致相同，故不再贅述相同處。
如第4A圖所示，形成膠體23於該半導體基板21上，以包覆該些導電凸塊3。
如第4B圖所示，將該接置件22壓合於該膠體23上，使該些銲錫材料222嵌入該膠體23中，而令該第三金屬層32置於該銲錫材料222上，再進行熱壓接合製程，以結合該第三金屬層32與銲錫材料222。
如第4C圖所示，進行回銲製程，以形成導電體20，俾供接合該半導體基板21與接置件22。
綜上所述，本發明之半導體封裝件及其製法與導電凸塊，主要藉由該第一金屬層上具有第二金屬層與第三金屬層，以於結合製程時，可先以低溫壓合第三金屬層與銲錫材料，再以高溫回銲第二金屬層以形成高溫熔點之合金部，不僅能避免半導體基板碎裂，且能使導電體之可靠度提升。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1‧‧‧半導體封裝件
10‧‧‧銲錫凸塊
10’‧‧‧銲接凸塊
100‧‧‧銅柱
101‧‧‧凸塊底下金屬層
102‧‧‧銲錫材料
11,11’‧‧‧半導體晶片
110‧‧‧銲墊
12‧‧‧封裝基板
120‧‧‧電性接觸墊
13‧‧‧底膠
2‧‧‧半導體結構
20‧‧‧導電體
21‧‧‧半導體基板
210‧‧‧第一銲墊
211‧‧‧第一絕緣保護層
22‧‧‧接置件
220‧‧‧第二銲墊
221‧‧‧第二絕緣保護層
222‧‧‧銲錫材料
223‧‧‧導電柱
224,33‧‧‧阻障層
23‧‧‧膠體
3‧‧‧導電凸塊
30‧‧‧第一金屬層
300‧‧‧凸塊底下金屬層
31‧‧‧第二金屬層
32‧‧‧第三金屬層
34‧‧‧合金部
S‧‧‧碎裂
第1A圖係為習知覆晶式半導體封裝件的剖視示意圖；第1B圖係為習知覆晶式晶片的局部剖視示意圖； 第2A至2D圖係為本發明半導體封裝件之製法之第一實施例之剖面示意圖；第2A’圖係為第2A圖之另一實施例；第3A至3C圖係為本發明半導體封裝件之製法之第二實施例之剖面示意圖；以及第4A至4C圖係為本發明半導體封裝件之製法之第三實施例之剖面示意圖。
21‧‧‧半導體基板
210‧‧‧第一銲墊
211‧‧‧第一絕緣保護層
22‧‧‧接置件
220‧‧‧第二銲墊
221‧‧‧第二絕緣保護層
222‧‧‧銲錫材料
3‧‧‧導電凸塊
30‧‧‧第一金屬層
300‧‧‧凸塊底下金屬層
31‧‧‧第二金屬層
32‧‧‧第三金屬層
33‧‧‧阻障層

Claims (23)

  1. 一種導電凸塊，係用於形成於具有銲墊之半導體基板上，該導電凸塊包括：第一金屬層，係形成於該銲墊上；第二金屬層，係形成於該第一金屬層上，其中，該第二金屬層係無鉛材質之銲錫；以及第三金屬層，係形成於該第二金屬層上，且該第二金屬層之熔點高於該第三金屬層之熔點，其中，該第三金屬層係銲錫。
  2. 如申請專利範圍第1項所述之導電凸塊，其中，該第一金屬層之熔點係大於該第二金屬層之熔點與第三金屬層之熔點。
  3. 如申請專利範圍第1項所述之導電凸塊，其中，該第二金屬層之熔點為200至250℃。
  4. 如申請專利範圍第1項所述之導電凸塊，其中，該無鉛材質包含錫銀或錫銀銅。
  5. 如申請專利範圍第1項所述之導電凸塊，其中，該第三金屬層之熔點為70至160℃。
  6. 如申請專利範圍第1項所述之導電凸塊，其中，該第三金屬層係無鉛材質。
  7. 如申請專利範圍第6項所述之導電凸塊，其中，該無鉛材質更包含鉍或銦。
  8. 如申請專利範圍第1項所述之導電凸塊，復包括阻障層，係形成於該第一金屬層與該第二金屬層之間。
  9. 一種半導體結構之製法，係包括：提供一具有複數第一銲墊與導電凸塊之半導體基板，該導電凸塊係具有第一金屬層、第二金屬層與第三金屬層，該第一金屬層係形成於該第一銲墊上，而該第二金屬層係形成於該第一金屬層上，且該第三金屬層係形成於該第二金屬層上，又該第二金屬層之熔點高於該第三金屬層之熔點；將該半導體基板以其導電凸塊置放於一接置件上，再加熱該第三金屬層至第一溫度區間，以熔化該第三金屬層，使該第三金屬層結合於該接置件上；以及加熱該第二金屬層至第二溫度區間，以熔化該第二金屬層，使該第二金屬層與第三金屬層形成合金部，以令該第一金屬層及合金部構成導電體，俾供接合該接置件與半導體基板。
  10. 如申請專利範圍第9項所述之半導體結構之製法，其中，該半導體基板係為低介電係數(low-k)材質。
  11. 如申請專利範圍第9項所述之半導體結構之製法，其中，該第二金屬層之熔點為200至250℃。
  12. 如申請專利範圍第9項所述之半導體結構之製法，其中，該第三金屬層之熔點為70至160℃。
  13. 如申請專利範圍第9項所述之半導體結構之製法，其中，該合金部之熔點為197至213℃。
  14. 如申請專利範圍第9項所述之半導體結構之製法，其中，該接置件係為低介電係數(low-k)材質。
  15. 如申請專利範圍第9項所述之半導體結構之製法，其中，該接置件係為半導體基板或封裝基板。
  16. 如申請專利範圍第9項所述之半導體結構之製法，其中，該接置件上具有銲錫材料，以結合該第三金屬層。
  17. 如申請專利範圍第16項所述之半導體結構之製法，其中，該銲錫材料與第三金屬層係為相同材質。
  18. 如申請專利範圍第16項所述之半導體結構之製法，復包括形成導電柱於該接置件與該銲錫材料之間，以當熔化該第二金屬層後，該導電柱連結該合金部。
  19. 如申請專利範圍第9項所述之半導體結構之製法，復包括形成阻障層於該第一金屬層與該第二金屬層之間，使該導電體復具有形成於該第一金屬層與該合金部之間的該阻障層。
  20. 如申請專利範圍第9項所述之半導體結構之製法，復包括形成膠體於該接置件與半導體基板之間，以包覆該些導電體。
  21. 如申請專利範圍第20項所述之半導體結構之製法，其中，係於熔化該第二金屬層之後，形成該膠體。
  22. 如申請專利範圍第20項所述之半導體結構之製法，其中，係先形成該膠體於該接置件上，再將該半導體基板壓合於該膠體上，使該些導電凸塊嵌入該膠體中。
  23. 如申請專利範圍第20項所述之半導體結構之製法，其中，係先形成該膠體於該半導體基板上，以包覆該些導電凸塊，再將該接置件壓合於該膠體上。
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3022697B1 (fr) * 2014-06-24 2017-12-22 Commissariat Energie Atomique Dispositif de connexion electrique a elements de connexion comportant des membranes deformables
TWI557856B (zh) * 2014-07-04 2016-11-11 立錡科技股份有限公司 積體電路元件及其封裝結構
TWI546932B (zh) * 2014-07-17 2016-08-21 矽品精密工業股份有限公司 半導體封裝件及其製法
KR102430984B1 (ko) 2015-09-22 2022-08-09 삼성전자주식회사 반도체 장치 및 이의 제조 방법
KR102534735B1 (ko) * 2016-09-29 2023-05-19 삼성전자 주식회사 필름형 반도체 패키지 및 그 제조 방법
JP2021162728A (ja) * 2020-03-31 2021-10-11 デクセリアルズ株式会社 光学体、光学体の製造方法及び光学デバイス
US20240312941A1 (en) * 2023-03-13 2024-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Electronic apparatus and method for forming conductive bumps

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5803340A (en) * 1995-09-29 1998-09-08 Delco Electronics Corporation Composite solder paste for flip chip bumping
TW200509345A (en) * 2003-08-21 2005-03-01 Siliconware Precision Industries Co Ltd Process of forming lead-free bumps on electronic component
US20110254146A1 (en) * 2010-04-14 2011-10-20 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Electrical Interconnection Between Semiconductor Die and Substrate with Continuous Body of Solder Tape
US20110260316A1 (en) * 2010-04-21 2011-10-27 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Bump on Substrate to Prevent ELK ILD Delamination During Reflow Process
US20120146181A1 (en) * 2010-12-10 2012-06-14 Stats Chippac, Ltd. Semiconductor Device and Method of Forming an Inductor Within Interconnect Layer Vertically Separated from Semiconductor Die

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020151164A1 (en) * 2001-04-12 2002-10-17 Jiang Hunt Hang Structure and method for depositing solder bumps on a wafer
US6622907B2 (en) * 2002-02-19 2003-09-23 International Business Machines Corporation Sacrificial seed layer process for forming C4 solder bumps
US6596621B1 (en) * 2002-05-17 2003-07-22 International Business Machines Corporation Method of forming a lead-free tin-silver-copper based solder alloy on an electronic substrate
US7547623B2 (en) * 2002-06-25 2009-06-16 Unitive International Limited Methods of forming lead free solder bumps
TWI305403B (en) * 2004-06-15 2009-01-11 Advanced Semiconductor Eng Lead-free conductive jointing bump
JP3905100B2 (ja) * 2004-08-13 2007-04-18 株式会社東芝 半導体装置とその製造方法
WO2006057360A1 (ja) * 2004-11-25 2006-06-01 Nec Corporation 半導体装置及びその製造方法、配線基板及びその製造方法、半導体パッケージ並びに電子機器
US7314819B2 (en) * 2005-06-30 2008-01-01 Intel Corporation Ball-limiting metallurgies, solder bump compositions used therewith, packages assembled thereby, and methods of assembling same
US7404154B1 (en) * 2005-07-25 2008-07-22 Lsi Corporation Basic cell architecture for structured application-specific integrated circuits
JP4998073B2 (ja) * 2007-05-07 2012-08-15 ソニー株式会社 半導体チップおよびその製造方法
US8269345B2 (en) * 2007-10-11 2012-09-18 Maxim Integrated Products, Inc. Bump I/O contact for semiconductor device
US8349721B2 (en) * 2008-03-19 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming insulating layer on conductive traces for electrical isolation in fine pitch bonding
TW201019440A (en) * 2008-11-03 2010-05-16 Int Semiconductor Tech Ltd Bumped chip and semiconductor flip-chip device applied from the same
US7741148B1 (en) * 2008-12-10 2010-06-22 Stats Chippac, Ltd. Semiconductor device and method of forming an interconnect structure for 3-D devices using encapsulant for structural support
US8003512B2 (en) * 2009-02-03 2011-08-23 International Business Machines Corporation Structure of UBM and solder bumps and methods of fabrication
JPWO2010119934A1 (ja) * 2009-04-14 2012-10-22 パナソニック株式会社 発光装置、光特性調整方法及び発光装置の製造方法
US8067308B2 (en) * 2009-06-08 2011-11-29 Stats Chippac, Ltd. Semiconductor device and method of forming an interconnect structure with TSV using encapsulant for structural support
JP4901933B2 (ja) * 2009-09-29 2012-03-21 株式会社東芝 半導体装置の製造方法
JP2011077308A (ja) * 2009-09-30 2011-04-14 Fujitsu Ltd 半導体装置の実装方法
US20110186989A1 (en) * 2010-02-04 2011-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Bump Formation Process
US8610270B2 (en) * 2010-02-09 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and semiconductor assembly with lead-free solder
US8492891B2 (en) * 2010-04-22 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with electrolytic metal sidewall protection
US8441124B2 (en) * 2010-04-29 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US8232193B2 (en) * 2010-07-08 2012-07-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming Cu pillar capped by barrier layer
US9048135B2 (en) * 2010-07-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Copper pillar bump with cobalt-containing sidewall protection
US8598030B2 (en) * 2010-08-12 2013-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Process for making conductive post with footing profile
US8581420B2 (en) * 2010-10-18 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Under-bump metallization (UBM) structure and method of forming the same
US8242011B2 (en) * 2011-01-11 2012-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming metal pillar
JP5023226B1 (ja) * 2011-03-31 2012-09-12 株式会社東芝 電子機器、電子機器の制御方法及び制御プログラム
US8568271B2 (en) * 2011-04-19 2013-10-29 Caterpillar Inc. System and method to prevent shift hunting in a powertrain
US9905524B2 (en) * 2011-07-29 2018-02-27 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structures in semiconductor device and packaging assembly
US8847388B2 (en) * 2011-10-06 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Bump with protection structure
US9536818B2 (en) * 2011-10-13 2017-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same
US9245834B2 (en) * 2012-03-16 2016-01-26 Stats Chippac, Ltd. Semiconductor device and method of forming compliant conductive interconnect structure in flipchip package
US8970034B2 (en) * 2012-05-09 2015-03-03 Micron Technology, Inc. Semiconductor assemblies and structures

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5803340A (en) * 1995-09-29 1998-09-08 Delco Electronics Corporation Composite solder paste for flip chip bumping
TW200509345A (en) * 2003-08-21 2005-03-01 Siliconware Precision Industries Co Ltd Process of forming lead-free bumps on electronic component
US20110254146A1 (en) * 2010-04-14 2011-10-20 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Electrical Interconnection Between Semiconductor Die and Substrate with Continuous Body of Solder Tape
US20110260316A1 (en) * 2010-04-21 2011-10-27 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Bump on Substrate to Prevent ELK ILD Delamination During Reflow Process
US20120146181A1 (en) * 2010-12-10 2012-06-14 Stats Chippac, Ltd. Semiconductor Device and Method of Forming an Inductor Within Interconnect Layer Vertically Separated from Semiconductor Die

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US20140008787A1 (en) 2014-01-09

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