[go: up one dir, main page]

TWI480986B - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

Info

Publication number
TWI480986B
TWI480986B TW101131510A TW101131510A TWI480986B TW I480986 B TWI480986 B TW I480986B TW 101131510 A TW101131510 A TW 101131510A TW 101131510 A TW101131510 A TW 101131510A TW I480986 B TWI480986 B TW I480986B
Authority
TW
Taiwan
Prior art keywords
semiconductor wafer
substrate body
thermally conductive
conductive metal
metal layer
Prior art date
Application number
TW101131510A
Other languages
English (en)
Other versions
TW201409628A (zh
Inventor
唐紹祖
蔡瀛洲
Original Assignee
矽品精密工業股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW101131510A priority Critical patent/TWI480986B/zh
Publication of TW201409628A publication Critical patent/TW201409628A/zh
Application granted granted Critical
Publication of TWI480986B publication Critical patent/TWI480986B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73227—Wire and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

半導體封裝件及其製法
本發明係有關於一種半導體封裝件及其製法，尤指一種具有導熱金屬層之半導體封裝件及其製法。
隨著時代的進步，現今電子產品均朝向微型化、多功能、高電性及高速運作的方向發展，為了配合此一發展趨勢，半導體業者莫不積極研發體積微小、高性能、高功能、與高速度化的半導體封裝件，藉以符合電子產品之要求。
一般半導體封裝件需要接置散熱件，以保持半導體晶片之正常作動，如第1至3圖所示，係各種習知之具有散熱件之半導體封裝件之剖視圖。
第1圖所示者係將一散熱片11設置於封裝基板10上，之後再進行包覆封裝膠體12，並使該散熱片11之頂面外露。
第2圖所示者係於半導體晶片21接置於封裝基板20後，先形成封裝膠體22，再於該封裝膠體22上貼設有一散熱片23。
第3圖所示者係於半導體晶片31接置於封裝基板30後，堆疊置放一大一小的矽材質之虛設晶粒(dummy die)32於該半導體晶片31上，由於矽(Si)亦為不錯之導熱材料，故以此取代一般之金屬散熱片。
惟，前述習知之散熱方式仍有如下之缺點：
1.散熱件離半導體晶片太遠，故散熱效果不佳。(如 第1或2圖所示)
2.將散熱件貼附於半導體晶片或封裝膠體上，增加半導體封裝件之整體厚度。(如第1、2或3圖所示)
3.散熱件或虛設晶粒須逐一對位並貼附於半導體晶片或封裝膠體上，其產出率(throughput)低，故產品之生產速度慢。(如第1或3圖所示)
因此，如何避免上述習知技術中之種種問題，並解決半導體封裝件之散熱效果不佳、厚度過大以及生產速度較慢等缺失，實已成為目前亟欲解決的課題。
有鑒於上述習知技術之缺失，本發明提供一種半導體封裝件，係包括：基板本體，係具有相對之第一表面與第二表面，該基板本體中設有導熱金屬路徑，且該第二表面具有連接該導熱金屬路徑的散熱墊；半導體晶片，係接置於該基板本體之第一表面上，且藉由打線方式電性連接該基板本體；圖案化之導熱金屬層，係形成於該基板本體之第一表面及半導體晶片之頂面與側面上，且連接該導熱金屬路徑；以及封裝膠體，係形成於該基板本體之第一表面上，以包覆該半導體晶片。
本發明提供另一種半導體封裝件，係包括：導線架；半導體晶片，係接置於該導線架之一表面上，且藉由打線方式電性連接該導線架；圖案化之導熱金屬層，係形成於該導線架之該表面及半導體晶片之頂面與側面上；以及封裝膠體，係形成於該導線架之該表面上，以包覆該半導體 晶片。
本發明復提供一種半導體封裝件之製法，係包括：於一基板本體之第一表面上接置半導體晶片，該基板本體具有相對該第一表面之第二表面；於該基板本體之第一表面及半導體晶片之頂面與側面上形成圖案化之導熱金屬層，該導熱金屬層係藉由該基板本體中之導熱金屬路徑連接該第二表面之散熱墊；以打線方式電性連接該半導體晶片與該基板本體；以及於該基板本體之第一表面上形成包覆該半導體晶片的封裝膠體。
本發明復提供另一種半導體封裝件之製法，係包括：於一導線架之一表面上接置半導體晶片；於該導線架之該表面及半導體晶片之頂面與側面上形成圖案化之導熱金屬層；以打線方式電性連接該半導體晶片與該導線架；以及於該導線架之該表面上形成包覆該半導體晶片的封裝膠體。
由上可知，因為本發明係將導熱金屬層直接形成在半導體晶片上，故可有效地將熱迅速地傳導至外界；此外，該導熱金屬層之厚度遠較習知之散熱件還薄，所以可大幅縮減整體厚度；又，本發明之導熱金屬層能一次在未切單之大版面的複數半導體封裝件上同時形成，因此整體產出率遠較習知技術來得高。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解 本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「頂」、「側」、「圖案化」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第一實施例
第4A至4G圖所示者，係本發明之半導體封裝件及其製法之第一實施例的示意圖，其中，第4A至4F圖係俯視圖，第4G圖係剖視圖。
如第4A圖所示，提供一具有相對之第一表面40a與第二表面40b之基板本體40，該基板本體40之第一表面40a可選擇性地形成導熱孔或導熱槽400，或者，該基板本體40之第一表面40a可選擇性地形成有導熱墊(未圖示)，該基板本體40中設有連接該導熱槽400的導熱金屬路徑401(圖示於第4G圖)，該導熱金屬路徑401係可包括散熱金屬線路、散熱金屬孔或散熱金屬柱，該第二表面40b係具有連接該導熱金屬路徑401的散熱墊402(圖示於第4G 圖)。
如第4B圖所示，於該基板本體40之第一表面40a上接置半導體晶片41。
如第4C圖所示，於該基板本體40之第一表面40a與該半導體晶片41上形成具有阻層開口420的阻層42，該阻層42可為感光性乾膜，且該阻層42係覆蓋該半導體晶片41之電極墊(未圖示)及其周緣，並覆蓋該基板本體40之銲墊(未圖示)及其周緣。
如第4D圖所示，進行金屬濺鍍或電鍍步驟。
如第4E圖所示，移除該阻層42，以於該基板本體40之第一表面40a及半導體晶片41之頂面與側面上定義出圖案化之導熱金屬層43，該導熱金屬層43係藉由該基板本體40中之導熱金屬路徑401連接該第二表面40b之散熱墊402。
要補充說明的是，由於前述第4C至4E圖之方式雖對位精度較高，但所花費的成本也較高，故在該導熱金屬層43之對位精度之需求較低的情況下，為了降低整體成本，亦可改用下述之方式：先於該基板本體40之第一表面40a與該半導體晶片41之上方設置模板(未圖示)，且該模板具有對應該導熱金屬層43的模板開口(未圖示)，並進行濺鍍步驟，再移除該模板，且該模板可再重複使用。由於本替代方式係本發明所屬技術領域具有通常知識者依據本說明書而能瞭解者，故不在此加以圖示與說明。
如第4F圖所示，以打線方式電性連接該半導體晶片 41之電極墊與該基板本體40之銲墊。
如第4G圖所示，於該基板本體40之第一表面40a上形成包覆該半導體晶片41的封裝膠體44，並於該散熱墊402上接置例如銲球的散熱元件45，且可藉由該散熱元件45將熱傳導至另一電路板(未圖示)上。
第二實施例
第5A至5D圖所示者，係本發明之半導體封裝件及其製法之第二實施例的示意圖，本實施例之作法係大致相同於前一實施例，故在此僅進行簡單的說明。
如第5A圖所示，於一導線架50之一表面上接置半導體晶片51。
如第5B圖所示，於該導線架50之該表面與該半導體晶片51上形成具有阻層開口520的阻層52，該阻層52可為感光性乾膜，且該阻層52係覆蓋該半導體晶片51之電極墊(未圖示)及其周緣，並覆蓋該導線架50之銲墊(未圖示)及其周緣。
如第5C圖所示，進行金屬濺鍍或電鍍步驟。
如第5D圖所示，移除該阻層52，以於該導線架50之該表面及半導體晶片51之頂面與側面上定義出圖案化之導熱金屬層53，並以打線方式電性連接該半導體晶片51與該導線架50，並於該導線架50之該表面上形成包覆該半導體晶片51的封裝膠體(未圖示)，最後，可視需要進行切割步驟。
本發明復提供一種半導體封裝件，係包括：基板本體 40，係具有相對之第一表面40a與第二表面40b，該基板本體40中設有導熱金屬路徑401，該第二表面40b係具有連接該導熱金屬路徑401的散熱墊402；半導體晶片41，係接置於該基板本體40之第一表面40a上，且藉由打線方式電性連接該基板本體40；圖案化之導熱金屬層43，係形成於該基板本體40之第一表面40a及半導體晶片41之頂面與側面上，且連接該導熱金屬路徑401；以及封裝膠體44，係形成於該基板本體40之第一表面40a上，以包覆該半導體晶片41。
於本發明之半導體封裝件中，復包括導熱孔或導熱槽400，係形成於該基板本體40之第一表面40a，且該導熱金屬層43復形成於該導熱孔或導熱槽400中。
本發明復提供另一種半導體封裝件，係包括：導線架50；半導體晶片51，係接置於該導線架50之一表面上，且藉由打線方式電性連接該導線架50；圖案化之導熱金屬層53，係形成於該導線架50之該表面及半導體晶片51之頂面與側面上；以及封裝膠體，係形成於該導線架50之該表面上，以包覆該半導體晶片51。
綜上所述，相較於習知技術，由於本發明係將導熱金屬層直接形成在半導體晶片上，故可有效地將熱迅速地傳導至外界；此外，該導熱金屬層之厚度遠較習知之散熱件還薄，所以可大幅縮減整體厚度；又，本發明之導熱金屬層能一次在未切單之大版面的複數半導體封裝件上同時形成，因此整體產出率遠較習知技術來得高。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
10、20、30‧‧‧封裝基板
11、23‧‧‧散熱片
12、22、44‧‧‧封裝膠體
21、31、41、51‧‧‧半導體晶片
32‧‧‧虛設晶粒
40‧‧‧基板本體
40a‧‧‧第一表面
40b‧‧‧第二表面
400‧‧‧導熱槽
401‧‧‧導熱金屬路徑
402‧‧‧散熱墊
42、52‧‧‧阻層
420、520‧‧‧阻層開口
43、53‧‧‧導熱金屬層
45‧‧‧散熱元件
50‧‧‧導線架
第1至3圖所示者係各種習知之具有散熱件之半導體封裝件之剖視圖；第4A至4G圖所示者，係本發明之半導體封裝件及其製法之第一實施例的示意圖，其中，第4A至4F圖係俯視圖，第4G圖係剖視圖；以及第5A至5D圖所示者，係本發明之半導體封裝件及其製法之第二實施例的示意圖。
40‧‧‧基板本體
40a‧‧‧第一表面
40b‧‧‧第二表面
400‧‧‧導熱槽
401‧‧‧導熱金屬路徑
402‧‧‧散熱墊
41‧‧‧半導體晶片
43‧‧‧導熱金屬層
44‧‧‧封裝膠體
45‧‧‧散熱元件

Claims (12)

  1. 一種半導體封裝件，係包括：基板本體，係具有相對之第一表面與第二表面，該基板本體中設有導熱金屬路徑，且該第二表面具有連接該導熱金屬路徑的散熱墊；半導體晶片，係接置於該基板本體之第一表面上，且藉由打線方式電性連接該基板本體；圖案化之導熱金屬層，係形成於該基板本體之第一表面及半導體晶片之頂面與側面上，且連接該導熱金屬路徑；以及封裝膠體，係形成於該基板本體之第一表面上，以包覆該半導體晶片。
  2. 如申請專利範圍第1項所述之半導體封裝件，復包括導熱孔或導熱槽，係形成於該基板本體之第一表面，且該導熱金屬層復形成於該導熱孔或導熱槽中。
  3. 一種半導體封裝件，係包括：導線架；半導體晶片，係接置於該導線架之一表面上，且藉由打線方式電性連接該導線架；圖案化之導熱金屬層，係形成於該導線架之該表面及半導體晶片之頂面與側面上；以及封裝膠體，係形成於該導線架之該表面上，以包覆該半導體晶片。
  4. 一種半導體封裝件之製法，係包括： 於一基板本體之第一表面上接置半導體晶片，該基板本體具有相對該第一表面之第二表面；於該基板本體之第一表面及半導體晶片之頂面與側面上形成圖案化之導熱金屬層，該導熱金屬層係藉由該基板本體中之導熱金屬路徑連接該第二表面之散熱墊；以打線方式電性連接該半導體晶片與該基板本體；以及於該基板本體之第一表面上形成包覆該半導體晶片的封裝膠體。
  5. 如申請專利範圍第4項所述之半導體封裝件之製法，其中，形成該導熱金屬層之步驟係包括：於該基板本體之第一表面與該半導體晶片之上方設置模板，且該模板具有對應該導熱金屬層的模板開口；進行濺鍍步驟；以及移除該模板。
  6. 如申請專利範圍第4項所述之半導體封裝件之製法，其中，形成該導熱金屬層之步驟係包括：於該基板本體之第一表面與該半導體晶片上形成阻層，且該阻層具有對應該導熱金屬層的阻層開口；進行濺鍍或電鍍步驟；以及移除該阻層。
  7. 如申請專利範圍第6項所述之半導體封裝件之製法，其 中，該阻層係為感光性乾膜。
  8. 如申請專利範圍第4項所述之半導體封裝件之製法，復包括於該基板本體之第一表面形成連接該導熱金屬路徑的導熱孔或導熱槽，且該導熱金屬層復形成於該導熱孔或導熱槽中。
  9. 一種半導體封裝件之製法，係包括：於一導線架之一表面上接置半導體晶片；於該導線架之該表面及半導體晶片之頂面與側面上形成圖案化之導熱金屬層；以打線方式電性連接該半導體晶片與該導線架；以及於該導線架之該表面上形成包覆該半導體晶片的封裝膠體。
  10. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，形成該導熱金屬層之步驟係包括：於該導線架之該表面與該半導體晶片之上方設置模板，且該模板具有對應該導熱金屬層的模板開口；進行濺鍍步驟；以及移除該模板。
  11. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，形成該導熱金屬層之步驟係包括：於該導線架之該表面與該半導體晶片上形成阻層，且該阻層具有對應該導熱金屬層的阻層開口；進行濺鍍或電鍍步驟；以及 移除該阻層。
  12. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，該阻層係為感光性乾膜。
TW101131510A 2012-08-30 2012-08-30 半導體封裝件及其製法 TWI480986B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW101131510A TWI480986B (zh) 2012-08-30 2012-08-30 半導體封裝件及其製法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW101131510A TWI480986B (zh) 2012-08-30 2012-08-30 半導體封裝件及其製法

Publications (2)

Publication Number Publication Date
TW201409628A TW201409628A (zh) 2014-03-01
TWI480986B true TWI480986B (zh) 2015-04-11

Family

ID=50820481

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101131510A TWI480986B (zh) 2012-08-30 2012-08-30 半導體封裝件及其製法

Country Status (1)

Country Link
TW (1) TWI480986B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111918519B (zh) * 2019-05-07 2023-01-17 河南烯力新材料科技有限公司 弹性导热结构及其制造方法和电子装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090104735A1 (en) * 2005-12-14 2009-04-23 Lsi Logic Corporation Semiconductor package having increased resistance to electrostatic discharge
JP2011096830A (ja) * 2009-10-29 2011-05-12 Toyota Motor Corp 半導体装置
TW201220444A (en) * 2010-11-02 2012-05-16 Global Unichip Corp Semiconductor package device with a heat dissipation structure and the packaging method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090104735A1 (en) * 2005-12-14 2009-04-23 Lsi Logic Corporation Semiconductor package having increased resistance to electrostatic discharge
JP2011096830A (ja) * 2009-10-29 2011-05-12 Toyota Motor Corp 半導体装置
TW201220444A (en) * 2010-11-02 2012-05-16 Global Unichip Corp Semiconductor package device with a heat dissipation structure and the packaging method thereof

Also Published As

Publication number Publication date
TW201409628A (zh) 2014-03-01

Similar Documents

Publication Publication Date Title
TWI651828B (zh) 晶片封裝結構及其製造方法
TWI555166B (zh) 層疊式封裝件及其製法
TWI500130B (zh) 封裝基板及其製法暨半導體封裝件及其製法
US8330267B2 (en) Semiconductor package
TWI652787B (zh) 電子封裝件及其製法
TW201324727A (zh) 層疊封裝的封裝結構及其製法
CN104716110B (zh) 芯片封装结构及其制造方法
TWI611542B (zh) 電子封裝結構及其製法
TW201507075A (zh) 半導體封裝件及其製法
TW201603215A (zh) 封裝結構及其製法
TWI594382B (zh) 電子封裝件及其製法
TWI467731B (zh) 半導體封裝件及其製法
TWI503935B (zh) 半導體封裝件及其製法
TW201227916A (en) Multi-chip stack package structure and fabrication method thereof
TWI491017B (zh) 半導體封裝件及其製法
TWI637536B (zh) 電子封裝結構及其製法
TWI587465B (zh) 電子封裝件及其製法
TWI480986B (zh) 半導體封裝件及其製法
TWI645518B (zh) 封裝結構及其製法
CN101207105A (zh) 开窗型球栅阵列基板及其半导体封装件
TWI680547B (zh) 半導體封裝結構及其製作方法
TWI529898B (zh) 半導體封裝件及其製法
TWI435427B (zh) 半導體承載件暨封裝件及其製法
TWI541952B (zh) 半導體封裝件及其製法
TWI573230B (zh) 封裝件及其封裝基板