TWI467696B - Semiconductor process - Google Patents

Description

Semiconductor process

This invention relates to a semiconductor process and, more particularly, to a method for removing moisture from an opening.

With the rapid development of semiconductor process technology, in order to improve the speed and performance of components, the size of the entire circuit components must be continuously reduced, and the component's integrality is continuously improved. When the integration of integrated circuits is increased, so that the surface of the wafer cannot provide sufficient area to make the required interconnects, more than two layers of multi-metal interconnects become ultra-large integrated circuit (VLSI) technology. The way that must be done. The dual damascene process has the advantage of improving component reliability and increasing throughput, making it a metal interconnect technology commonly used in the semiconductor industry.

In the case where the component accumulation is required to be higher and higher, it is necessary to consider changes in the physical properties of the components (such as contact resistance between components) to avoid the operation speed and performance of the components being affected. Taking the formation of a double damascene structure as an example, the current process has an idle time after forming the barrier layer and before proceeding to the next step, so that moisture or a small amount of impurities are easily adhered to the barrier layer in the opening. . When the metal copper material is filled in the opening, the copper material filled in the opening may cause defects such as holes after the heat treatment, resulting in an increase in the contact resistance value, which seriously affects the water. The performance of the component.

Therefore, how to reduce the critical dimension of the opening, avoid the defects of the material filled in the opening and ensure the quality of the components to be formed later, to improve the process reliability and component performance is one of the problems that the industry is eager to solve.

In view of this, the present invention provides a semiconductor process that effectively removes moisture in the opening and helps to avoid formation of holes in the conductor layer.

The present invention proposes a semiconductor process. First, a substrate having at least one conductive region is provided, and a dielectric layer has been formed on the substrate. An opening exposing the conductive region is formed in the dielectric layer. A first conductor layer is conformally formed on the surface of the opening. The first cleaning step is performed with the first cleaning liquid. After the first washing step, a heating step is performed. Thereafter, a second conductor layer is filled in the opening.

In an embodiment of the invention, the temperature at which the heating step is performed is between 200 ° C and 300 ° C.

In one embodiment of the invention, the time during which the heating step is performed is between 30 minutes and 60 minutes.

In an embodiment of the invention, the first cleaning solution comprises hydrofluoric acid (HF) and sulfuric acid (H ₂ SO ₄ ). The hydrofluoric acid (HF) content is between about 0.01% and 0.1% by weight. The content of sulfuric acid (H ₂ SO ₄ ) is between about 1% by weight and 10% by weight.

In an embodiment of the invention, the first cleaning step and the heating step are performed between the step of forming the first conductor layer and the step of forming the second conductor layer.

In an embodiment of the invention, before the forming the first conductor layer, the second cleaning step is further performed with the second cleaning liquid. The second cleaning liquid includes hydrofluoric acid (HF) and sulfuric acid (H ₂ SO ₄ ).

In one embodiment of the invention, the first cleaning step is performed using a one-piece cleaning process.

In an embodiment of the invention, the first conductor layer is a barrier layer.

In an embodiment of the present invention, the material of the first conductor layer comprises a refractory metal such as titanium, titanium nitride, tungsten, tungsten nitride, titanium tungsten alloy, tantalum, tantalum nitride, nickel, nickel vanadium alloy or the like Nitride, alloy.

In an embodiment of the invention, the second conductor layer is a plug or a wire.

In an embodiment of the invention, the material of the second conductor layer comprises copper or a copper alloy.

In an embodiment of the invention, the opening comprises a contact opening, a via opening, a wire opening or a dual damascene opening.

In an embodiment of the invention, the opening has a width of 70 nm or less.

Based on the above, the present invention performs the cleaning step with the cleaning liquid after forming the conformal conductor layer on the opening surface and before the opening is filled in the other conductor layer, and then performs the heating step, thereby completely removing the water adhering to the opening. Gas or impurities. The cleaning step and the heating step after the barrier layer can help the conductor layer to fill the opening without generating holes, thereby reducing contact resistance and improving component performance.

The above described features and advantages of the present invention will be more apparent from the following description.

The semiconductor process of the present invention is mainly applied to the subsequent stage process, and further embodiments of the present invention will be further described in flow chart and cross-sectional view. 1 is a flow chart showing the steps of a semiconductor process in accordance with an embodiment of the present invention. 2A-2B are schematic cross-sectional views showing a semiconductor process in accordance with an embodiment of the present invention.

Referring to FIG. 1 and FIG. 2A, step S100 is performed to provide a substrate 200 having a conductive region 202, and a dielectric layer 204 is formed on the substrate 200. The substrate 200 is, for example, a semiconductor substrate such as an N-type or P-type germanium substrate, a tri-five semiconductor substrate, or the like. The conductive region 202 can be a germanium-containing conductive region or a metal conductive region, such as a gate, a doped region or a wire as a source drain. The material of the dielectric layer 204 is, for example, yttrium oxide, borophosphon glass, phosphor bismuth glass or a low dielectric material having a dielectric constant of less than 3. Among them, the low dielectric material is, for example, a sesquioxide semi-oxide such as Hydrogen Silsesquioxane HSQ, Methyl silsesquioxane (MSQ) and a mixed organic decane polymer (Hybrido-organo siloxane). Polymer, HOSP); Aromatic hydrocarbon such as SiLK; Organosilicate glass such as black diamond (BD), 3MS, 4MS; Parylene; fluorination Polymers (Fluoro-Polymer) such as PFCB, CYTOP, Teflon; Poly(arylethers) such as PAE-2, FLARE; Porous polymers such as XLK, Nanofoam, Aerogel; Coral, and the like.

In an embodiment, a termination stop layer 203 is further included between the conductive region 202 and the dielectric layer 204 for isolating the conductive region 202 from the dielectric layer 204. In addition, the capping layer 203 may also serve as an etch stop layer in the subsequent step of removing a portion of the dielectric layer 204 to form the opening 206. The material covering the termination layer 203 is, for example, tantalum carbonitride (SiCN) or tantalum carbide (SiC).

In step S110, an opening 206 exposing the conductive region 202 is formed in the dielectric layer 204. The opening 206 is, for example, a contact window opening, a via opening or a single damascene opening that only forms a wire. In one embodiment, the opening 206 is formed by first forming a patterned photoresist layer (not shown) on the dielectric layer 204, and then removing the uncovered portion by using the patterned photoresist layer as a mask. The electrical layer 204 is exposed to partially cover the termination layer 203. Thereafter, a portion of the capping layer 203 is removed, thereby forming an opening 206 exposing the conductive region 202, and removing the patterned photoresist layer. The method of removing a portion of the dielectric layer 204 and covering the termination layer 203 to form the opening 206 is, for example, a dry etching process.

After the dry etching process, particles or impurities such as polymers may remain on the surface of the dielectric layer 204 or the surface of the opening 206, and these residues may cause adverse effects such as leakage, short circuit, and the like in subsequent processes. Therefore, the washing step (step S120) can be selectively performed to remove the residue without affecting the subsequent process. In one embodiment, the washing step in step S120 is a diluted hydrofluoric acid solution (HF) and sulfuric acid (H ₂ SO ₄ ) as a cleaning solution. The content of hydrofluoric acid (HF) is between about 0.01wt% to 0.1wt%, while the content of sulfuric acid (H ₂ SO ₄₎ between about 1wt% to 10wt% range. The washing step in step S120 is performed, for example, by a single-wafer cleaning method.

Thereafter, step S130 is performed to form the conductor layer 208 conformally on the surface of the opening 206. That is, the conductor layer 208 covers the sidewalls and the bottom of the opening 206 along the outer shape of the opening 206, for example, as a barrier layer to enhance the surface of the conductor material and the dielectric layer 204 pre-filled into the opening 206 in a subsequent process. The ability to adhere between and prevent the diffusion of metals in the conductor material. The material of the conductor layer 208 is, for example, a refractory metal such as titanium, titanium nitride, tungsten, tungsten nitride, titanium tungsten alloy, tantalum, tantalum nitride, nickel, nickel vanadium alloy, or a nitride or alloy thereof. The method of forming the conductor layer 208 is, for example, a physical vapor deposition method or a chemical vapor deposition method.

Continuing to refer to FIG. 1 and FIG. 2B, between the step of forming the conductor layer 208 and the step of forming the conductor layer 210 that is performed in advance, water vapor 209 or a small amount of impurities are easily adhered to the conductor layer 208. This causes the formed conductor layer 210 to have defects such as holes after heat treatment. Therefore, in order to remove the moisture 209 or impurities adhering to the conductor layer 208 in the opening 206, after the conductor layer 208 is formed, steps S140 and S150 are performed.

In step S140, the washing step is performed using the washing liquid. The cleaning solution used in the washing step is, for example, a hydrofluoric acid (HF) and sulfuric acid (H ₂ SO ₄ ) solution diluted with deionized water. In one embodiment, the content of hydrofluoric acid (HF) is between about 0.01wt% to 0.1wt%, while the content of sulfuric acid (H ₂ SO ₄₎ between about 1wt% to 10wt% range. The washing step in step S140 is performed, for example, by a one-chip cleaning method.

After the completion of step S140, a heating step (step S150) is performed to completely remove the moisture 209 in the opening 206. In one embodiment, the temperature at which the heating step is performed is between about 200 ° C and 300 ° C and the heating time is between about 30 minutes and 60 minutes.

Then, in step S160, the conductor layer 210 is formed to cover the conductor layer 208 and fill the opening 206. The material of the conductor layer 210 is a metal such as copper or a copper alloy. The method of forming the conductor layer 210 is, for example, a physical vapor deposition method or a chemical vapor deposition method or a solution plating method.

In particular, since the wafer does not necessarily form the conductor layer 210 immediately after the formation of the conductor layer 208, that is, the wafer may have an idle time between the two steps, causing moisture 209 or impurities to adhere to the conductor layer. 208. Therefore, the washing step using the diluted hydrofluoric acid (HF) and sulfuric acid (H ₂ SO ₄ ) solution and then the heating step (steps S140 and S150) can effectively remove the moisture 209 before forming the conductor layer 210. It can help to prevent the conductor layer 210 filled in the opening 206 from generating holes, thereby reducing the contact resistance of the conductor layer 210 and improving the performance of the element.

In the above embodiment, for convenience of explanation, the description is made by taking a case where a contact opening, a via opening, or a single damascene opening in which only a wire is formed on the substrate 200 is exemplified, but the present invention is not limited thereto. In other embodiments, the invention may also be applied to dual damascene processes, or to processes of the 45 nm generation or less. That is, the method of the present invention can be applied to all openings having a width of 70 nm or less. It is well known to those skilled in the art that, as required by the visual process, the cleaning step and the heating step as described in steps S140 and S150 are performed after forming the barrier layer to remove moisture in the opening.

Next, the dual metal damascene process will be taken as an example to illustrate the practical application of the semiconductor process of the present invention. It should be noted that the flow described below is mainly for the purpose of detailing the cleaning step and heating step of the semiconductor process of the present invention after it is actually applied to form a barrier layer, so that those skilled in the art can implement it, but not It is intended to define the scope of the invention. The arrangement, the number, and the manner in which other components such as the substrate, the plug, the wire, the opening, or the conductive region are formed may be made according to techniques known to those skilled in the art, and are not limited to the embodiments described below. .

3A through 3D are schematic cross-sectional views showing a semiconductor process in accordance with another embodiment of the present invention.

Referring to FIG. 3A, a substrate 300 having a conductive region 302 is provided. The conductive region 302 may be formed on the substrate 300, and a dielectric layer 304 is formed between adjacent conductive regions 302, for example. The conductive region 302 is, for example, a wire in an interconnect process, such as a copper wire. The material of the dielectric layer 304 is, for example, a low dielectric material having a dielectric constant of less than 3.

Then, a dielectric layer 308 and a patterned photoresist layer 314 are sequentially formed on the substrate 300. The material of the dielectric layer 308 is, for example, a low dielectric material having a dielectric constant of less than 3, and the formation method thereof is, for example, a chemical vapor deposition method. The patterned photoresist layer 314 can be a pattern 314a having via openings. The area covered by the patterned photoresist layer 314 is, for example, above the partially conductive region 302 and above the dielectric layer 304. In an embodiment, a termination layer 306 may also be formed between the dielectric layer 308 and the conductive region 302, the dielectric layer 304. In an embodiment, the buffer layer 310 is selectively formed between the dielectric layer 308 and the patterned photoresist layer 314. In an embodiment, another layer of termination layer 312 may be selectively formed between patterned photoresist layer 314 and buffer layer 310 over conductive region 302. The termination layer 312 has an opening, and the formation of this opening is completed, for example, prior to forming the patterned photoresist layer 314, in a manner similar to that shown in FIG. 2A. The material of the termination layer 306 is, for example, tantalum carbonitride (SiCN) or tantalum carbide (SiC). The material of the buffer layer 310 is, for example, hafnium oxide or hafnium oxynitride (SiON). The material of the termination layer 312 is, for example, titanium nitride, titanium, tantalum nitride or tantalum. The method of forming the above-mentioned film layer is well known to those skilled in the art and will not be described herein.

Referring to FIG. 3B, the patterned photoresist layer 314 is used as a mask to remove a portion of the buffer layer 310, the dielectric layer 308, and the termination layer 306 to form an opening 316 to expose a portion of the surface of the conductive region 302. In one embodiment, the opening 316 is a dual damascene opening that is subsequently preformed into a dual damascene structure, including a via opening 316a and a trench 316b. The formation of the opening 316 is accomplished, for example, by a dry etching process in a single step. It is noted that when a portion of the dielectric layer 308 is removed with the patterned photoresist layer 314 as a mask, the pattern 314a is first transferred to the dielectric layer 308, and the exposed portion is terminated in the dielectric layer 308. The opening of layer 306. Then, after the patterned photoresist layer 314 is removed, since the termination layer 312 is not formed over the dielectric layer 304, continuing the dry etching process removes the buffer layer 310 and a portion of the dielectric layer above the dielectric layer 304. Layer 308, while simultaneously removing exposed termination layer 306 on conductive region 302, forms via opening 316a and trench 316b that expose portions of conductive region 302.

Thereafter, a cleaning step can be selectively performed to remove the residue of the dry etching process. The washing step is, for example, using a diluted hydrofluoric acid solution (HF) and sulfuric acid (H ₂ SO ₄ ) as a cleaning liquid, wherein the content of hydrofluoric acid (HF) is between about 0.01 wt% and 0.1 wt%, and The content of sulfuric acid (H ₂ SO ₄ ) is between about 1% by weight and 10% by weight.

Referring to FIG. 3C, a conductor layer 318 is conformally formed on the surface of the opening 316 to cover the sidewall and bottom of the opening 316. The conductor layer 318 is, for example, a barrier layer, and the material thereof is, for example, a refractory metal such as titanium, titanium nitride, tungsten, tungsten nitride, titanium tungsten alloy, tantalum, tantalum nitride, nickel, nickel vanadium alloy or nitride thereof, alloy.

During the period after the formation of the conductor layer 318 and before the filling of the conductor material of the double damascene structure in the opening 316, moisture 319 is likely to adhere to the conductor layer 318. Therefore, before the opening 316 is filled with the conductor material of the double damascene structure, the cleaning step and the heating step after the formation of the barrier layer may be performed first to completely remove the moisture 319 in the opening 316. In detail, the washing step is carried out, for example, by using a diluted hydrofluoric acid solution (HF) and sulfuric acid (H ₂ SO ₄ ) as a washing liquid. In one embodiment, the content of hydrofluoric acid (HF) is between about 0.01wt% to 0.1wt%, while the content of sulfuric acid (H ₂ SO ₄₎ between about 1wt% to 10wt% range. The temperature of the heating step after the completion of the washing step is between about 200 ° C and 300 ° C, and the heating time is between about 30 minutes and 60 minutes.

Next, referring to FIG. 3D, a conductor layer 320 is formed on the substrate 300. The conductor layer 320 fills the opening 316 and is electrically connected to the conductive region 302 to complete the fabrication of the double-layer damascene structure. The material of the conductor layer 320 is a metal such as copper or a copper alloy.

After the conductor layer 318 is formed on the surface of the opening 316 and before the conductor layer 320 is formed, the aforementioned cleaning step and heating step (steps S140 and S150 as described in FIG. 1) are utilized to completely remove the moisture 319 in the opening 316, thus It is effective to avoid the formation of holes in the conductor layer 320, thereby further reducing the contact resistance of the dual damascene structure.

In order to demonstrate that the semiconductor process of the present invention can indeed remove moisture in the opening and enhance component performance, the following experimental examples are given to illustrate the effect of the semiconductor process of the present invention on the contact resistance (Rc).

Experimental example

4 is a comparative distribution diagram of average contact resistance of a wafer measured by forming a dual damascene structure on a wafer by a conventional method and an experimental example of the present invention.

Referring to FIG. 4 , the conventional method is to form a double damascene structure by directly filling the openings with germanium and tantalum nitride as a barrier layer on the surface of the double damascene opening, and then measuring the wafer. The contact resistance of the double damascene structure of each of the wafers 402a, 402b is shown, and the contact resistance map (Rc map) is shown. In the experimental example of the present invention, after the tantalum and tantalum nitride are formed as a barrier layer on the surface of the double damascene opening, 0.06% hydrofluoric acid solution (HF) and 3% sulfuric acid (H ₂ SO ₄ ) are used as the barrier layer. The cleaning solution is subjected to a cleaning step, and then heated at a temperature of 200-300 ° C for about 30 minutes to fill the double damascene opening to complete the dual damascene structure, and the dual damascene structure of each wafer 404 on the wafer is measured. The contact resistance is shown and its contact resistance map (Rc map).

Further, the average contact resistance value of the wafer measured in the conventional method and the experimental example of the present invention is compared, wherein the range 406 represents an acceptable range of contact resistance values. It can be seen from the comparison results that the double damascene structure formed by the conventional method has a high contact resistance, and the double damascene structure formed by the experimental example of the present invention has a low contact resistance, and the experimental example of the present invention The contact resistance value will fall within the range 406.

It is explained here that since the wafer has an idle time between the two steps of forming the barrier layer and filling the opening with copper, moisture or impurities are likely to adhere to the opening. In general, wafers near the outer circumference of the wafer are more susceptible to moisture. As shown in FIG. 4, the double damascene structure formed by the conventional method has a contact resistance value on the outer ring wafer 402a higher than that on the inner ring wafer 402b, wherein the contact resistance value of the wafer 402a is The range 406 is exceeded and the contact resistance value of the wafer 402b is within the range 406. In contrast, the contact resistance values of the wafer 404 of the double damascene structure formed by the experimental example of the present invention are all within the range 406. It can be seen that the semiconductor process proposed by the present invention can reduce the contact resistance of the conductor layer, thereby achieving the effect of improving the performance of the component.

In summary, the semiconductor process of the present invention utilizes a diluted hydrofluoric acid solution (HF) and sulfuric acid (H ₂ SO ₄ ) after forming a conformal conductor layer on the open surface and before filling the opening into another conductor layer. The washing step is performed as a washing liquid, and then a heating step is performed to remove moisture or impurities adhering to the opening. By completely removing the water vapor in the opening by the cleaning step and the heating step after the barrier layer, it is possible to effectively prevent the conductor layer filled in the opening from being defective after the heat treatment, thereby reducing the contact resistance of the conductor layer and improving Component performance.

In addition, the semiconductor process utilizing the present invention can help ensure the quality of the component structures formed in the openings and significantly improve process reliability even when the critical dimensions of the openings in the 45 nm generation or less are reduced.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

200, 300. . . Base

202, 302. . . Conductive zone

203. . . Cover termination layer

204, 304, 308. . . Dielectric layer

206, 316. . . Opening

208, 210, 318, 320. . . Conductor layer

209, 319. . . steam

306, 312. . . Termination layer

310. . . The buffer layer

314. . . Patterned photoresist layer

314a. . . pattern

316a. . . Via window opening

316b. . . ditch

402a, 402b, 404. . . Wafer

406. . . range

S100, S110, S120, S130, S140, S150, S160. . . step

1 is a flow chart showing the steps of a semiconductor process in accordance with an embodiment of the present invention.

2A-2B are schematic cross-sectional views showing a semiconductor process in accordance with an embodiment of the present invention.

3A through 3D are schematic cross-sectional views showing a semiconductor process in accordance with another embodiment of the present invention.

4 is a comparative distribution diagram of average contact resistance of a wafer measured by forming a dual damascene structure on a wafer by a conventional method and an experimental example of the present invention.

S100, S110, S120, S130, S140, S150, S160. . . step

Claims (16)

A semiconductor process comprising: providing a substrate having at least one conductive region, and forming a dielectric layer on the substrate; forming an opening in the dielectric layer exposing the conductive region; conforming to a surface of the opening Forming a first conductor layer; performing a first cleaning step with a first cleaning liquid to clean the first conductor layer; and after performing the first cleaning step, performing a heating step to dry the first conductor And filling a second conductor layer in the opening such that the second conductor layer covers and contacts the first conductor layer. The semiconductor process of claim 1, wherein the temperature of the heating step is between 200 ° C and 300 ° C. The semiconductor process of claim 1, wherein the heating step is performed between 30 minutes and 60 minutes. The semiconductor process of claim 1, wherein the first cleaning liquid comprises hydrofluoric acid (HF) and sulfuric acid (H ₂ SO ₄ ). The semiconductor process of claim 4, wherein the hydrofluoric acid (HF) is present in an amount between 0.01% and 0.1% by weight. The semiconductor process of claim 4, wherein the content of the sulfuric acid (H ₂ SO ₄ ) is between 1% by weight and 10% by weight. The semiconductor process of claim 1, wherein the first cleaning step and the heating step are steps in forming the first conductor layer. The step is performed between the step of forming the second conductor layer. The semiconductor process of claim 1, further comprising performing a second cleaning step with a second cleaning solution before forming the first conductor layer. The semiconductor process of claim 8, wherein the second cleaning liquid comprises hydrofluoric acid (HF) and sulfuric acid (H ₂ SO ₄ ). The semiconductor process of claim 1, wherein the first cleaning step is performed by a one-chip cleaning method. The semiconductor process of claim 1, wherein the first conductor layer is a barrier layer. The semiconductor process of claim 1, wherein the material of the first conductor layer comprises titanium, titanium nitride, tungsten, tungsten nitride, titanium tungsten alloy, tantalum, tantalum nitride, nickel or nickel vanadium alloy. The semiconductor process of claim 1, wherein the second conductor layer is a plug or a wire. The semiconductor process of claim 1, wherein the material of the second conductor layer comprises copper or a copper alloy. The semiconductor process of claim 1, wherein the opening comprises a contact opening, a via opening, a wire opening or a dual damascene opening. The semiconductor process of claim 1, wherein the opening has a width of 70 nm or less.