CN108376676B - A metal interconnect structure with a porous dielectric layer - Google Patents

Abstract

The invention provides a metal interconnection structure with a porous medium layer, which comprises a through hole structure arranged in the porous medium layer, wherein the edge part of the through hole is lower than the upper surface of an interconnection line in a lower medium layer; a metal interconnection structure is arranged in the through hole structure and is in contact with the upper surface and part of the side surface of the interconnection line; a capping layer is over the metal interconnect structure, the capping layer having a portion located at a top surface of the metal interconnect structure and a portion located below the top surface in a second recess structure around the top surface.

Description

A metal interconnect structure with a porous dielectric layer

technical field

The present invention relates to a semiconductor interconnection structure, in particular to a semiconductor interconnection structure with a porous low-K or ultra-low-K interlayer dielectric layer.

Background technique

The rapid development of semiconductor integrated circuit technology constantly puts forward new requirements for the development of interconnection technology. At present, in the back-end process of semiconductor manufacturing, in order to connect integrated circuits composed of various components, metal materials with relatively high conductivity are usually used, but as the size of semiconductor devices continues to shrink, the interconnect structure becomes narrower and narrower. , resulting in higher and higher interconnect resistance. Copper, thanks to its excellent electrical conductivity, has been widely used in processes for 90nm and 65nm technology nodes.

In the existing process of forming copper wiring or copper interconnection, trenches or through holes are formed by etching an insulating dielectric layer, and then copper conductive material is filled in the trenches or through holes. However, as the space between the metal wires gradually shrinks, the insulating dielectric layer used to isolate the metal wires becomes thinner and thinner, which may lead to unfavorable interactions between the metal wires or crosstalk. It has been found that reducing the dielectric constant (K) of the insulating dielectric layer used to isolate the metal wiring layer can effectively reduce this crosstalk. At the same time, reducing the K value of the interlayer dielectric layer material can also effectively reduce the interconnection. Resistor-capacitor delay effect (RC delay).

However, the use of low-K or ultra-low-K insulating dielectric materials brings new requirements to the semiconductor manufacturing process. On the one hand, in order to obtain low-K or ultra-low-K materials and reduce the K value of the material, porous materials are usually used. However, the mechanical strength of the porous material is low, which leads to the easy damage of the insulating medium layer during the process of etching through holes or trenches. On the other hand, the porous insulating medium layer is easily penetrated by external materials, causing pollution. , reducing the reliability of the material. Some studies have pointed out that the "open" pore structure exposed to the outside when the porous dielectric layer is etched can be formed into a closed structure through an additional "blocking" process, so as to prevent metal impurities from being easily formed when the interconnect structure is formed. Defects entering the hole, however, the additional process not only increases the cost, but also easily changes the morphology of the through hole or trench formed by etching, resulting in an unsatisfactory effect of the final interconnect structure; and usually the case There are other interconnect structures under the through holes or trenches formed in the interlayer dielectric layer. During etching, it is easy to cause damage to the underlying interconnect structure. At the same time, the through holes or trenches are filled with Between the metal (usually copper) and the underlying interconnect layer, during the deposition or heat treatment step, the induced stress is prone to peel off, causing the metal filled in the via or trench and the underlying interconnect line. Poor contact will have a great impact on the stability and reliability of semiconductor devices.

At the same time, after forming the metal interconnect structure (usually copper metal), in order to enhance the electromigration characteristics, it has been proved that the Cu/metal interface instead of the Cu/dielectric interface can improve the electromigration characteristics by more than 100%, and the material of the metal cap layer is usually selected. It is a metal containing Co (such as CoWP), but in the subsequent cleaning step after forming the interconnect structure, dilute hydrofluoric acid is usually used, which will corrode the metal of Co and cause the performance of the device to decrease.

In view of the above problems, it is necessary to provide an interconnect structure with a porous low-K or ultra-low-K interlayer dielectric layer, on the one hand, to reduce damage or pollution to the interlayer dielectric layer, and at the same time to prevent the underlying interconnection. When the wire structure is damaged and the electromigration performance is improved, the technology of the cap layer must also have a certain stability, which can prevent acid corrosion.

SUMMARY OF THE INVENTION

A series of concepts in simplified form are introduced in the Summary of the Invention, which will be described in detail in the Detailed Description.

The technical problem solved by the present invention is to provide a semiconductor structure with a porous dielectric layer, which can prevent damage or pollution to the interlayer dielectric layer during the preparation process, and prevent damage to the underlying interconnect structure, while increasing the interlayer dielectric. Robustness between the metal filled in the layer and the underlying interconnects without the need for an additional "plugging" step of the porous interlayer dielectric layer, reducing cost, and having a stable cap layer structure for improved electromigration performance , improve the stability and reliability of semiconductor devices.

In order to solve the above problems, a metal interconnection structure with a porous dielectric layer is characterized in that, it includes the following structures: an interconnection structure located in a lower dielectric layer; a nitrogen-rich etch stop located on the lower dielectric layer a detection layer; a porous dielectric layer on the nitrogen-rich etch stop detection layer; a through-hole structure is formed in the porous dielectric layer, the through-holes extend down to above the interconnect lines, the through-holes The edge part of the hole is lower than the upper surface of the interconnect line, a first groove structure is formed around the interconnect line in the lower dielectric layer, and the through hole structure in the porous dielectric layer is formed by femtosecond laser etching , during the etching process, local melting of the exposed pore structure in the porous medium layer seals the exposed pore structure; there is a metal interconnection structure in the through-hole structure, and the metal interconnection structure is connected with the exposed pore structure. The interconnection line surface and part of the side surface are in contact, and the metal interconnection structure includes a part located in the first groove structure; the metal interconnection structure is provided with a capping layer, and the capping layer has a part located in the first groove structure; A portion of a top surface of the metal interconnect structure and a portion of a second recess structure surrounding the top surface below the top surface.

Further, the material of the interconnect structure is copper, and the material of the metal interconnect structure in the via structure is copper.

Further, the porous medium layer is a low-K or ultra-low-K material.

Further, the nitrogen-rich etch stop detection layer is nitrogen-containing silicon oxide.

Further, the capping layer is a nitrogen-containing metal layer, wherein the metal is Ir or Ru.

Further, the length of the downward extending length of the contact portion between the metal interconnection structure in the through hole and the side surface of the interconnection line, that is, the depth of the first groove is about 5-20 nm.

Further, the downward length of the portion of the capping layer below the top surface of the metal interconnect structure, that is, the depth of the second groove is about 5-20 nm.

Further, the surface of the interconnect structure is a surface that has undergone hydrogen reduction treatment, and the first groove structure in the lower dielectric layer is formed by over-etching in a hydrogen atmosphere.

Further, the second groove is formed by femtosecond laser etching.

Further, a barrier layer is further included in the first groove, and the barrier layer is located between the metal interconnection structure and the lower dielectric layer; the second groove further includes a barrier layer, and the barrier layer is located in the between the capping layer and the porous medium layer.

Compared with the prior art, the present invention has the following beneficial technical effects:

1. Femtosecond lasers with ultra-short pulse time (usually 10 ^-15 m/s) have super high focusing ability. Femtosecond lasers can quickly and accurately concentrate all their energy in a small area of action. It can be etched quickly and accurately, and there are few side effects. After etching, there is no need to clean and remove the residue. The high temperature generated by the femtosecond laser during etching affects the dielectric layer at the edge of the exposed porous structure. By melting, the melted dielectric layer can block the exposed open pore structure, that is, the open pore structure is sealed during the etching process, and no additional steps are required. The through-hole structure of the porous dielectric layer in the structure is formed by femtosecond laser etching without the need for additional sealing of the hole structure;

2. In order to prevent the oxidation of the surface of the interconnect, and to reduce the oxide layer that may be formed on the surface of the interconnect, hydrogen is introduced to reduce the interconnect layer when the interconnect layer is exposed. Entering hydrogen, even if the surface of the interconnection wire has an oxide layer (usually copper oxide) in the previous step, the introduced hydrogen gas reduces it to copper, that is, the surface of the underlying interconnection wire structure in the metal interconnection structure is The surface that has undergone hydrogen reduction treatment; and the lower dielectric layer has a first groove structure surrounding the interconnect structure, and the first groove structure is formed by over-etching in a hydrogen atmosphere. When filling the interconnection metal, the interconnection metal is filled in the groove, and the interconnection metal "wrapped" below the interconnection line is formed, which not only increases the contact area, but also improves the firmness of the contact to improve stability and reliability. reliability.

3. The material of the capping layer above the metal interconnection structure is a nitrogen-containing metal layer, wherein the metal is Ir or Ru, and Ir or Ru metal is more stable than metal Co, even in the subsequent cleaning process. Corrosion, while preventing oxidation, can improve the electromigration characteristics of the Cu/metal interface, and in order to prevent the capping layer from peeling off from the metal interconnect structure, the capping layer is not only formed on the top surface of the metal interconnect structure, but also formed In the second groove surrounding the top surface of the metal interconnection structure, a snap-fit structure is formed, which not only increases the contact area, but also improves the contact stability.

In conclusion, the method can not only reduce the fabrication process, but also improve the stability and reliability of the semiconductor device.

Description of drawings

1 is a schematic diagram of a semiconductor interconnection structure in an embodiment of the present invention;

Figure 2a shows the "open" hole structure exposed at the opening of the trench when traditional dry etching is used, and Figure 2b shows the hole at the opening of the trench when femtosecond laser etching is used in the present invention The "sealed" state of the structure.

Detailed ways

In the following description, the method for fabricating the semiconductor interconnection structure proposed by the present invention will be further described in detail with reference to the accompanying drawings and embodiments, so as to provide a more thorough understanding of the present invention through specific details. It should be noted that, the accompanying drawings are all in a very simplified form and in inaccurate scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention. In the embodiments, in order to avoid confusion with the present invention, some technical features known in the art are not described.

Please refer to the metal interconnection structure of the present invention shown in FIG. 1 , which includes an interconnection structure 2 located in a lower dielectric layer 1 . The lower dielectric layer 1 may also include a substrate substrate structure. The substrate substrate structure may be a common semiconductor substrate in the field, such as a silicon substrate or an SOI substrate structure. The lower dielectric layer 1 may be silicon oxide, silicon oxynitride, It is formed of insulating materials such as black diamond or methyl silicate compound, and the interconnection line 2 in the lower dielectric layer can be a copper interconnection line. repeat;

It also includes a nitrogen-rich etch stop detection layer 3 on the lower dielectric layer 1 . A nitrogen-rich etch stop detection layer 3 is formed on the lower dielectric layer 1 , and the etch stop detection layer 3 covers the lower dielectric layer 1 and covers the interconnect lines 2 . The material of the nitrogen-rich etch termination detection layer is nitrogen-containing silicon oxide, and the formation process of the nitrogen-rich etch termination detection layer 3 is a chemical vapor deposition deposition process, and nitrogen gas or ammonia gas is introduced into the deposition process. , to increase the nitrogen content in the silicon oxide to distinguish it from the nitrogen content in the subsequently formed material (such as the subsequently formed dielectric layer), so as to facilitate the subsequent detection in the etching step of forming the through hole;

It also includes a porous dielectric layer 4 on the nitrogen-rich etch stop detection layer 3 . A porous dielectric layer 4 is formed on the nitrogen-rich etch stop detection layer 3 . The porous medium layer 4 is a low-K or ultra-low-K material, and the material of the low-K or ultra-low-K porous medium layer can be a silicon-based polymer material with a dielectric constant (K value) of 2.2-2.9, such as HSQ , MSQ, etc., it can also be porous SiLK, the method of forming a low-K or ultra-low-K porous medium layer can be a spin coating process, and the thickness of the formed porous medium layer is 200-300nm;

It also includes a through-hole structure in the porous medium layer, the through-holes extend downward to above the interconnection lines, and the edge portion of the through-holes is lower than the upper surface of the interconnection lines, at the lower layer A first groove structure is formed around the interconnection line in the dielectric layer, the through hole structure in the porous dielectric layer is formed by femtosecond laser etching, and the hole structure exposed in the porous dielectric layer is exposed during the etching process. The localized melting seals the exposed pore structure. Specifically, when forming the through-hole structure in the porous medium layer, after forming the porous medium layer 4, a low-K buffer layer is formed on the porous medium layer 4. The material of the low-K buffer layer can be porous silica, which It has good contact performance with the underlying porous dielectric layer, and also has good contact performance with the upper metal hard mask layer, which is formed between the metal hard mask layer and the porous dielectric layer, which can buffer the transition and improve the The role of adhesion. A metal hard mask layer is formed on the low-K buffer layer. The thickness of the metal hard mask layer is 15-20 nm. The low-K buffer layer and the metal hard mask layer can be formed by CVD or PVD. The mask can be made of materials such as TaN, TiN or Ti, and a photoresist layer is coated on the metal hard mask layer. After exposure and development, a photoresist layer with an opening pattern is formed, wherein the opening pattern is aligned with the underlying The interconnection line structure, and the width of the cross-section of the opening is larger than the cross-sectional width of the interconnection line, the width of the opening can be 1-50nm wider than the cross-sectional width of the interconnection line, and the thickness of the photoresist layer with the opening pattern can be 250-300nm; Next, using the photoresist layer as a mask, a first etching is performed on the underlying metal hard mask layer and the low-K buffer layer. The first etching uses oxygen plasma etching with a first source power, wherein the oxygen plasma The etching is carbon dioxide plasma etching, a first opening is formed on the metal hard mask layer and the low-K buffer layer, and after the first opening structure is formed, a step of removing the remaining photoresist is also included. Next is the etching step of the porous medium layer. As shown in FIG. 2a, it is a schematic diagram of using the existing dry etching method. Dry etching (usually plasma etching) is used to form openings in the porous medium layer. , the porous dielectric layer on both sides of the opening (the dotted line in Figure 2a) is etched, because the porous dielectric layer usually has many pore structures, and when the opening is formed by etching, the pore structure will also be etched. Etching, that is, in the enlarged part, there will be many pore structures with openings exposed at the etch boundary (the interior of which is the interior of the porous dielectric layer, the internal morphology of which is not shown), and these open The pore structure will have a lot of impurities remaining in the subsequent cleaning steps and deposition steps. These impurities will enter the porous dielectric layer in the subsequent high temperature process, which will have a great impact on the dielectric constant of the porous dielectric layer, and ultimately affect the porous dielectric layer. device performance. The present invention adopts a femtosecond laser etching process, which is different from traditional dry etching (using plasma to bombard the surface to be etched), and the femtosecond laser has an ultra-short pulse time (usually 10 ^-15 m/s), with super high focusing ability, it can concentrate all its energy quickly and accurately in a small area of action, and can etch quickly and accurately during etching, and rarely produce side effects After etching, there is no need to clean and remove residues; the high temperature generated by the femtosecond laser during etching melts the porous medium layer at the edge of the exposed porous structure, and the molten porous medium layer can be exposed. The structure is blocked, that is, the open pore structure is sealed during the etching process without additional steps. For the structure shown in Figure 2b, the enlarged structure is etched after etching At the boundary, the open pore structure is blocked to a certain extent; after the porous dielectric layer is etched to form the opening, through detection, when the nitrogen-rich etching termination detection layer is etched, the femtosecond laser etching is stopped. Etching, nitrogen plasma is used for the third etching, and hydrogen reducing gas is introduced during the etching process. Since the etching termination detection layer 3 is a nitrogen-rich material, a large amount of nitrogen-containing gas is detected in the exhaust gas of the etching. Substances (the metal hard mask layer and the interlayer dielectric layer are all nitrogen-free substances, even if there is nitrogen in a small amount), that is, etching to the etch stop detection layer, nitrogen plasma etching uses ammonia plasma etching. The source power value of the third etching is selected to be greater than the source power value of the first etching, which can prevent the edge of the photoresist opening caused by the high-power etching step during the etching process using the photoresist opening as a mask. Deformation will occur under the action of ion bombardment, which will affect the subsequent opening morphology. At the same time, in the third etching step, the opening with a metal hard mask is used as a mask. The material is harder than the photoresist, and the high power The high-power etch does not distort the topography of the opening, and the high-power etch step shortens the etch time. During the etching process, hydrogen gas is introduced, mainly to prevent the copper interconnects from being oxidized by the residual oxygen in the etching chamber after the interconnects are exposed, and after the underlying interconnects are exposed, the hydrogen is continuously introduced Hydrogen, and finally obtain an open structure in the interlayer dielectric layer, and the continuous introduction of hydrogen is 1-10 minutes. The continuous introduction of hydrogen is mainly to inevitably oxidize the surface of the copper interconnect in the previous steps. The layer is reduced to reduce the resistance of the copper interconnect line; and in the process of etching to form the second opening structure, the underlying dielectric layer is over-etched, and a first groove structure is formed around the interconnect line;

It also includes a metal interconnection structure 5 in the through hole structure, the metal interconnection structure 5 is in contact with the surface of the interconnection line and part of the side surface, and the metal interconnection structure includes a metal interconnection structure located on the first part in the groove structure. The specific forming process is as follows: a barrier layer, a seed layer and a metal layer are formed in the through hole structure in the formed porous medium layer and the first groove structure around the formed interconnection line, and the material of the metal layer can be It is copper, and the barrier layer is TiN. The metal layer can be formed by electroplating, and then the excess copper metal layer on the surface of the porous dielectric layer outside the through-hole structure is removed through the CMP process to form a metal interconnection structure. The connecting metal layer will be filled in the first groove, and then "wrapped" the underlying interconnection line, which not only increases the contact area, but also improves the firmness of the contact. The length of the downward extension of the contact portion on the side surface of the interconnection line, that is, the depth of the first groove is 5-20 nm;

Also included is a capping layer 6 over the metal interconnect structure, the capping layer 6 having a portion located on the top surface of the metal interconnect structure 5 and a first surface surrounding the top surface located below the top surface. Parts in a two-groove structure. The specific forming process is to form a second groove structure around the surface of the metal interconnect structure by femtosecond laser etching, and then after forming a barrier layer in the second groove, a capping layer 6 is formed, wherein the capping layer is located in the second groove. The length of the downward extension of the part below the top surface of the metal interconnection structure, that is, the depth of the second groove is 5-20 nm. The material of the capping layer is a nitrogen-containing metal layer, wherein the metal is Ir or Ru. Ir or Ru metal is more stable than metal Co, it will not corrode even in the subsequent cleaning process, and can also prevent oxidation , the electromigration characteristics of the Cu/metal interface can be improved, and in order to prevent the capping layer from peeling off from the metal interconnect structure, the capping layer is not only formed on the top surface of the metal interconnect structure, but also formed around the top of the metal interconnect structure. In the second groove around the surface, a snap-fit structure is formed, which not only increases the contact area, but also improves the contact stability.

In conclusion, the semiconductor interconnect structure with a porous dielectric layer can not only reduce the preparation process, but also eliminate the need for an additional step of "plugging" the open pore structure with multiple exposures. Improve the contact area between the interconnection metal and the underlying metal interconnection line and improve the contact firmness of the two, and at the same time, have a stable capping layer structure to improve the electromigration performance, and improve the stability and reliability of semiconductor devices .

The present invention has been described by the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope of protection of the present invention . The protection scope of the present invention is defined by the attached claims and their equivalents.

Claims (7)

1. A metal interconnect structure with a porous dielectric layer, characterized in that, comprising the following structures: The interconnect structure in the underlying dielectric layer; a nitrogen-rich etch stop detection layer on the underlying dielectric layer; a porous dielectric layer on the nitrogen-rich etch stop detection layer; There is a through hole structure in the porous medium layer, the through hole structure extends downward to above the interconnection line, the edge part of the through hole structure is lower than the upper surface of the interconnection line, and the lower dielectric layer has a through hole structure. A first groove structure is formed around the interconnection line in the layer, the through hole structure in the porous medium layer is formed by femtosecond laser etching, and the hole structure exposed in the porous medium layer is formed during the etching process. localized melting seals the exposed via structure; within the via structure there is a metal interconnect structure, the metal interconnect structure is in contact with the interconnect line surface and a portion of the side surface, and the metal interconnect structure includes having a portion located in the first recess structure; a capping layer over the metal interconnect structure, the capping layer having a portion located on a top surface of the metal interconnect structure and below the top surface the portion located in the second groove structure around the top surface; Wherein, the capping layer is a nitrogen-containing metal layer, and the material of the metal layer is Ir or Ru; the surface of the interconnect structure is a surface subjected to hydrogen reduction treatment, and all the materials in the lower dielectric layer are The first groove structure is formed by over-etching in a hydrogen atmosphere; the second groove structure is formed by femtosecond laser etching. 2 . The metal interconnection structure according to claim 1 , wherein the material of the interconnection line structure is copper, and the material of the metal interconnection structure in the via structure is copper. 3 . 3. The metal interconnection structure of claim 1, wherein the porous dielectric layer is a low-K or ultra-low-K material. 4 . The metal interconnect structure of claim 1 , wherein the nitrogen-rich etch stop detection layer is nitrogen-containing silicon oxide. 5 . 5. The metal interconnection structure of claim 1, wherein the length of the downwardly extending length of the contact portion between the metal interconnection structure in the through hole structure and the side surface of the interconnection line is equal to The depth of the first groove structure is 5-20 nm. 6 . The metal interconnect structure of claim 1 , wherein the length of the downwardly extending portion of the capping layer below the top surface of the metal interconnect structure is the second groove. 7 . The depth of the structures is 5-20 nm. 7. The metal interconnect structure of claim 6, further comprising a barrier layer in the first recess structure, the barrier layer being located between the metal interconnect structure and the underlying dielectric layer; the second recess structure A barrier layer is also included in the groove structure, and the barrier layer is located between the capping layer and the porous medium layer.

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