TWI463658B - Transistor device - Google Patents

Description

Transistor device

The invention relates to a crystal device, in particular to a crystal device for improving the bonding force of an electrical connection structure.

Generally, Flexible Electronics sets microelectronic components on flexible flexible plastic or thin metal substrates, and has the advantages of flexibility, low cost, and large area, which makes the technology of soft electronic products gradually. Replacing traditional electronic components using hard tantalum wafers or glass as the substrate material.

At present, in the soft electronic manufacturing technology, the related materials of the transistor and the technology of the deposition process enable the manufacturer to form a multi-layer circuit pattern on the plastic substrate in a low-cost and simple process; and it is commonly used in soft electronic products. The crystal system is an Organic Thin-Film Transistors (OTFTs), which is not only low in cost, but also makes OTFTs more suitable for flexible plastic electronic products in a low temperature environment. The OTFTs can be divided into two structures: a top gate and a bottom gate, and the bottom gate structure can be divided into two types; see FIGS. 1A to 1C.

As shown in FIG. 1A, a gate-type organic thin film transistor embedded in a package substrate is formed on the substrate 14 to form a source 101 and a drain 102, and then the substrate 14. The semiconductor material 10 having the first surface 10a and the second surface 10b is formed on the source electrode 101 and the drain electrode 102, and the first surface 10a is bonded to the substrate 14 to make the source electrode 101 and the drain electrode 102. Embedded in the first surface 10a of the semiconductor material 10, and forming a dielectric layer 11 on the second surface 10b of the semiconductor material 10, overlying the dielectric layer 11 and corresponding to the source 101 and the drain A gate 12 is formed at a position between the terminals 102; wherein the source 101, the drain 102, and the gate 12 are made of gold (Au); and further, the gate 12 and the dielectric layer 11 are over A line build-up structure (not shown) is formed.

As shown in FIG. 1B, a gate-type organic thin film transistor embedded in a package substrate is formed on the substrate 14' to form a gate 12', and then a dielectric layer 11' is disposed on the substrate 14. 'and the gate 12', the gate 12' is embedded in the substrate 14', and the dielectric layer 11' is bonded to the semiconductor material 10' having the first surface 10a' and the second surface 10b' ', and the first surface 10a' is bonded to the dielectric layer 11', and the second surface 10b' of the semiconductor material 10' has a source 101' and a drain 102', such that the gate 12' Corresponding to the position between the source 101' and the drain 102'; wherein the material forming the source 101', the drain 102' and the gate 12' is a gold material.

As shown in FIG. 1C, a gate-type organic thin film transistor embedded in a package substrate is formed on the substrate 14" to form a gate 12" on the substrate 14' and the gate 12". The dielectric layer 11" has the gate 12" embedded in the dielectric layer 11", and the dielectric layer 11" has a source 101" and a drain 102" thereon, and has a first surface 10a The semiconductor material 10" of the "second surface 10b" is formed on the dielectric layer 11", the source 101" and the drain 102", and the first surface 10a" covers the dielectric layer 11", the source 101" and the drain 102", the gate 12" corresponds to a position between the source 101" and the drain 102"; wherein the source 101", the drain 102" and the gate 12" are formed The material is gold.

However, the bonding force between the gate made of gold material and the dielectric layer made of organic material is poor, so when the gate is combined with the dielectric layer, or when the line build-up structure is formed on the gate When the dielectric layer is on the dielectric layer, the gate made of the gold material is not easily combined with the dielectric layer, which leads to the occurrence of delamination, which is not conducive to the conduction blindness of the wiring structure of the transistor structure and the subsequent process. The holes are electrically connected.

Therefore, how to avoid the problem that the bonding force between the gate made of gold material and the dielectric layer made of organic material is poor in the conventional technology has become a problem to be solved at present.

In view of the above-mentioned various deficiencies of the prior art, the present invention mainly provides a transistor device for improving the bonding strength of an electrical connection structure.

A transistor device according to the present invention includes: a semiconductor material having a first surface and a second surface; a source and a drain are disposed on the first surface and embedded in the semiconductor material to form the semiconductor device The material of the source and the drain is copper; the dielectric layer is disposed on the second surface of the semiconductor material; the gate is disposed on the dielectric layer and is located at the corresponding source and the drain The material is formed as a copper material; and the metal layer is disposed on the upper surface and the side surface of the gate, and the material of the metal layer is nickel/gold material.

The present invention discloses a transistor device comprising: a semiconductor material having a first surface and a second surface; a source and a drain are disposed on the first surface and embedded in the semiconductor material to form the source The material of the pole and the bungee is nickel/palladium material, palladium/gold material or gold material; the dielectric layer is disposed on the second surface of the semiconductor material; and the gate is disposed on the dielectric layer. And located at a position corresponding to the source and the drain, and the material forming the gate is nickel/palladium material, palladium/gold material, or gold material; and the first metal layer is disposed on the gate The upper surface, and the material forming the first metal layer is a copper material.

In one of the foregoing embodiments, the first metal layer may extend to a side surface of the gate. In another embodiment, the second metal layer is disposed on the lower surface of the gate, and the material forming the second metal layer is a copper material.

The invention further discloses a transistor device comprising: a semiconductor material having a first surface and a second surface; a source and a drain electrode disposed on the second surface to form a material of the source and the drain Is a copper material; a dielectric layer is disposed on the first surface of the semiconductor material, and has a third surface and a fourth surface, and the fourth surface is bonded to the first surface; the gate is provided The third surface is embedded in the dielectric layer and located at a position corresponding to the source and the drain, and the material forming the gate is copper; and the metal layer is disposed on the gate The upper surface and the side surface, and the material of the metal layer may be nickel/gold.

The invention further discloses a transistor device comprising: a semiconductor material having a first surface and a second surface; a source and a drain, disposed on the second surface, and forming a material of the source and the drain a nickel/palladium material, a palladium/gold material, or a gold material; a dielectric layer disposed on the first surface of the semiconductor material and having a third surface and a fourth surface, and bonded to the fourth surface The first surface; the gate is disposed on the third surface and embedded in the dielectric layer, and is located at a position corresponding to the source and the drain, and the material forming the gate is nickel/palladium a material, a palladium/gold material, or a gold material; and a first metal layer disposed on the upper surface of the gate, and the material forming the first metal layer is a copper material.

One of the foregoing embodiments may include a second metal layer disposed on a lower surface of the gate, and the material forming the second metal layer may be a copper material. In another embodiment, the first metal layer may extend to a side surface of the gate.

The present invention further discloses a transistor device comprising: a semiconductor material having a first surface and a second surface; a source and a drain are disposed on the first surface and embedded in the semiconductor material to form the source The material of the pole and the bungee is a copper material; the dielectric layer is disposed on the first surface of the semiconductor material, and has a third surface and a fourth surface, and the fourth surface is bonded to the first surface; a gate electrode is disposed on the third surface and embedded in the dielectric layer, and is located at a position corresponding to the source and the drain, and the material forming the gate is copper; and the metal layer It is disposed on the upper surface and the side surface of the gate, and the material of the metal layer may be nickel/gold material.

The invention further discloses a transistor device, comprising: a semiconductor material having a first surface and a second surface; a source and a drain are disposed on the first surface and embedded in the semiconductor material, and the source is formed The material of the pole and the bungee is nickel/palladium material, palladium/gold material or gold material; the dielectric layer is disposed on the first surface of the semiconductor material and has a third surface and a fourth surface, and The fourth surface is coupled to the first surface; a gate is disposed on the third surface and embedded in the dielectric layer, and is located at a position corresponding to the source and the drain, and the gate is formed The material is nickel/palladium material, palladium/gold material, or gold material; and the first metal layer is disposed on the upper surface of the gate, and the material forming the first metal layer is copper.

One of the foregoing embodiments may include a second metal layer disposed on a lower surface of the gate, and the material forming the second metal layer may be copper. In another embodiment, the first metal layer may extend to a side surface of the gate.

It can be seen from the above that the gate of the transistor device of the present invention utilizes copper material with nickel/gold material, nickel/palladium material with copper material, palladium/gold material with copper material, or gold material with copper material to utilize copper material and The organic material has the characteristics of good bonding force, so that when the gate electrode is bonded to the dielectric layer, the bonding force between the gate electrode and the dielectric layer can be improved by the copper material, so that the gate electrode and the dielectric layer are not easily separated. Therefore, delamination can be avoided to facilitate the electrical connection between the transistor device and the line build-up structure, thereby achieving the purpose of improving the bonding force of the electrical connection structure.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

[First Embodiment]

Referring to FIG. 2A, the upper gate transistor device of the present invention includes a substrate 24, a semiconductor material 20, a source 201 and a drain 202, a dielectric layer 21, and a gate 22.

The semiconductor material 20 has a first surface 20a and a second surface 20b, and is bonded to the substrate 24 by the first surface 20a.

The source 201 and the drain 202 are disposed on the substrate 24 and are disposed on the first surface 20a and embedded in the semiconductor material 20, and the material forming the source 201 and the drain 202 is copper. material.

The dielectric layer 21 is disposed on the second surface 20b of the semiconductor material 20, and the material forming the dielectric layer 21 is made of an organic material.

The gate 22 is disposed on the dielectric layer 21 and located between the corresponding source 201 and the drain 202, and the material forming the gate 22 is copper; The upper surface and the side surface of the gate 22 are covered with a metal layer 23, and the material forming the metal layer 23 is a nickel/gold material.

In the present invention, since the gate 22 made of a copper material has a better bonding property with the dielectric layer 21 made of an organic material, when the gate 22 is provided on the dielectric layer 21, the system can be The gate 22 of the copper material is used to enhance the bonding force with the dielectric layer 21, so that the gate 22 and the dielectric layer 21 can be easily and effectively combined to avoid delamination; or, in the subsequent process, when When the dielectric layer of the line build-up structure (not shown) is formed on the gate 22 and the dielectric layer 21, it is also advantageous for the transistor device buried in the package substrate and the conductive blind hole of the line build-up structure to be electrically operated. Sexual connection.

Referring to FIG. 2B, in another embodiment, the material forming the source 201', the drain 202', and the gate 22' is a nickel/palladium material, and is formed on the upper surface of the gate 22'. The first metal layer 23a is formed of a copper material, and a second metal layer 23b made of copper is formed on the lower surface of the gate 22'.

Referring to FIG. 2C, in other embodiments, the material forming the source 201", the drain 202" and the gate 22" is palladium/gold or gold, and above the gate 22" The surface extends to form a first metal layer 23a" on the side surface, and the material forming the first metal layer 23a" is a copper material.

The material of the gate 22', 22" of the present invention is nickel/palladium material and then copper, palladium/gold material and copper material, or gold material and copper material, and the bonding force of the copper material and the organic material. Preferably, the gate 22', 22" is disposed on the dielectric layer 21, so that the gate 22', 22" and the dielectric layer 21 are easily and effectively combined, thereby avoiding delamination to facilitate the transistor. Electrically connected to the line build-up structure.

[Second embodiment]

Please refer to FIG. 3A, which is a gate type transistor device of the present invention, comprising: a substrate 34, a semiconductor material 30, a source 301 and a drain 302, a dielectric layer 31, and a gate 32.

The semiconductor material 30 has a first surface 30a and a second surface 30b. The source 301 and the drain 302 are disposed on the second surface 30b, and the material forming the source 301 and the drain 302 is a copper material. The dielectric layer 31 is disposed on the first surface 30a of the semiconductor material 30, and the dielectric layer 31 has a third surface 31a and a fourth surface 31b, and the fourth surface 31b is bonded to the first surface. 30a, and the material forming the dielectric layer 31 is made of an organic material. The gate 32 is disposed on the third surface 31a and embedded in the dielectric layer 31, and is located between the corresponding source 301 and the drain 302, and the material forming the gate 32 is The copper material is covered with a metal layer 33 on the upper surface and the side surface of the gate 32, and the material forming the metal layer 33 is a nickel/gold material. In addition, the substrate 34 is disposed on the dielectric layer 31 and the lower surface of the gate 32.

Referring to FIG. 3B, in another embodiment, the material forming the source 301', the drain 302', and the gate 32' is a nickel/palladium material, and is formed on the upper surface of the gate 32'. The first metal layer 33a is formed of a copper material, and a second metal layer 33b made of a copper material is formed on the lower surface of the gate 32'.

Referring to FIG. 3C, in other embodiments, the material forming the source 301", the drain 302", and the gate 32" is palladium/gold or gold, and is on the upper surface of the gate 32". The first metal layer 33a" is formed on the side surface, and the material forming the first metal layer 33a" is a copper material.

In the present invention, since the gate 32 made of copper material has a better bonding property with the dielectric layer 31 made of an organic material, when the gate electrode 32 is provided on the dielectric layer 31, the system can be The gate 32 of the copper material enhances the bonding force with the dielectric layer 31, so that the gate electrode 32 and the dielectric layer 31 are easily and effectively combined, thereby avoiding delamination, thereby facilitating embedding in the package substrate. The transistor device is electrically connected to a wiring layer (not shown) and a conductive blind via (not shown) in the substrate 34.

Furthermore, the material of the gate 32', 32" of the present invention is a nickel/palladium material which is further combined with a copper material, a palladium/gold material, and a copper material, or a gold material, and a copper material, because the copper material and the organic material are The bonding force is good, so that the gates 32', 32" are disposed on the dielectric layer 31, so that the gates 32', 32" and the dielectric layer 31 can be easily and effectively combined, thereby avoiding delamination.

[Third embodiment]

Referring to FIG. 4A, another embodiment of a lower gate transistor device of the present invention includes a substrate 44, a semiconductor material 40, a source 401 and a drain 402, a dielectric layer 41, and a gate 42.

The semiconductor material 40 has a first surface 40a and a second surface 40b. The source electrode 401 and the drain electrode 402 are disposed on the first surface 40a and embedded in the semiconductor material 40, and the material forming the source electrode 401 and the drain electrode 402 is made of copper. The dielectric layer 41 is disposed on the first surface 40a of the semiconductor material 40, and the dielectric layer 41 has a third surface 41a and a fourth surface 41b, and is bonded to the semiconductor material 40 by the fourth surface 41b. The first surface 40a is formed, and the material forming the dielectric layer 41 is made of an organic material. The gate 42 is disposed on the third surface 41a and embedded in the dielectric layer 41, and is located between the corresponding source 401 and the drain 402, and the material forming the gate 42 is The copper material is covered with a metal layer 43 on the upper surface and the side surface of the gate 42, and the material forming the metal layer 43 is a nickel/gold material. In addition, the substrate 44 is disposed on the third surface 41a of the dielectric layer 41 and the lower surface of the gate 42.

Referring to FIG. 4B, in another embodiment, the material forming the source 401', the drain 402', and the gate 42' is a nickel/palladium material, and is formed on the upper surface of the gate 42'. The first metal layer 43a is formed of a copper material, and a second metal layer 43b made of copper is formed on the lower surface of the gate 42'.

Referring to FIG. 4C, in other embodiments, the material forming the source 401", the drain 402" and the gate 42" is palladium/gold or gold, and above the gate 42" The surface extends to form a first metal layer 43a" on the side surface, and the material forming the first metal layer 43a" is a copper material.

In the present invention, since the gate 42 made of a copper material has a better bonding property with the dielectric layer 41 made of an organic material, when the gate 42 is provided on the dielectric layer 41, the system can be The gate 42 of the copper material enhances the bonding force with the dielectric layer 41, so that the gate 42 and the dielectric layer 41 are easily and effectively combined, thereby avoiding delamination, thereby facilitating embedding in the package substrate. The transistor device is electrically connected to a wiring layer (not shown) and a conductive blind via (not shown) in the substrate 44.

Furthermore, the material of the gate 42', 42" of the present invention is a nickel/palladium material which is further combined with a copper material, a palladium/gold material and a copper material, or a gold material, and a copper material, because of the copper material and the organic material. The bonding force is good, so the gate 42', 42" is disposed on the dielectric layer 41, so that the gate 42', 42" and the dielectric layer 41 can be easily and effectively combined, thereby avoiding delamination.

In summary, the gate of the present invention is coated with nickel/gold, nickel/palladium-coated copper or gold-clad copper material by copper, so as to utilize the characteristics of the copper material and the organic material. When the gate is bonded to the dielectric layer, the bonding force between the gate and the dielectric layer can be improved to avoid delamination, and the transistor embedded in the package substrate is electrically connected to the circuit structure. Effectively achieve the purpose of improving the bonding strength of the electrical connection structure.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

10, 10', 10"... semiconductor material

101, 101', 101"... source

102, 102', 102"... bungee

10a, 10a', 10a"... first surface

10b, 10b', 10b"... second surface

11, 11', 11"... dielectric layer

12, 12', 12"... gate

14, 14', 14"... substrate

20. . . Semiconductor material

20a. . . First surface

20b. . . Second surface

201, 201', 201"... source

202, 202', 202"... bungee

twenty one. . . Dielectric layer

22, 22', 22"... gate

twenty three. . . Metal layer

23a, 23a"...first metal layer

23b. . . Second metal layer

twenty four. . . Substrate

30. . . Semiconductor material

30a. . . First surface

30b. . . Second surface

301, 301', 301"... source

302, 302', 302"... bungee

31. . . Dielectric layer

31a. . . Third surface

31b. . . Fourth surface

32, 32', 32"... gate

33. . . Metal layer

33a, 33a"...first metal layer

33b. . . Second metal layer

34. . . Substrate

40. . . Semiconductor material

40a. . . First surface

40b. . . Second surface

401, 401', 401"... source

402, 402', 402"... bungee

41. . . Dielectric layer

41a. . . Third surface

41b. . . Fourth surface

42, 42', 42"... gate

43. . . Metal layer

43a, 43a"...first metal layer

43b. . . Second metal layer

44. . . Substrate

1A is a partial cross-sectional view showing a package substrate of a conventional gated organic thin film transistor;

1B and 1C are partial cross-sectional views of a package substrate of a conventional gated organic thin film transistor embedded therein;

2A to 2C are schematic cross-sectional views showing a first embodiment of the transistor device of the present invention; wherein, FIGS. 2B and 2C are schematic cross-sectional views of other embodiments;

3A to 3C are cross-sectional views showing a second embodiment of the transistor device of the present invention; wherein, FIGS. 3B and 3C are schematic cross-sectional views of other embodiments;

4A to 4C are schematic cross-sectional views showing a third embodiment of the transistor device of the present invention; wherein, FIGS. 4B and 4C are schematic cross-sectional views of other embodiments.

20. . . Semiconductor material

20a. . . First surface

20b. . . Second surface

201. . . Source

202. . . Bungee

twenty one. . . Dielectric layer

twenty two. . . Gate

twenty three. . . Metal layer

twenty four. . . Substrate

Claims (18)

A transistor device includes: a semiconductor material having a first surface and a second surface; a source and a drain are disposed on the first surface and embedded in the semiconductor material, and the source and the drain are formed The material is a copper material; the dielectric layer is disposed on the second surface of the semiconductor material; the gate is disposed on the dielectric layer and located at a position corresponding to the source and the drain, and The material forming the gate is a copper material; and the metal layer is disposed on the upper surface and the side surface of the gate. The transistor device according to claim 1, wherein the material forming the metal layer is a nickel/gold material. A transistor device includes: a semiconductor material having a first surface and a second surface; a source and a drain are disposed on the first surface and embedded in the semiconductor material, and the source and the drain are formed The material is nickel/palladium material, palladium/gold material, or gold material; the dielectric layer is disposed on the second surface of the semiconductor material; the gate is disposed on the dielectric layer and is located corresponding to a position between the source and the drain, and the material forming the gate is a nickel/palladium material, a palladium/gold material, or a gold material; and a first metal layer is disposed on the upper surface of the gate, and The material forming the first metal layer is a copper material. The transistor device of claim 3, further comprising a second metal layer disposed on the lower surface of the gate. The transistor device of claim 4, wherein the material forming the second metal layer is a copper material. The transistor device of claim 3, wherein the first metal layer is extended to a side surface of the gate. A transistor device includes: a semiconductor material having a first surface and a second surface; a source and a drain are disposed on the second surface, and the material forming the source and the drain is copper a dielectric layer is disposed on the first surface of the semiconductor material and has a third surface and a fourth surface, and the fourth surface is bonded to the first surface; the gate is disposed on the third surface And embedded in the dielectric layer, and located at a position corresponding to the source and the drain, and the material forming the gate is copper; and the metal layer is disposed on the upper surface and the side of the gate surface. The crystal device according to claim 7, wherein the material forming the metal layer is a nickel/gold material. A transistor device comprising: a semiconductor material having a first surface and a second surface; a source and a drain are disposed on the second surface, and the material forming the source and the drain is nickel/ a palladium material, a palladium/gold material, or a gold material; the dielectric layer is disposed on the first surface of the semiconductor material, and has a third surface and a fourth surface, and the fourth surface is bonded to the first surface a gate electrode is disposed on the third surface and embedded in the dielectric layer, and is located at a position corresponding to the source and the drain, and the material forming the gate is nickel/palladium material, palladium/ The gold material or the gold material; and the first metal layer are disposed on the upper surface of the gate, and the material forming the first metal layer is a copper material. The transistor device of claim 9, comprising a second metal layer disposed on a lower surface of the gate. The transistor device of claim 10, wherein the material forming the second metal layer is a copper material. The transistor device of claim 9, wherein the first metal layer is extended to a side surface of the gate. A transistor device includes: a semiconductor material having a first surface and a second surface; a source and a drain are disposed on the first surface and embedded in the semiconductor material, and the source and the drain are formed The material is a copper material; the dielectric layer is disposed on the first surface of the semiconductor material, and has a third surface and a fourth surface, and the fourth surface is bonded to the first surface; the gate is Provided on the third surface and embedded in the dielectric layer, and located at a position corresponding to the source and the drain, and the material forming the gate is copper; and the metal layer is disposed on the gate The upper surface and the side surface. The crystal device according to claim 13, wherein the material forming the metal layer is a nickel/gold material. A transistor device includes: a semiconductor material having a first surface and a second surface; a source and a drain are disposed on the first surface and embedded in the semiconductor material, and the source and the drain are formed The material is nickel/palladium material, palladium/gold material, or gold material; the dielectric layer is disposed on the first surface of the semiconductor material, and has a third surface and a fourth surface, and the fourth surface Bonded to the first surface; a gate is disposed on the third surface and embedded in the dielectric layer, and is located at a position corresponding to the source and the drain, and the material forming the gate is nickel a palladium material, a palladium/gold material, or a gold material; and a first metal layer disposed on the upper surface of the gate, and the material forming the first metal layer is a copper material. The transistor device of claim 15 further comprising a second metal layer disposed on a lower surface of the gate. The transistor device of claim 16, wherein the material forming the second metal layer is a copper material. The transistor device of claim 15, wherein the first metal layer is extended to a side surface of the gate.