TWI460838B - Semiconductor device - Google Patents

Description

Semiconductor structure

The present invention provides a semiconductor structure, and more particularly to a semiconductor structure having a germanium through electrode and a shield.

In the modern information society, the microprocessor system consisting of integrated circuits has been widely used in all aspects of life, such as automatic control of household appliances, mobile communication devices, personal computers, etc., all of which have traces of integrated circuits. . With the increasing advancement of technology and the imagination of human society for electronic products, the integrated circuit has also developed in the direction of more yuan, more precision and smaller.

Generally, an integrated circuit is formed by a die produced in a conventional semiconductor process. The process of fabricating a die begins with the production of a wafer: first, a plurality of regions are distinguished on a wafer, and in each region, through various semiconductor processes such as deposition, lithography, etching, or flattening. The steps to form various required circuit paths, and then, the respective regions on the wafer are cut into individual chips, packaged into chips, and finally the wafer is electrically connected to a circuit board. Such as a printed circuit board (PCB), after the chip is electrically connected to the pins of the printed circuit board, a variety of stylized processing can be performed.

In order to improve the function and performance of the wafer and increase the degree of integration to accommodate more semiconductor components in a limited space, the related manufacturers have developed a number of semiconductor wafer stacking technologies, including flip chip technology (Flip-Chip) technology, multi-chip package ( Multi-chip Package (MCP) technology, package on package (PoP) technology, package in package (PiP) technology, etc., can be increased by stacking wafers or packages between each other. The degree of integration of semiconductor components per unit volume. Under the above various package architectures, in recent years, a technology called a through silicon via (TSV) technology has been developed to facilitate internal interconnection of wafers in a package to improve stacking efficiency. Further advancement.

The principle of the through electrode is to form a via (Via) in the wafer by etching or laser, and then fill a via hole with a conductive material such as copper, polysilicon, tungsten, etc., and finally thin the wafer or the grain and Stacked and bonded to form a 3D solid crystal grain stack structure. Since the connection path of the internal lines of each chip applied to the through-electrode technology is the shortest, compared with other stacking technologies, the transmission speed between the wafers is faster, the noise is smaller, and the performance is better, which is one of the currently promising technologies. .

Please refer to FIG. 1 , which is a schematic diagram of a conventional die stack with a through electrode. The die 1 has a substrate 11 on the substrate 11 and includes a plurality of metal interconnect layers 13 for connecting the active or passive components (not shown) inside the die 1 up and down or left and right, and electrically connecting one contact upward. Pad 15. The inside of the substrate 11 includes a plurality of through electrodes 14 , each of which penetrates the substrate 11 , is electrically connected to the metal interconnect layer 13 , and is electrically connected to a solder ball 16 .

The die 2 includes a substrate 21, a plurality of metal interconnect layers 23, a plurality of turn-on electrodes 24, a plurality of contact pads 25, and a plurality of solder balls 26, the positions and connections of the elements being the same as those of the die 1. . When the crystal grains 1 and 2 are stacked, the solder balls 26 of the crystal grains 2 are electrically in contact with the contact pads 15 of the crystal grains 1 so that the crystal grains 1 and the crystal grains 2 can be electrically connected up and down and form a stable stack. structure. Of course, the die 1 can also be connected downward through a solder ball 16 to a package substrate or a circuit board (not shown) to provide external power or signal output/input. Similarly, the die 2 can also be contacted with other dies (not shown) through its contact pads 25, and then stacked in multiple layers.

Please refer to FIG. 2, which is a cross-sectional view of a conventional crystal having a through electrode. The die 1 includes a substrate 11, a plurality of metal interconnect layers 13, a plurality of via electrodes 14, a power transmission layer 18, and a contact pad 15. A plurality of metal interconnect layers 13 are located on the substrate 11 for joining the active or passive components inside the die 1 up and down or left and right. Each of the through electrodes 14 penetrates through the substrate 11 and is electrically connected to the metal interconnect layer 13 upwardly, and is open to the bottom surface of the substrate 11. The external signal is transmitted through the through electrode 14 to be electrically connected to the wafer 1. Metal interconnect layer 13.

In the area A of Fig. 2, a circuit area 17 is also included. The circuit region 17 is connected to the metal interconnect layer 13 and contains various active components such as a transistor, a memory or various passive components such as an inductor, a resistor, etc., and various kinds of stylized processes can be performed. The through-electrode 14 shown in the area A is a signal pin, so that the through-electrode 14 receives the external signal, first enters the circuit area 17 via the metal interconnect layer 13, and passes through the circuit. After the semiconductor element in the region 17 reacts, it is transferred to the other metal interconnect layer 13 to complete the stylization process.

In the region B, the illustrated through electrode 14 is a power pin for supplying power to components of the die 1. Therefore, with respect to the signal pin of the foregoing area A, the through electrode 14 is often required to transmit a large current as the power pin. Therefore, in order to ensure the transmission efficiency, a power distribution layer 18 having a small resistance and a thick thickness is required to be arranged. Above the pellet 1, the tantalum through electrode 14 is coupled to the power transport layer 18 by transmission of the lower to upper metal interconnect layer 13 to provide an intra die power distribution.

However, since the through electrode 14 of the region B serves as a power pin, the current flowing through the through electrode 14 and the metal interconnect layer 13 in the region B is large, and is relatively easy to be disposed on other circuits provided around the periphery. (For example, the metal interconnect layer 13 and the circuit region 17 of the region A) generate electromagnetic interference and electromagnetic interference (EMI), which affects its normal operation, and this is a problem that needs to be solved and overcome.

Therefore, it is necessary to provide a suitable semiconductor structure, which can effectively block the problem that the conventional through-electrode 14 causes noise to surrounding circuit components when transmitting power.

The present invention provides a semiconductor structure, and more particularly to a semiconductor structure having a germanium through electrode and a shield.

In accordance with the scope of the present invention, the present invention discloses a semiconductor structure including a substrate, a circuit region, at least one through electrode, and a shield. The circuit region and the 矽 through electrode are disposed on the substrate, and the 矽 penetrates the electrode through the substrate. The shielding member is disposed on the substrate and at least a portion is located between the shielding member and the meandering through electrode for shielding the circuit region from the meandering through electrode.

According to the present invention, since the shield member is provided between the through electrode and the circuit region, it is possible to effectively prevent the problem that the conventional through-electrode causes noise to the surrounding circuit components when the power is transmitted.

As described in the text for the relative relationship between the relative elements in the figure, it should be understood by those skilled in the art that it refers to the relative position of the object, and therefore can be flipped to present the same member, which should belong to the same specification. The scope of the disclosure is hereby stated.

Please refer to FIG. 3 first, and FIG. 3 is a schematic view of the semiconductor structure of the present invention. The semiconductor structure 3 of the present invention comprises a substrate 31, at least one via electrode 34, a plurality of metal interconnect layers 33, and a circuit region 331. The material of the substrate 31 may be monocrystalline silicon, gallium arsenide (GaAs) or other semiconductor materials well known in the art. The through electrode 34 is located in the substrate 31 and penetrates the substrate 31. The material is usually a conductor such as copper, polysilicon, tungsten or aluminum, and has an insulating layer 341 on the periphery thereof to ensure that there is no leakage when the power signal is transmitted. The plurality of metal interconnect layers 33 are located on the substrate 31 and include a shield 332 and a connection circuit 333. The connection circuit 333 includes a plurality of metal circuit layers and a plurality of through holes, and is electrically connected to the through electrodes 34 and a power output/input pad 35. The power input/output pad 35 is located on the substrate 31. In the preferred embodiment of the present invention, it is mounted on the connection circuit 333, and includes a thicker power transmission layer 351 for transmitting power to the entire area of the chip. It may contain conductive materials such as copper and aluminum. Therefore, the external power source (arrow A) passes through the through-electrode 34 and passes through the connection circuit 333 from bottom to top to the power transmission layer 351 to provide distribution of power inside the wafer. In addition, the power input/output pad 35 further includes a contact pad 352 located above the power transmission layer 351, and the material thereof may include a conductive material such as aluminum or copper. As shown in FIGS. 1 and 3, the contact pads 352 can be electrically connected to another wafer (not shown) stacked thereon when the wafers are stacked.

The semiconductor structure of the present invention further includes a circuit region 331 containing various active components such as transistors, memories or various passive components such as inductors, resistors, etc., and various kinds of stylized processes can be performed. Since the through electrode 34 as the power pin passes through the external power source (arrow A), a large amount of current is transmitted to the power input/output pad 35 via the connection circuit 333, and strong electromagnetic interference (EMI) is generated. Interference noise is generated to a semiconductor element located in the vicinity of the through electrode 34, such as the circuit region 331. The semiconductor structure of the present invention therefore also includes a shield 332 to substantially alleviate this problem. The shielding member 332 is disposed in the plurality of metal inner wiring layers 33, and the uppermost end of the shielding member 332 is higher than the crucible through electrode 34. In the preferred embodiment of the present invention, the shielding member 332 is disposed on the connecting circuit 333 and the crucible. The periphery of the through electrode 34 may of course be provided only on the periphery of the connection circuit 333 or only on the periphery of the through electrode 34. In this way, the shielding member 332 can effectively shield the generation of the coupling noise from the large amount of current flowing through the bypass electrode 34 or the connection circuit 333. The material of the shielding member 32 is generally selected from the group consisting of copper, aluminum, tungsten, titanium, titanium nitride, tantalum and tantalum nitride, and the product structure design is integrated with the semiconductor process. It depends on compatibility, but not limited to the above.

In another embodiment of the present invention, the through electrode 34 may be directly connected to the power input/output pad 35 through the connection circuit 333. As shown in FIG. 4, the power transmission (arrow A) may directly pass through the port. The through electrode 34 is directly connected to the power input/output pad 35 for current transmission, and the shield 332 is disposed on the periphery of the 矽 through electrode 34, and the shielding effect can also be achieved.

In still another embodiment of the present invention, the shield member 332 can be disposed on the periphery of the circuit region 331. As shown in FIG. 5, the circuit region 331 can also be prevented from being disturbed by the through electrode 34 and the connection circuit 333.

Regarding the shape and arrangement of the shield 332 of the present invention, please refer to Figs. 6 to 10. 6 to 7 are cross-sectional views drawn in accordance with the position of the tangent I in Fig. 3; and Figs. 8 to 10 are cross-sectional views drawn in accordance with the tangent J in Fig. 3. The tangent line I and the tangent line J respectively correspond to the cross section of the metal circuit layer and the through hole portion of the connection circuit 333.

As can be clearly seen from the cross-sectional view, the shield member 332 of the present invention may be a continuous metal ring pattern or a discrete metal block pattern. As shown in FIG. 6, the shield member 332 includes at least one continuous metal ring layer. Further, as shown in Fig. 7, the shield 332 includes at least one discrete, discontinuous metal block layer. Similarly, if the cross section of the connection circuit 333 is a via, that is, a position of the tangent J, the shield 332 may also include at least one continuous metal ring layer, as shown in FIG. 8, or include a discrete, no A continuous metal block layer as shown in Figure 9.

Regarding the shape surrounded by the shield 332, please refer to Figs. 8 and 10. In general, the shield 332 of the present invention comprises at least one polygonal metal layer. In one embodiment of the present invention, the shield 332 includes at least one octagonal metal layer, as shown in FIG. 8; and in another embodiment of the present invention, the shield 332 includes at least one circular metal layer. As shown in Figure 10.

Therefore, the embodiment of the shield 332 is not limited to the above embodiment, but should include various combinations of "continuous-discrete" and "polygonal" structures, and a good shielding effect can be obtained. In addition, the shield member 332 of the present invention is not limited to the structure of a single layer, but may include a plurality of layers of the shield structure. As shown in Fig. 11, it is exemplified as a shield structure having a plurality of layers. The shielding structure of the present invention comprises a first shielding member 3322 and a second shielding member 3323. The first shielding member 3322 is a continuous octagonal metal layer, and the second shielding member 3323 is a discrete circular metal layer. Of course, the third shielding member (not shown) may be further included as the case may be. The fourth shielding member (not shown) is combined with a plurality of shielding members 332 to obtain a good shielding effect. Of course, the structure of each shielding member 332 can also be a combination of various continuous discontinuities and patterns of various polygons.

In addition, the present invention utilizes various metal interconnect processes, such as an aluminum process, a via plug process, a copper damascene process, etc., and adjusts the formed plurality of metal circuit layers and a plurality of connections. Various metals The layout position of the vias of the layer can be effectively integrated into the current semiconductor process, and in the metal interconnection process, the required shield 332 and the connection circuit 333 are simultaneously formed. The layout pattern of the shield 332 and the connection circuit 333 is not limited to the above-described continuous or discontinuous annular pattern, block pattern, polygonal pattern, etc., single layer or multi-layer pattern, and the shield member 332 of the present invention is disposed in the through-hole The periphery of the electrode 34, the connection circuit 333 or the circuit region 331 can effectively shield the electromagnetic interference (EMI) generated when the through electrode 34 transmits power to the connection circuit, thereby avoiding affecting the circuit region 331.

In addition, in order to enhance the shielding effect of the shield member 332, the shield member 332 of the present invention can be further connected to a signal ground 3321, as shown in FIG. This signal ground 3321 can be connected to the most stable ground, such as ground or chip group level grounding of a system board (not shown) mounted with a semiconductor package to more efficiently avoid noise. Furthermore, a high frequency filter can be additionally provided between the ground of the system board to selectively avoid and remove high frequency noise.

In summary, the semiconductor device of the present invention includes a shield member 332 disposed on the periphery of the through electrode 34 or the connection circuit 333 and having a signal ground 3321, so that the conventional through electrode 34 can be effectively blocked from the connection circuit. When transmitting power, it causes noise problems to surrounding circuit components (such as circuit area 331).

The above description is only a preferred embodiment of the present invention, and the application according to the present invention is Equivalent changes and modifications made by the scope of the invention are intended to be within the scope of the invention.

1,2‧‧‧ grain

11,21‧‧‧Base

13,23‧‧‧Metal interconnect layer

14,24‧‧‧矽through electrode

15,25‧‧‧Contact pads

16,26‧‧‧ solder balls

17‧‧‧Circuit area

18‧‧‧Power transmission layer

3‧‧‧Semiconductor structure

31‧‧‧Base

33‧‧‧Metal interconnect layer

331‧‧‧Circuit area

332‧‧‧Shield

3321‧‧‧Signal grounding

3322‧‧‧First shield

3323‧‧‧second shield

333‧‧‧Connected circuit

34‧‧‧矽through electrode

341‧‧‧Insulation

35‧‧‧Power input/output pad

351‧‧‧Power transmission layer

352‧‧‧Contact pads

FIG. 1 is a schematic view of a conventional die stack having a through electrode.

Fig. 2 is a cross-sectional view of a conventional crystal having a through electrode.

Figure 3 is a schematic view showing the structure of a semiconductor in the present invention.

4 and 5 are another embodiment of the semiconductor structure of the present invention.

6 to 11 are schematic views of a semiconductor structure shield in the present invention.

3. . . Semiconductor structure

31. . . Base

33. . . Metal interconnect layer

331. . . Circuit area

332. . . Shield

3321. . . Signal ground

333. . . Connecting circuit

34. . .矽through electrode

341. . . Insulation

35. . . Power input/output pad

351. . . Power transmission layer

352. . . Contact pad

Claims (20)

A semiconductor structure comprising: a substrate; a circuit region disposed on the substrate; at least one through electrode extending through the substrate and located adjacent to the circuit region; a first shielding member disposed on the substrate and at least a portion Located between the circuit region and the meandering through electrode, wherein the uppermost end of the first shield is higher than the meandering electrode. The semiconductor structure of claim 1, further comprising a power output/input pad disposed on the substrate, wherein the through-electrode is electrically connected to the power output/input pad. The semiconductor structure of claim 2, further comprising a plurality of metal interconnect layers, wherein the metal interconnect layers comprise: a first metal interconnect to form the first shield; and a first The two metal interconnects form a connection circuit for electrically connecting the turn-on electrode and the power output/input pad. The semiconductor structure of claim 3, wherein the first shield is disposed on a periphery of the connecting circuit. The semiconductor structure of claim 1, wherein the first shield comprises a polygonal metal layer. The semiconductor structure of claim 5, wherein the first shield comprises an octagonal metal layer. The semiconductor structure of claim 5, wherein the first shield comprises a circular metal layer. The semiconductor structure of claim 1, wherein the first shield comprises a continuous metal layer. The semiconductor structure of claim 1, wherein the first shield comprises a discrete metal layer. The semiconductor structure of claim 1, further comprising at least one second shield, each of the second shields surrounding the first shield. The semiconductor structure of claim 10, wherein at least one of the second shields comprises a polygonal metal layer. The semiconductor structure of claim 11, wherein at least one of the second shields comprises an octagonal metal layer. The semiconductor structure of claim 11, wherein at least one of the second shields comprises a circular metal layer. The semiconductor structure of claim 10, wherein at least one of the second shields comprises a continuous metal layer. The semiconductor structure of claim 10, wherein at least one of the second shields comprises a discrete metal layer. The semiconductor structure of claim 1, wherein the first shield is selected from the group consisting of copper, aluminum, tungsten, titanium, titanium nitride, tantalum, and tantalum nitride. The semiconductor structure of claim 10, wherein the second shield is selected from the group consisting of copper, aluminum, tungsten, titanium, titanium nitride, tantalum, and tantalum nitride. The semiconductor structure of claim 1, wherein the through electrode is electrically connected to a power source. The semiconductor structure of claim 1, wherein the first shield is electrically connected to a signal ground. The semiconductor structure of claim 10, wherein the second shield is electrically connected to a signal ground.