201023323 六、發明說明： 【發明所屬之技術領域】 本發明提供-種半導體結構，特別是—種具有石夕貫通電 極與屏蔽件的半導體結構。 【先前技術】 在現代的資訊社會中，由積體電路所構成的微處理機系 統早已被普遍運用於生活的各個層面，例如自動控制之家電 用品、行動通訊設備、個人電腦等，都有積體電路之蹤跡。 而隨著科技的日益精進，以及人類社會對於電子產品的各種 想像，使得積體電路也往更多元、更精密、更小型的方向發 展。 一般所謂積體電路，是透過習知半導體製程中所生產的 ❹晶粒(die)而形成。製造晶粒的過程，係由生產一晶圓（wafer) 開始：首先，在一片晶圓上區分出多個區域，並在每個區域 上，透過各種半導體製程如沈積、微影、蝕刻或平坦化步驟， 以形成各種所需之電路路線，接著，再對晶圓上的各個區域 進行切割而成各個晶粒，並加以封裝成晶片（chip)，最後再 將晶片電連至一電路板，如一印刷電路板(printed circuit board，PCB) ’使晶片與印刷電路板的接腳印⑻電性連結後， 便可執行各種程式化之處理。 4 201023323 為了提高晶片功能與效能，增加積集度以便在有限空間 下能容納更多半導體元件，相關廠商開發出許多半導體晶片 的堆疊技術，包括了覆晶封裝（Flip-chip)技術、多晶片封裝 (Multi-chip Package，MCP)技術、封裝堆疊（package 〇n Package，PoP)技術、封裝内藏封裝體(packagepip) 技術等，都可以藉由晶片或封裝體之間彼此的堆叠來增加單 ❿位體積内半導體元件的積集度。而在上述各種封裝架構下， 近年來又發展一種稱為石夕貫通電極(Through siH_ via，TSV) 之技術’可促進在封裝體中夂 姐甲各晶片彼此之間的内部連結 .(WnneetWx將堆纽率進—步往上提升。 石夕貫通電極原理是在晶圓 通孔(Via)，再將導電材料如鋼、多晶石夕、鶴等填人=成最 後則將晶圓或晶粒薄化並加以 ❹3D立體之晶粒堆叠結構。隹疊、咖㈣，而成為 片内部線路之連結路徑最短，相應用;;貫通電極技術之各晶 片間的傳輸速度更快、雜乂、其他堆疊技術，可使晶 好的技術之-。雜訊更小、效能更佳，是目前遠景看 請參考第1圖，第1阁* 疊示意圖。晶粒i具有一久：具有矽貫通電極之晶粒堆 複數層金屬内連線層13, ^ 於基底11之上包含有 上下或左右連結晶粒1内部之 201023323 主動或被動元件（未顯示），並向上電連接一揍觸墊15。基 底11内部則包含複數個矽貫通電極14,每個矽貫通電極14 係貫穿基底11，向上電性連結於金屬内連線層13，向下則 電性連結一錫球16。 晶粒2則包含有一基底21、複數層金屬内連線層23、 複數個矽貫通電極24、複數個接觸墊25以及複數個錫球 26，其各元件的位置與連結關係與晶粒1相同。在晶粒1、2 進行堆疊時，晶粒2之錫球26係向下電性接觸晶粒1的接 觸墊15，使得晶粒1與晶粒2可上下導通連結，並形成一穩 固之堆疊結構。當然，晶粒1還可以透過錫球16向下連結 一封裝底板或一電路板（未顯示），藉以提供外部電力或訊 號之輸出/輸入。同樣地，晶粒2上方還可透過其接觸墊25 而接觸其他晶粒（未顯示），再進行多層之堆疊。 © 請參考第2圖，第2圖為習知具有矽貫通電極之晶粒剖 面圖。晶粒1包含有一基底11_、複數層金屬内連線層13、 複數個矽貫通電極14、一電力傳輸層18以及一接觸墊15。 複數層金屬内連線層13位於基底11上，用以上下或左右連 結晶粒1内部之主動或被動元件。每個矽貫通電極14係貫 穿基底11，向上電性連結於金屬内連線層13，向下則開口 於基底11之一底表面；外部訊號透過矽貫通電極14，可向 上導通至晶片1之金屬内連線層13。 201023323 還包含有一雷％ 17與金屬内連線層13連結，且人 电路區17。電路1 體,、記憶體或各種被動元件如電感3 各種主動元件如電 程式化之處理。在區域A所繪示 電阻等，而可執行各: 號接腳(signal pin) ’使得此矽貫'通^貫通電极14係為 Ο201023323 VI. Description of the Invention: [Technical Field] The present invention provides a semiconductor structure, particularly a semiconductor structure having a day-to-earth electrode and a shield. [Prior Art] In the modern information society, the microprocessor system consisting of integrated circuits has been widely used in all aspects of life, such as automatic control of household appliances, mobile communication devices, personal computers, etc. Trace of the body circuit. With the increasing advancement of technology and the imagination of human society for electronic products, the integrated circuit has also developed in more directions, more precision and smaller. Generally, an integrated circuit is formed by a germanium die produced in a conventional semiconductor process. The process of making a grain begins with the production of a wafer: first, a plurality of regions are distinguished on a wafer, and in each region, through various semiconductor processes such as deposition, lithography, etching, or flattening. The steps are to form various required circuit paths, and then each region on the wafer is diced into individual dies, packaged into chips, and finally the wafer is electrically connected to a circuit board. If a printed circuit board (PCB) is used to electrically connect the chip to the printed circuit board's footprint (8), various stylized processing can be performed. 4 201023323 In order to improve the function and performance of the wafer and increase the degree of integration to accommodate more semiconductor components in a limited space, manufacturers have developed a number of semiconductor wafer stacking technologies, including flip chip technology (Flip-chip) technology, multi-chip Multi-chip Package (MCP) technology, package 〇n Package (PoP) technology, package-incorporated package (packagepip) technology, etc., can be added by stacking wafers or packages between each other. The degree of integration of semiconductor components within the clamp volume. Under the above various package architectures, in recent years, a technology called "Through SiH_via" (TSV) has been developed to promote the internal connection between the wafers in the package. (WnneetWx will The stacking rate is stepped up. The principle of the Shixi through electrode is in the via hole (Via), and then the conductive materials such as steel, polycrystalline stone, crane, etc. are filled = the final wafer or grain Thinning and ❹ 3D three-dimensional crystal stacking structure. Folding, coffee (four), and the shortest connection path of the internal wiring of the film, phase application;; the transmission speed between the wafers through the electrode technology is faster, miscellaneous, other stacking The technology can make crystal technology better. The noise is smaller and the performance is better. For the current perspective, please refer to Figure 1, the first cabinet* stack diagram. The grain i has a long time: the grain with the through electrode A plurality of layers of metal interconnect layers 13 are formed on the substrate 11 including 201023323 active or passive components (not shown) that connect the inside of the die 1 up and down or left and right, and electrically connect a contact pad 15 upward. Including a plurality of 矽 through electricity 14. Each of the through electrodes 14 penetrates the substrate 11 and is electrically connected to the metal interconnect layer 13 and electrically connected to a solder ball 16. The die 2 includes a substrate 21 and a plurality of metal interconnects. The line layer 23, the plurality of 矽 through electrodes 24, the plurality of contact pads 25, and the plurality of solder balls 26 have the same position and connection relationship as the crystal grains 1. When the crystal grains 1 and 2 are stacked, the crystal grains 2 are formed. The solder ball 26 is electrically in contact with the contact pad 15 of the die 1 so that the die 1 and the die 2 can be electrically connected up and down and form a stable stacked structure. Of course, the die 1 can also pass through the solder ball 16 A package bottom plate or a circuit board (not shown) is connected downward to provide external power or signal output/input. Similarly, the die 2 can also contact other pads (not shown) through the contact pads 25, Then carry out multi-layer stacking. © Please refer to Fig. 2, which is a cross-sectional view of a conventional die having a through-electrode. The die 1 includes a substrate 11_, a plurality of metal interconnect layers 13, and a plurality of turns. The electrode 14, a power transmission layer 18 and a contact pad 15. The plurality of metal interconnect layers 13 are located on the substrate 11 for connecting the active or passive components inside the die 1 up and down or left and right. Each of the through electrodes 14 penetrates the substrate 11 and is electrically connected upward to the metal interconnect layer. 13. The bottom surface is open to the bottom surface of the substrate 11. The external signal is transmitted through the through electrode 14 to be electrically connected to the metal interconnect layer 13 of the wafer 1. The 201023323 further includes a Ray 17 and a metal interconnect layer 13 Connected, and human circuit area 17. Circuit 1 body, memory or various passive components such as inductor 3 various active components such as electronic programming. In the area A, the resistors are drawn, and each: pin can be executed ( Signal pin) 'Make this pass through the through electrode 14
後’先經由金屬内連線層13進入電路區 14接受到外部訊號 内部半導體元件產生反應後，再傳輪品17 ’並經電路區 13’而完成程式化之處理。 、他之金屬内連線, 而在區域Β中，所繪示㈣貫通電極 腳(power pin)，係用以提供晶粒丨各部位_ 、為一電力接 相對於前述區域A之訊號接腳，作為電力接^卩之電力。因此’ 14常需傳輸較大電流，因此為確保傳輸效率， 較小、較厚之電源分配層18於晶粒1之上部，梦^通電^ 14藉由下到上金屬内連線層13的傳輸連結至電力傳輸層 18，以長：供晶片内部電力之分布（intra p〇wer distribution) ° 但是，由於區域B之矽貫通電極14係作為一電力接腳， 因此區域B之矽貫通電極14與金屬内連線層13流通之電流 流量較大’相對的，容易對設置於四周的其他電路（如區域 A之金屬内連線層π與電路區17)產生電磁效應之干擾與 201023323 雜訊（electromagnetic interference，EMI)，而影響其正常運 作，而這是一個需要解決與克服的問題。 因此，需提供一適當之半導體結構，能有效阻絕習知矽 貫通電極14於傳輸電力時，對周遭之電路元件造成雜訊之 問題。 【發明内容】 ® 本發明提供一種半導體結構，特別是一種具有矽貫通電 極與屏蔽件的半導體結構。 根據本發明之申請專利範圍，本發明係揭露一種半導體 結構，其包含有一基底、一電路區、至少一矽貫通電極以及 一屏蔽件。電路區與矽貫穿電極皆設置於基底上，且矽貫穿 電極貫穿基底。屏蔽件設置於該基底上且至少一部分位於該 ❹屏蔽件與該矽貫穿電極之間，用以屏蔽該電路區與該矽貫通 電極。 ， 本發明由於在矽貫通電極與電路區之間具有屏蔽件，故 能有效阻絕習知矽貫通電極於傳輸電力時，對周遭之電路元 件造成雜訊之問題。 【實施方式】 8 201023323 •人比!^述對於圖形中相對元件之上下關係，在本領 白應此理解其係指物件之相對位置而言，因此皆可以 翻轉呈見相同之構件，此皆應同屬本說明書所揭露之範 圍，在此容先敘明。 。月先參考第3圖’第3圖為本發明之半導體結構示意 圖。本發明之半導體結構3包含有-基底3卜至少-石夕貫通 ❹電極34、複數層金屬内連線層33以及一電路區331。基底 31的材質可為單晶矽（m〇n〇crystalline silic〇n)、砷化鎵 (gallium arsenide, GaAs)或其他習知技藝所熟知之半導體材 質。矽貫通電極34位於基底31之中並貫穿基底31，其材質 通常為銅、多晶矽、鎢、鋁等導體，其外圍並具有一絕緣層 341，以確保電力訊號傳輸時不會有漏電的情況。複數層金 屬内連線層33位於基底31上，包含有一屏蔽件332以及一 連接電路333。連接電路333包含有複數層金屬線路層以及 複數個通孔，並電連接矽貫通電極34與一電源輸出/輸入墊 35。電源輸入/輸出塾35位於基底31上，在本發明之較佳實 施例中’係架設於連接電路333之上，其包含有一較厚之電 力傳輸層351，負責傳輸電力至晶片之各處，其可包含有銅、 銘等導電材質。因此，外部之電源（箭頭A)透過矽貫通電 極34 ’由下到上通過連接電路333而至電力傳輸層351，以 提供晶片内部電力之分布。另外，電源輸入/輸出墊35還包 含一接觸墊352，位於電力傳輸層351之上方，其材質可包 9 201023323 含習知之鋁、銅等導電材質。如第i圖與第 牛j圖所不，接觸 墊352可於晶片堆疊時，再將電力傳輸至堆疊於上之另一日 片（未顯示）形成電連接。 曰曰 ❹ ❹ 本發明之半導體結構還包含一電路區331，内含有各種 主動元件如電晶體、記憶體或各種被動元件如電感、電阻種 等，而可執行各種程式化之處理。由於作為電力接腳之^貫 通電極34,經由外部電源（箭頭A)，將大量電流經由連接 電路333傳至電源輸入/輸出墊35時，會產生強大的電磁干 擾(electromagnetic imerference，ΕΜΙ)，而對位於矽貫通電極 34附近的半導體元件如電路區331產生干擾雜訊。因此本發 明之半導體結構還包含有-屏蔽件332，以徹底改善此問 題。屏蔽件332設置於複數層金屬内連線層33中在本發 明之較佳實施例中，屏蔽件332係設置於連接電路如與石夕 貫通電極34之外圍，t然，也可僅設置於連接電路333之 外圍，或僅石夕貫通電極34之外圍。如此一來，屏蔽件说 對於所包圍之碎貫通電極34或連接電路333所流通之大量 電流，便能夠有效屏蔽其耗合雜訊之產生。上述屏蔽件32 之材質，-般而言係可選自於由銅、鋁、鎢、鈦、氮化鈦、 组以及氮驗職心馳，職產品㈣設計與半導體製 程之整合的相容性Μ,但不以上述為限。 而在本心明之另一實施例中，石夕貫通電極Μ也可毋需 201023323 透過連接電路333而直接連結電源輸入/輸出墊35，如第4 圖所示，電力傳輸（箭頭A)可直接經由矽貫通電極34直 接連結至電源輸入/輸出墊35,進行電流的傳輪，屏蔽件332 則設置在矽貫穿電極34之外圍，同樣也可達成屏蔽的效果。 而在本發明之又一實施例中，屏蔽件332可設置在電路 區331之外圍，如第5圖所示，同樣可以避免電路區331受 q 到矽貫通電極34與連接電路333之干擾。 關於本發明之屏蔽件332的形狀與排列，請參考第6圖 至第10圖。其中第6圖至第7圖為依照第3圖之切線I位 置所繪製之剖面圖；而第8圖至第1〇圖則為依照第3圖之 切線J所繪製之剖面圖。切線1與切線j分別對應連接電路 333之金屬線路層與通孔部位之剖面。 ❹ 從剖面圖可以清楚看出，本發明之屏蔽件332可為連續 之金屬環圖形，亦可為離散金屬塊圖形，如第6圖所繪示， 屏蔽件332包含至少一連續之金屬環層，另外如第7圖所 示屏蔽件332包含至少一離散、不連續之金屬塊層。同樣 的，若連接電路333之剖面為通孔(via)，也就是切線^之位 置屏蔽件332也可以包含至少一連續之金屬環層，如第8 圖所示，或包含一離散、不連續之金屬塊層，如第9圖所示。 11 201023323 而關於屏蔽件332包圍的形狀，請參考第8圖與第ι〇 圖。一般而言’本發明之屏蔽件332包含至少 :二本發明之一實施例中，屏蔽件332包含至少 ^圖所示；而於本發明之另—實施例，屏蔽件 則包3至少—圓形金屬層，如第10圖所示。 ❹ 2，屏蔽件332之實施方式並不拘於上述實施例，而 =二各種連續，散」與「多邊形」結構之排列組合， 白可得，好之屏蔽效果。此外，本發明之屏蔽件332亦不 偈限於早層之結構，而可包含複數層H结構4第U 2示，所例示為-具有多層之屏蔽結構。本發明之屏蔽結 構L含有-第一屏蔽件3322與一第二屏蔽件助。其中第 -屏蔽件3322係為一連續之八邊型金屬層，而第二屏蔽件 助係為-離散之圓形金屬層，當然，還可視情況而進一步 包含第三屏蔽件（未顯示）或第四屏蔽件（未顯示），並藉 由複數個屏蔽件332的組合搭配而得到良好的屏蔽效果。當 然，各屏蔽件332之結構亦可為各種連續不連續，及各種多 邊形所呈現圖樣之排列組合。 此外，本發明係利用各種金屬内連線製程，例如鋁製 程、通孔插塞(via plug)製程、銅鑲嵌(Cu damascene)等製程， 並調整所形成之複數層金屬線路層以及複數個連接各金屬 層之通孔的佈局位置，即可有效整合於現行之半導體製程， 12 201023323After that, the metal interconnect layer 13 enters the circuit region 14 to receive the external signal. After the internal semiconductor device reacts, the wheel product 17' is transferred and the program is processed through the circuit region 13'. The metal is connected to the wire, and in the area, the (four) through-pin (power) is used to provide the die _, the power pin is connected to the signal pin of the area A. As the power of electricity. Therefore, '14 often needs to transmit a large current, so to ensure transmission efficiency, a small, thick power distribution layer 18 is on the upper part of the die 1, and the power is applied through the lower-to-up metal interconnect layer 13. The transmission is connected to the power transmission layer 18 to be long: for the internal power distribution of the wafer. However, since the through electrode 14 of the region B serves as a power pin, the region B passes through the electrode 14 The current flow rate with the metal interconnect layer 13 is relatively large, and it is easy to interfere with electromagnetic effects generated by other circuits disposed around the periphery (such as the metal interconnect layer π of the region A and the circuit region 17) and 201023323. (electromagnetic interference, EMI), which affects its normal operation, and this is a problem that needs to be solved and overcome. Therefore, it is necessary to provide a suitable semiconductor structure, which can effectively prevent the conventional 矽 through electrode 14 from causing noise to the surrounding circuit components when transmitting power. SUMMARY OF THE INVENTION The present invention provides a semiconductor structure, particularly a semiconductor structure having a germanium through electrode and a shield. In accordance with the scope of the present invention, the present invention discloses a semiconductor structure including a substrate, a circuit region, at least one through electrode, and a shield. The circuit region and the 矽 through electrode are disposed on the substrate, and the 矽 penetrates the electrode through the substrate. A shield is disposed on the substrate and at least a portion is located between the ❹ shield and the 矽 through electrode for shielding the circuit region from the 矽 through electrode. According to the present invention, since the shield member is provided between the through electrode and the circuit region, it is possible to effectively prevent the problem that the conventional through-electrode causes noise to the surrounding circuit components when the power is transmitted. [Embodiment] 8 201023323 • People ratio! ^ For the upper and lower relationship of the relative elements in the figure, it should be understood that it refers to the relative position of the object, so it can be flipped to see the same component, which should be The scope of the same disclosure is hereby incorporated by reference. . Referring to Fig. 3, Fig. 3 is a schematic view of a semiconductor structure of the present invention. The semiconductor structure 3 of the present invention comprises a substrate 3, at least a lithium through electrode 34, a plurality of metal interconnect layers 33, and a circuit region 331. The material of the substrate 31 may be a single crystal germanium, gallium arsenide (GaAs) or other semiconductor materials well known in the art. The through electrode 34 is located in the substrate 31 and penetrates the substrate 31. The material is usually copper, polysilicon, tungsten, aluminum or the like, and has an insulating layer 341 on the periphery thereof to ensure that there is no leakage when the power signal is transmitted. The plurality of metal interconnect layers 33 are located on the substrate 31 and include a shield 332 and a connection circuit 333. The connecting circuit 333 includes a plurality of metal wiring layers and a plurality of through holes, and is electrically connected to the through electrodes 34 and a power output/input pad 35. The power input/output port 35 is located on the substrate 31. In the preferred embodiment of the present invention, the system is mounted on the connection circuit 333 and includes a thicker power transmission layer 351 for transmitting power to the entire area of the chip. It can contain conductive materials such as copper and Ming. Therefore, an external power source (arrow A) is passed through the connection transistor 333 from the bottom through the 矽 through electrode 34' to the power transmission layer 351 to provide distribution of power inside the wafer. In addition, the power input/output pad 35 further includes a contact pad 352, which is located above the power transmission layer 351 and can be made of a material such as aluminum or copper. As shown in Fig. i and Fig. 7, the contact pads 352 can be electrically connected to another wafer (not shown) stacked on the wafer when the wafers are stacked.半导体 ❹ 半导体 The semiconductor structure of the present invention further includes a circuit region 331 containing various active components such as transistors, memories or various passive components such as inductors, resistors, etc., and various kinds of stylized processes can be performed. Since the through electrode 34 as the power pin transmits a large amount of current to the power input/output pad 35 via the connection circuit 333 via the external power source (arrow A), strong electromagnetic interference (ΕΜΙ) is generated, and Interference noise is generated to a semiconductor element located in the vicinity of the through electrode 34, such as the circuit region 331. The semiconductor structure of the present invention therefore also includes a shield 332 to substantially alleviate this problem. The shielding member 332 is disposed in the plurality of metal interconnecting layers 33. In the preferred embodiment of the present invention, the shielding member 332 is disposed on the periphery of the connecting circuit, such as the outer electrode 34, or may be disposed only on the periphery of the connecting electrode 34. The periphery of the connection circuit 333, or only the periphery of the electrode 34. In this way, the shielding member can effectively shield the generation of the noise due to the large amount of current flowing through the broken through electrode 34 or the connecting circuit 333. The material of the shielding member 32 is generally selected from the compatibility of copper, aluminum, tungsten, titanium, titanium nitride, group and nitrogen, and the integration of the product (4) design and the semiconductor process. Oh, but not limited to the above. In another embodiment of the present invention, the Shixi through electrode can also directly connect the power input/output pad 35 through the connection circuit 333 in 201023323. As shown in FIG. 4, the power transmission (arrow A) can be directly The through-electrode 34 is directly connected to the power input/output pad 35 to carry out current transfer, and the shield 332 is disposed on the periphery of the 矽-through electrode 34, and the shielding effect can also be achieved. In still another embodiment of the present invention, the shield member 332 can be disposed on the periphery of the circuit region 331, as shown in Fig. 5, and the interference of the circuit region 331 from the through-electrode 34 and the connection circuit 333 can be avoided. Regarding the shape and arrangement of the shield 332 of the present invention, please refer to Figs. 6 to 10. 6 to 7 are cross-sectional views drawn in accordance with the position of the tangent I in Fig. 3; and Figs. 8 to 1 are cross-sectional views drawn in accordance with the tangent J in Fig. 3. The tangent 1 and the tangent j correspond to the cross section of the metal wiring layer and the via portion of the connection circuit 333, respectively. ❹ It can be clearly seen from the cross-sectional view that the shielding member 332 of the present invention may be a continuous metal ring pattern or a discrete metal block pattern. As shown in FIG. 6, the shielding member 332 includes at least one continuous metal ring layer. In addition, as shown in FIG. 7, the shield 332 includes at least one discrete, discontinuous metal block layer. Similarly, if the cross section of the connection circuit 333 is a via, that is, the tangent line position shield 332 may also include at least one continuous metal ring layer, as shown in FIG. 8, or include a discrete, discontinuous The metal block layer is shown in Figure 9. 11 201023323 For the shape surrounded by the shield 332, please refer to Fig. 8 and Fig. In general, the shield 332 of the present invention comprises at least: two embodiments of the invention, the shield 332 comprises at least the figure; and in another embodiment of the invention, the shield is at least 3 - round The metal layer is shown in Figure 10. ❹ 2, the embodiment of the shield 332 is not limited to the above embodiment, and = two kinds of continuous, scattered and "polygonal" structure arrangement, white, good shielding effect. Further, the shield member 332 of the present invention is not limited to the structure of the early layer, but may include a plurality of layers of the H structure 4, U 2 , which is exemplified as a shield structure having a plurality of layers. The shield structure L of the present invention contains a first shield member 3322 and a second shield member. Wherein the first shielding member 3322 is a continuous octagonal metal layer, and the second shielding member is a discrete circular metal layer, and of course, further includes a third shielding member (not shown) or The fourth shielding member (not shown) is combined with a plurality of shielding members 332 to obtain a good shielding effect. Of course, the structure of each of the shields 332 can also be a combination of various continuous discontinuities and patterns of various polygons. In addition, the present invention utilizes various metal interconnect processes, such as an aluminum process, a via plug process, a copper damascene process, and the like, and adjusts the formed plurality of metal circuit layers and a plurality of connections. The layout of the vias of each metal layer can be effectively integrated into the current semiconductor process, 12 201023323
331之外圍，故能有 電力時所產生的電磁 效屏蔽矽貫通電極34於連接電路傳輪 干擾(ΕΜΙ)，避免影響電路區331。 而於此金屬内’石▲，丨 連接電路333 侷限别述之連續或不連續之環狀圖案、 案等、單層或多層圖案，而且本發明之 石夕貫通電極34、連接電路333 此外，為加強屏蔽件332之屏蔽效I，本發明之屏蔽件 332結構更可連接一信號接地3321，如第3圖所示。此信號 接地3321可連接至最穩^的接地端，例如安裝有半導體封 裝件的线板(未㈣）的接地或晶片缺接地，以便更有效 率地避免雜訊。再者，與系統板的接地之間還可再另行設置 一高頻濾波器以選擇性地避免及移除高頻雜音。 表τ、上而吕，本發明之半導體裝置，包含有一屏蔽件332， 设置於梦貫通電極34或連接電路333之外圍，並具有一信 號接地3321，故能有效阻絕習知矽貫通電極34於連接電路 傳輸電力時，對周遭之電路元件（如電路區331)造成雜訊 之問題。 以上所述僅為本發明之較佳實施例，凡依本發明申請專 利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 13 201023323 【圖式簡單說明】 第1圖為習知具有矽貫通電極之晶粒堆疊示意圖。 第2圖為習知具有矽貫通電極之晶粒剖面圖。 第3圖為本發明中半導體結構示意圖。 第4圖與第5圖為本發明半導體結構之另一實施例。 第6圖至第11圖為本發明中半導體結構屏蔽件之示意圖。 【主要元件符號說明】 1,2 晶粒 331 電路區 11,21 基底 332 屏蔽件 13,23 金屬内連線層 3321 信號接地 14,24 矽貫通電極 3322 第一屏蔽件 15,25 接觸墊 3323 第二屏蔽件 16,26 锡球 333 連接電路 17 電路區 34 矽貫通電極 18 電力傳輸層 341 絕緣層 3 半導體結構 35 電源輸入/輸出墊 31 基底 351 電力傳輸層 33 金屬内連線層 352 接觸墊 14Outside the 331, the electromagnetic effect generated by the power can be shielded from the through-electrode 34 to the circuit-carrying interference (ΕΜΙ) to avoid affecting the circuit area 331. In the metal, the 'stone ▲, the 丨 connection circuit 333 is limited to a continuous or discontinuous ring pattern, a case, etc., a single layer or a multi-layer pattern, and the stone-like through electrode 34 and the connection circuit 333 of the present invention are further provided. In order to enhance the shielding effect I of the shield member 332, the shield member 332 of the present invention can be further connected to a signal ground 3321 as shown in FIG. This signal ground 3321 can be connected to the most stable ground, such as the ground of the board (not (4)) on which the semiconductor package is mounted or the wafer is not grounded to avoid noise more effectively. Furthermore, a high frequency filter can be additionally provided between the ground of the system board to selectively avoid and remove high frequency noise. The semiconductor device of the present invention includes a shield member 332 disposed on the periphery of the dream through electrode 34 or the connection circuit 333 and having a signal ground 3321, so that the conventional through electrode 34 can be effectively blocked. When the connection circuit transmits power, it causes a problem of noise for surrounding circuit components (such as circuit area 331). The above are only the preferred embodiments of the present invention, and all changes and modifications made to the patent scope of the present invention are intended to be within the scope of the present invention. 13 201023323 [Simple description of the drawings] Fig. 1 is a schematic diagram of a conventional crystal stack having a through electrode. Fig. 2 is a cross-sectional view of a conventional crystal having a through electrode. Figure 3 is a schematic view showing the structure of a semiconductor in the present invention. 4 and 5 are another embodiment of the semiconductor structure of the present invention. 6 to 11 are schematic views of a semiconductor structure shield in the present invention. [Main component symbol description] 1,2 die 331 circuit area 11, 21 substrate 332 shield 13, 23 metal interconnect layer 3321 signal ground 14, 24 矽 through electrode 3322 first shield 15, 25 contact pad 3323 Second shield 16, 26 Tin ball 333 Connection circuit 17 Circuit area 34 矽 Through electrode 18 Power transmission layer 341 Insulation layer 3 Semiconductor structure 35 Power input/output pad 31 Substrate 351 Power transmission layer 33 Metal interconnection layer 352 Contact pad 14