TWI454037B - Multi-phase non-inverting buck boost voltage converter and operating and controlling methods thereof - Google Patents

Description

Multiphase non-inverting buck-boost voltage converter and operation and control method thereof [Reciprocal Reference of Related Applications]

This application claims the benefit of U.S. Patent Application Serial No. 13/160,162 (Attorney Docket No. INTS-30,622) filed on Jun. 14, 2011, which is incorporated herein by reference. This is a continuation of U.S. Patent Application Serial No. 12/848,579 (Attorney Docket No. INTS-29, 982) filed on Aug. 2, 2010.

This invention relates to buck-boost voltage converters and, more particularly, to a system and method for controlling a non-inverting buck-boost converter to provide smooth transitions between buck and boost modes of operation.

The non-inverting buck-boost converter is capable of achieving an output voltage above or below its input voltage depending on the mode of operation. As battery-powered devices become more popular, these types of converters are becoming more attractive because they can take advantage of the battery's discharge cycle. When a battery input voltage is higher than its output voltage, a buck-boost converter operates in a buck mode of operation. In the buck mode of operation, the converter reduces the input voltage to a necessary level for use at its output. When a battery input voltage is lower than the output voltage, the buck-boost converter operates in a boost mode of operation in which the input voltage is increased to a desired level at its output. Control in the pure buck and pure boost modes of operation is achieved by the turn-on and turn-off of various associated power switches. When the output voltage is close to the input voltage, the transition between the buck and boost modes of operation provides various control challenges. Two challenges from controlling the buck-boost converter during such transitions between buck and boost modes of operation include the generation of a line transient that is a dynamic response and the generation of output chopping, where the resulting input The voltage system is close to the output voltage, which is a problem of steady state performance.

As disclosed and described herein, in one aspect of the invention, the invention includes a non-inverting buck-boost converter. The buck-boost converter includes a buck-boost voltage regulating circuit for generating an adjusted output voltage in response to an input voltage. A current sensor monitors an input current of the buck-boost regulating circuit. The buck-boost mode control circuit is responsive to the monitored input current to control the buck-boost voltage regulation circuit utilizing deep current mode control in a buck mode of operation and utilizing active current mode control in a boost mode of operation.

Referring now to the drawings, wherein like reference numerals are used to refer to the like elements throughout the disclosure, various views and embodiments of a non-inverted buck-boost voltage converter are depicted and described, and other possible embodiments The system is described. The figures are not necessarily to scale, and in some instances, the drawings have been exaggerated and/or simplified in some places. Those of ordinary skill in the art will recognize many possible applications and variations of the examples in accordance with the following possible embodiments.

A non-inverting buck-boost converter is capable of achieving a positive output voltage above or below its input voltage. As battery-powered devices become more popular, such topologies are becoming more attractive because they can take advantage of the battery's discharge cycle. When a battery input voltage is higher than its output voltage, a buck-boost converter operates in a buck mode of operation. In the buck mode of operation, the converter reduces the input voltage to the necessary level for use at its output. When the battery input voltage is lower than the output voltage, the buck-boost converter operates in a boost mode of operation in which the input voltage is increased to a desired level at the output. It is quite easy to implement control in a pure buck mode of operation or a pure boost mode of operation by having certain power switches turned "on" or "off". This challenge still exists between the buck and boost modes of operation when the output voltage is close to the input voltage. There are two challenges in controlling this buck-boost converter during this transition between the buck and boost modes of operation. One challenge involves a line transient, which is a dynamic response. Another challenge is the output chopping, where the resulting input voltage is close to the output voltage, which is a problem with steady state performance.

The implementations described below include a design that controls the non-inverting buck-boost converter and provides a means of achieving smooth transitions and line transients between modes while still maintaining minimal chopping when the output voltage is close to the input voltage. Voltage. Only one integrated current sensor is utilized in this design, rather than multiple sensors, to reduce complexity and simplify the overall design. The controller utilizes cycle-by-cycle detection to use a peak current mode control in the buck mode of operation and a valley current control mode in the boost mode of operation. This method provides smooth transitions and line transients within the converter. In the condition that the output voltage is close to the input voltage, the buck-boost converter automatically switches from the step-down operation mode to the step-up operation mode or from the step-up operation mode by monitoring the maximum duty cycle. This step-down mode of operation. This simplifies the control of the buck-boost converter and reduces the output voltage ripple. Both the buck mode operation and the boost mode operation use the same integrated current sensor, which reduces the complexity of the system and increases overall reliability.

A non-inverting buck-boost converter is capable of achieving a positive output voltage above or below its input voltage. Many applications prefer non-inverting buck-boost converters, for example, battery-powered devices that are eager to utilize the discharge cycle of the battery. Battery-powered electronic devices and automobiles suffer from poor battery voltage due to load dumps or cold start. In these cases, the non-inverting buck-boost converter is an ideal candidate. If the load power is high, a multi-phase buck-boost converter is required for low cost and heat dissipation.

Referring now to the drawings, and more particularly to FIG. 1, an overview of a buck-boost converter is depicted. The buck-boost converter includes an input voltage node 102 that applies an input voltage V _IN . A high side buck transistor 104 includes a P-channel transistor such that its source/drain path is connected between node 102 and node 106. A low side buck transistor 108 includes an N-channel transistor such that its drain/source path is connected between node 106 and ground. An inductor 110 is coupled between node 106 and node 112. A high side P-channel boost transistor 114 is connected such that its source/drain path is connected between the output voltage node V _OUT 116 and node 112. A low side boost transistor 118 includes an N-channel transistor such that its source/drain path is connected between node 112 and ground. As is well known to those skilled in the art, these high side buck and boost transistors can also be implemented by N-channel transistors. Furthermore, all of the switching transistors can be implemented by a dual carrier transistor or any other suitable controlled switching device. The output capacitor 120 is connected between the output voltage node 116 and ground. The output load resistor 122 is connected in parallel with the capacitor 120 between the node 116 and ground. Each of the high side buck transistor 104, the low side buck transistor 108, the high side boost transistor 114, and the low side boost transistor 118 causes its gate to be connected to the buck-boost control circuit 124. The buck-boost control circuit 124 utilizes internal control logic to generate a gate control signal via a plurality of outputs that are responsible for at least the output voltage _VOUT applied from the node 116. The duty cycle in this buck mode of operation is defined as D = t _{on (104)} / T, where t _{on is the on-time} of the switching transistor 104 and T is the switching period of the converter. T is the reciprocal of the switching frequency fsw (T=1/fsw). During the boosting action, the duty cycle is defined as D = t _{on (118)} /T, that is, the on-time of the synchronous high-side boost transistor 114 divided by the switching period.

Referring now to Figure 2, depicted is a functional block diagram of a non-inverting buck-boost converter operating in accordance with the present disclosure. The buck-boost converter circuit 202 receives the input voltage V _IN at the input node 204 and the output voltage V _OUT at the node 206. The switching cell system within the buck-boost converter 202 is driven in accordance with a drive control signal provided by the drive logic 208. The drive logic 208 is responsive to the PWM control signals provided by the PWM control logic 210 to generate drive control signals to the switch transistors. The error amplifier and PWM control logic 210 is responsive to the output voltage monitored at node 206 and also to the current control voltage VSUM provided by current slope control compensation logic 212 to generate the PWM control signals. The current slope control compensation logic is responsive to the current monitored by one of the current sensers 214 in the buck-boost converter 202 and the mode control logic 216 to generate the VSUM voltage to the error amplifier and PWM control logic 210. . The current sensor 214 measures the input current provided at the input node 204 of the buck-boost converter 202. The mode control logic 216 determines that the buck-boost converter 202 is operating in the buck mode or boost mode by monitoring the PWM signal provided by the PWM control logic 210. The mode control logic 216 additionally provides mode control signals to the drive logic 208 to control operation of the switching transistors within the buck-boost converter 202.

Referring now to Figure 3, a block diagram of a non-inverting buck-boost converter incorporating the present disclosure is depicted. The buck-boost converter 302 includes an input voltage node 304 that applies an input voltage V _IN . A current sensor 306 senses the input voltage current through node 304 and provides a sensed input current I _SNS . A high side buck transistor 308 is coupled between the current sensor 306 and the node 310. The high side buck transistor 308 includes a P-channel transistor. The high side buck transistor 308 is coupled to receive the drive signal HD_BUCK. A low side buck transistor 312 includes an N-channel transistor such that its drain/source path is connected between node 310 and ground node 314. The low side buck transistor 312 is coupled to receive the drive control signal LD_BUCK. An inductor 316 is coupled between node 310 and node 318.

A high side boost transistor 320 includes a P-channel transistor having its source/drain path connected between the output voltage node V _OUT 322 and node 318. The low side boost transistor 321 includes an N-channel transistor such that its drain/source path is connected between node 318 and node 314. The gate of transistor 324 is coupled to receive the drive control signal LD_BOOST. The gate of the high side boost transistor 320 is connected to receive the drive control signal HD_BOOST. An output capacitor 326 is coupled to the output voltage node 322 and between the output voltage node 322 and the ground node 314. In addition, a load 328 and the output capacitor 326 are connected in parallel between the output voltage node 322 and the ground node 314.

The driving control signals of each of the high side step-down transistor 308, the low side step-down transistor 312, the high side boosting transistor 320, and the low side boosting transistor 324 are respectively driven by the step-down mode. Current logic and driver 330 and boost mode control logic and driver 332 are provided. The buck mode control logic and driver 330 is responsive to a PWM signal (PWM_BUCK) provided by the SR latch 334 and a mode control signal provided by the mode control logic 336 to generate the HD_BUCK signal to the high side. The piezoelectric crystal 308 and the step-down transistor 312 that generates the LD_BUCK signal to the low side. The boost mode control logic and driver 332 is responsive to a PWM control signal (PWM_BOOST) from the SR latch 338 and a mode control signal from the mode control logic 336 to generate the HD_BOOST drive signal to the transistor 320 and to generate The LD_BOOST drives the signal to transistor 324. The transistors 308 and 312 are power switches of the buck-boost converter 302 in the step-down mode of operation. In this step-down mode of operation, transistor 320 is always turned on and transistor 324 is always turned off. Similarly, in the boost mode of operation, the buck mode control logic and driver 330 and the boost mode control logic and driver 332 control the boost transistors 320 and 324 to form a power FET switch. In this boost mode of operation, the transistor 308 is always turned on and the transistor 312 is turned off.

The SR latch 334 is responsive to a clock signal provided at the S input of the SR latch 334 and a logic signal applied to the R input of the SR latch 334 to generate the buck PWM signal to the buck mode. Control logic and driver 330. The PWM signal PWM_BOOST is provided by the Q output of the SR latch 338 in response to a clock input to the R input of the SR latch 338 and a logic input to the S input of the SR latch 338.

The mode control logic 336 provides the MODE signal to each of the buck mode control logic and driver 330 and boost mode control logic and driver 332. The mode control logic 336 generates the output control signal MODE to the buck mode control logic and driver 330 and the boost mode control logic and driver 332 in response to the PWM_BUCK and PWM_BOOST signals provided by the outputs of the SR latches 334 and 338, respectively. Every one. The maximum duty cycle detection circuit 340 is responsive to the output voltage V _OUT proximate to the input voltage V _IN to determine when a maximum duty cycle condition exists between the buck and boost modes of operation. When a maximum duty cycle condition is detected, the maximum duty cycle detection circuit 340 generates a logic "high" value to the MAX_D signal, which is provided to mode selection logic 342.

The mode selection logic 342 determines whether the buck-boost converter 302 needs to switch to the buck mode of operation or the boost mode of operation and generates a mode control signal MODE to indicate the change. In order to smoothly switch from the buck action to the boost action or from the boost action to the buck action, the determination of the maximum duty cycle is introduced into the control design by the maximum duty cycle detection circuit 340. The MAX_D signal becomes a logical "high" level whenever a maximum duty cycle condition is detected. This typically occurs when the input voltage V _{IN is} close to the output voltage V _OUT or when a load transient occurs in the output. The mode selection logic 342 determines that the mode of operation of the buck-boost converter 302 is buck or boost. A simple control method is implemented such that each time a MAX_D logic "high" signal is detected, the mode of operation is switched. More complex control methods can be applied by utilizing multiple MAX_D signals. There are two modes of operation in the buck-boost converter, and there are only two modes of operation, either buck or boost. The output "MODE" signal of the mode selection logic acts like a multiplexer control signal to select an operational circuit (eg, current sensing) and switch drivers depending on whether the converter is in a buck or boost mode of operation Control logic. Therefore, the MODE control signal selects the buck mode control logic driver 330 or the boost mode control logic and driver 332 according to the operation mode, and also selects the current sensing compensation provided by the output of the multiplexer 344. signal.

The multiplexer 344 is connected to receive a VSUM_BUCK signal or a VSUM_BOOST signal. The VSUM_BUCK signal includes a sum of sensed current from current sensor 306, a buck mode offset signal, and a buck slope compensation signal, which are summed together in adder circuit 346. . The VSUM_BOOST signal is generated by an adder circuit 348 by summing the measurement of the ISNS input current from the current sensor 306, a boost mode offset signal, and a boost slope compensation signal. The sensed current ISNS from the current sensor 306 and the buck mode offset or boost mode offset are summed to ensure that the error amplifier 352 is operating with a suitable DC bias. The buck or boost compensation slope is added to the sensed current to avoid oscillation of the subharmonic during operation during a large duty cycle. Each of the VSUM_BUCK and VSUM_BOOST compensation signals is provided to an input of the multiplexer 344. According to the buck-boost converter 302 operating in the buck mode or the boost mode, either VSUM_BUCK (buck mode) or VSUM_BOOST (boost mode) is selected in response to the MODE signal at the multiplexer 344, And the selected signal is provided as the output current compensation signal V _SUM .

The V _SUM signal is supplied from the multiplexer 344 to an inverted input of a PWM comparator 350. The non-inverting input of the PWM comparator 350 is coupled to receive the voltage error signal V _COMP from an error amplifier 352. The output of the error amplifier 352 is coupled to ground through a series connection of a capacitor 354 and a resistor 356. The inverting input of the error amplifier 352 is monitored at node 322 by a resistor divider formed by a resistor 358 connected between node 322 and node 360 and a resistor connected to node 360 and ground. The output voltage is V _OUT . The inverted input of error amplifier 352 is coupled to node 360. The error amplifier 352 compares a reference voltage V _REF applied to its non-inverted input with an output feedback voltage from the buck-boost converter 302 to generate an error signal V _COMP . The V _COMP signal is used to determine a peak current mode when the buck-boost converter operates in the buck mode of operation and through the inductor 316 in a valley current mode when the buck-boost converter operates in the boost mode of operation. Inductor current. The buck operation shares the same voltage error signal as the boost operation. The comparison of V _SUM from the output of multiplexer 344 to the voltage error signal V _COMP determines the on/off states of power transistors 308, 312, 320, and 324.

The output of the PWM comparator 350 (V _COMPOUT ) is provided as an input to an inverter 362 and a first input to the AND gate 364. The output from the inverting of inverter 362 is provided to a first input of OR gate 366. Another input of OR gate 366 is coupled to receive the MAX_D signal from the output of the maximum duty cycle detection circuit 340. The output of the OR gate 366 provides a logic signal to the R input of the latch 334 to enable the generation of the buck PWM signal. The other input of AND gate 364 is coupled to the output of an inverter 368. The input of inverter 368 is coupled to receive the MAX_D signal from the maximum duty cycle protection circuit 340. The output of the AND gate 364 is coupled to another inverter 370. The output of the inverter 370 provides a logic signal to the S input of the SR latch 338 to provide the boost PWM signal.

Referring now to Figure 4, a flow chart depicting the operation of the buck-boost converter of Figure 3 is depicted. When the operation of the converter begins at step 402, the converter initially operates in a step-down mode of operation at step 404 and operates in the operating mode of the peak current control. The query step 406 monitors the maximum duty cycle, and if the maximum duty cycle is not currently detected, then control passes back to step 404. When the maximum duty cycle is detected, the converter enters the boost mode of operation at step 408 and operates with the valley current control mode. The query step 410 monitors the maximum duty cycle, and if the maximum duty cycle is not detected, the control passes back to step 408. When the maximum duty cycle is detected, the converter transitions back to operating in the buck mode of operation at step 404.

Referring now to Figure 5, there are depicted various waveforms associated with the buck-boost converter when the buck-boost converter 302 transitions from a buck mode of operation to a boost mode of operation. Transistors 308 and 312 form the primary power switch in the buck mode of operation. The transistor 320 is always on during this buck mode of operation, and the transistor 324 is always off during the buck mode of operation. As the input voltage V _IN 502 falls, the duty cycle of the switching increases due to D~Vout/Vin. When the input voltage V _IN 502 drops to a value that reaches a maximum threshold (maximum duty cycle), the maximum duty cycle detection circuit 340 (which in one embodiment includes a digital comparison) In response to this condition, the signal MAX_D is set to a logic "high" level. At the same time, the high side transistor 308 is turned off and the transistor 312 is turned on. The mode select logic 342 is aware of the next cycle, and when the clock signal is present at the input of the SR latch 334, the buck-boost converter 302 will transition to the boost mode. The control signal MODE is set to a logic "high" level (boost) when the clock pulse arrives, and the buck-boost converter is now configured to be set in the boosting operation. However, in this case, the input voltage V _IN 502 is still a little higher than the output voltage V _OUT 504, and thus the boost mode of operation may be pumping excess energy into the load and further increasing the output voltage V _OUT . Thus, the buck-boost converter 302 returns to the buck mode of operation after the boost cycle and remains in the buck mode of operation for more than one cycle until the output voltage V _OUT 504 falls below the input voltage V _IN . As V _IN 502 falls further, there will be more boost cycles. In this way, a smooth transition from the buck mode of operation to the boost mode of operation is provided. FIG. 5 also depicts the output V _SUM 506 of the multiplexer 344, the output of the error amplifier V _COMP 508, and the inductor current 510.

Referring now to Figure 6, a depiction of the buck-boost converter 302 transitions from a boost mode of operation to a step-down mode of operation. When the input voltage V _IN 602 is much lower than the output voltage V _OUT 604, the buck-boost converter operates in a pure boost mode of operation. The transistors 320 and 324 form the primary power switch in the boost mode of operation, while the transistor 308 is always on and the transistor 312 is always off. As the input voltage V _IN 602 increases, the duty cycle of the switching increases because the buck-boost converter 302 is in the valley control mode of operation. The maximum duty cycle detection circuit 340 including a digital comparator responds to the situation when the input voltage V _IN 602 is increased to a certain level when the duty cycle reaches a maximum threshold level (maximum duty cycle). And the signal MAX_D is set to a logic "high" level. At the same time, the high side transistor 320 is turned off and the low side transistor 324 is turned on. The mode select logic 342 knows the next cycle and when a clock signal occurs, the converter will transition to the buck mode. When the clock signal arrives, the signal "MODE" is set to a logic "low" level (buck mode) and the entire buck-boost converter is configured to be set in the buck mode of operation. However, in this case, the input voltage V _IN 602 is still lower than the output voltage V _OUT 604. Therefore, the buck mode of operation may be pulling too much energy to the load, and the output voltage V _OUT 604 is reduced. Thus, the buck-boost converter 302 returns to the boost mode of operation after the buck cycle and remains in the boost mode of operation for more than one cycle until the output voltage 604 is increased. As the input voltage V _IN 602 increases further, there may be more buck cycles. In this way, a smooth transition from boost to buck is provided.

The plot of FIG. 6 further depicts the output V _SUM 606 of the multiplexer 344, the error voltage output V _COMP 608, and the inductor current 610.

When the output voltage V _{OUT is} close to the input voltage V _IN , the buck-boost converter 302 switches from buck to boost and from boost to buck mode. There is no separate buck-boost mode for the buck mode and boost mode. The control method ensures smooth transition by utilizing the peak current control mode in the buck mode of operation and the valley current control mode in the boost mode of operation. One of the main advantages of this method is that the error signal V _COMP does not have any sudden changes during mode switching. Since the V _COMP signal is a direct function of the output voltage V _OUT , if the error signal V _COMP is stable, the output voltage V _OUT is stable. As previously described, the output V _SUM of the multiplexer is the sum of the input current ISNS, the buck or boost mode offset, and a slope compensation signal. The different offset values in the buck and boost modes of operation are selected based on the largest slope compensation in a full cycle. Usually the different offset values are twice the maximum slope compensation voltage. For example, if the slope compensation is 1V/us and the switching frequency is 1MHz, the different offset value is 1V/us*1us*2, which is 2V. Therefore, if the offset in the buck mode is Vos, the offset for the boost mode is Vos+2V. A system that operates in this manner provides excellent line transients in both light and heavy load conditions. When the output voltage is close to the input voltage, the voltage ripple is also small. The control method is simple, which requires only a single integrated current sensor and cycle-by-cycle detection.

Referring now to Figure 7, a block diagram of the multiphase non-inverting buck-boost converter is depicted. The error amplifier 702 provides a feedback divider and loop compensation to the multiphase non-inverting buck-boost converter. The error amplifier system 702 generates a compensation signal V _COMP, the compensation signal V _COMP-based and is provided to each phase of the multiphase non-inverting buck-boost converter connected to each of the associated modulator 704 and driver circuitry. The modulator and driver circuit 704 is responsive to a V _COMP signal from the error amplifier 702 and a current signal I _SNS from the associated current sensor 708 to generate a drive signal to an associated buck-boost converter 706. The current sensor 708 monitors an input current of the associated buck-boost converter 706 to generate an I _SNS voltage signal to the associated modulator and driver 704. The buck-boost converter 706 generates an output voltage V _OUT that is monitored by the error amplifier 702 to generate the compensation voltage V _COMP .

Referring now to Figure 8, a block diagram of the modulator and driver circuit 704 is depicted, the modulator and driver circuit 704 being associated with each phase of the multi-phase non-inverting buck-boost converter. The PWM logic 802 generates the PWM control signals to the drive logic 804 and the mode control logic 806. The drive logic 804 is responsive to the PWM control signal provided by the PWM logic 802 to generate a drive signal to the switching transistor of the associated buck-boost converter. The mode control logic 806 determines whether the buck-boost converter is operating in a buck mode or a boost mode by monitoring a PWM signal from the PWM logic 802. The mode control logic 806 additionally provides mode control signals to the drive logic 804 to control the operation of the switching transistors within the buck-boost converter. The current slope compensation circuit 808 is responsive to current I _SNS from the buck-boost converter and provided by one of the current sensors 708 (FIG. 7) to generate a V _SUM voltage to the PWM logic 802.

Referring now to Figure 9, there is provided a more detailed block diagram of one of the multiphase non-inverting buck-boost converters provided between the different phases of the buck-boost converter Essential current sharing. As previously described, the error amplifier portion 702 monitors the output voltage of the output of the combination of the plurality of phases from the buck-boost converter 706 at node 902. The error amplifier circuit 702 includes a voltage divider formed by a resistor 904 connected between the node 902 and the node 906 and a resistor 908 connected to the node 906 and the ground. A feedback voltage V _FB is monitored at node 906 by an inverted input of an error amplifier 910. The non-inverting input of error amplifier 910 receives a reference voltage V _{REF for} comparison with the feedback voltage V _FB . The output of the error amplifier 910 is coupled to node 912 to provide a V _COMP input to each of the modulators and drivers 704 associated with each phase of the multi-phase non-inverting buck-boost converter. A comparator 914 and a resistor 916 connected in series are connected between the node 912 and ground. The comparator 914 is coupled between node 912 and node 918, and the resistor 916 is coupled between node 918 and ground. The error amplifier 910 includes a transconductance amplifier that produces a compensation signal V _COMP that is fed to each of the modulator and driver circuit 704. This system requires only a single error amplifier 910. However, multiple error amplifiers 910 can be placed in parallel and the total gain of the error amplifier will include the sum of each of the error amplifiers.

The second portion of the system depicted in FIG. 9 includes a modulator and driver 704. The modulator and a driver 704 lines were connected to receive from the error amplifier compensation signal V _COMP 910 and a current sense signal I _SNSN, the current sense signal I _SNSN lines associated with the down converter input voltage The sensed input current associated with a particular phase of the multiphase converter. Each phase of the converter requires a different modulator because the clock signals for each phase are different to produce interleaved inductor currents and smaller output and input ripple than a single phase converter. . An N-phase converter would ideally have a phase shift of 360/n between adjacent phases. Each phase also has independent current sensing from I _SNS1 to I _SNSn . This architecture provides a mechanism for intrinsic current balancing. The sense current voltage I _SNSn is compared with the compensation signal V _COMP regardless of the peak current mode in the buck mode of operation or the valley current mode control in the boost mode of operation. Since V _COMP is a common signal between each modulator, this signal balances the current of each phase. This is one of the great benefits of this multiphase converter, which reduces the complexity of the design while achieving excellent performance. Each phase has its own maximum duty cycle detection circuit and mode selection circuit. When V _{IN is} close to V _OUT , some phases may operate in buck mode while others operate in boost mode, which produces smaller output chopping. The modulator and driver circuit 704 for each phase produces each of the HD_BUCKn, LD_BUCKn, HD_BOOSTn, and LD_BOOSTn switch transistors associated with their associated phase buck-boost converters.

The output of these drivers is provided to the associated power switching transistor of the buck-boost converter 706. Each buck-boost converter 706 includes an input voltage node 915 that provides an input voltage to be regulated. A current sensor 917 senses the input voltage current through node 915 and provides a sensed input current voltage I _SNSn . A high side buck transistor 919 is coupled between the current sensor 917 and node 920. The high side buck transistor 919 includes a P-channel transistor. The high side buck transistor 919 is connected to receive the drive signal HD_BUCKn. A low side buck transistor 922 includes an N-channel transistor that connects its drain/source path to node 920 and ground node 924. The low side buck transistor 922 is coupled to receive the drive control signal LD_BUCKn. An inductor 926 is coupled between node 920 and node 928.

A high side boost transistor 930 includes a P-channel transistor having its source/drain path connected between the output voltage node V _OUT 932 and node 928. The low side boost transistor 934 includes an N-channel transistor having its drain/source path connected between node 928 and ground node 924. The gate of the transistor 934 is connected to receive the drive control signal HD_BOOSTn. The high side and low side buck and boost switch transistors and current sensors in each of the buck-boost converters associated with each phase of the multiphase buck-boost converter are identical. Each buck-boost converter has its output connected to node 932. In addition, a load system formed by a resistor 935 is connected between the node 932 and the ground. A capacitor 936 is connected in parallel with resistor 935 and is connected between node 932 and ground.

The drive control signal transmitted to each of the high side step-down transistor 918, the low side step-down transistor 922, the high side booster transistor 930, and the low side booster transistor 934 is modulated by the modulation And driver circuit 704 provides. Referring now to Figure 10, a block diagram of an overview of a modulator and driver circuit 704 for generating these gate drive switch signals is more particularly depicted. The buck mode control logic and driver 1002 is responsive to a PWM signal (PWM_BUCK) provided by the SR latch 1004 and a mode control signal provided by the maximum duty cycle detection and mode selection logic 1006 to generate the HD_BUCKn signal. The buck transistor 918 to the high side and generates the LD_BUCKn signal to the low side buck transistor 922.

The boost mode control logic and driver 1008 is responsive to a PWM control signal (PWM_BOOST) from the SR latch 1010 and a mode control signal from the maximum duty cycle detection and mode selection logic 1006 to generate the HD_BOOSTn driver. The signal is applied to transistor 930 and the LD_BOOSTn drive signal is generated to transistor 934. The transistors 918 and 922 are power switches of the buck-boost converter in a step-down mode of operation. In the buck mode of operation, transistor 930 is always turned on and transistor 934 is always turned off. Similarly, in the boost mode of operation, the buck mode control logic and driver 1002 and the boost mode control logic and driver control the boost transistors 320 and 324 that make up the power FET switch. In the boost mode of operation, the transistor 918 is always turned on and the transistor 922 is always turned off. The SR latch 1004 is responsive to a clock signal provided at the S input of the SR latch 1004 and a logic signal applied to the R input of the SR latch 1004 to generate the PWM_BUCK signal to the buck mode control. Logic and driver 1002. The PWM signal PWM_BOOST is provided by the Q output of the SR latch 1010 in response to a clock input received at the R input of the SR latch 1010 and a logic input provided to the S input of the SR latch 1010.

The maximum duty cycle detection and mode selection logic 1006 provides the mode signal to each of the buck mode control logic and driver 1002 and boost mode control logic and driver 1008. The maximum duty cycle detection and mode selection logic 1006 is responsive to the PWM_BUCK and PWM_BOOST signals provided by the outputs of the SR latches 1004 and 1010, respectively, to generate the output control signal MODE to the buck mode control logic and driver 1002 and The boost mode controls the logic and each of the drivers 1008. The maximum duty cycle detection and mode selection logic 1006 is responsive to the output voltage V _OUT approaching the input voltage V _IN to determine when a maximum duty cycle condition exists between the buck and boost modes of operation. When the maximum duty cycle condition is detected, the maximum duty cycle detection and mode selection logic 1006 generates a logic "high" value for the MAX_D signal.

The maximum duty cycle detection and mode selection logic 1006 determines whether the buck-boost converter needs to switch to the buck mode or boost mode and generates a mode control signal MODE to indicate the change. In order to smoothly switch from the buck operation to the boost operation or the buck operation to the buck operation, the determination of the maximum duty cycle is introduced by the maximum duty cycle detection and mode selection logic 1006. Control design. The MAX_D signal becomes a logic "high" whenever a maximum duty cycle condition is detected. This typically occurs when the input voltage V _{IN is} close to the output voltage V _OUT or when a load transient occurs in the output. The maximum duty cycle detection and mode selection logic 1006 determines whether the buck-boost converter mode of operation is buck or boost. A simple control method is implemented such that each time a MAX_D logic "high" signal is detected, the mode of operation is switched. More complex control methods can be applied by utilizing multiple MAX_D signals. There are two modes of operation in the buck-boost converter, and there are only two modes of operation, either buck or boost.

The mode output "MODE" signal of the maximum duty cycle detection and mode selection logic 1006 acts like a multiplexer control signal to select an operational circuit depending on whether the converter is in a buck or boost mode of operation ( For example, current sensing) and switching driver control logic. Therefore, the mode control signal selects the buck mode control logic driver 1002 or the boost mode control logic and driver 1008 according to the operation mode, and also selects the current sensing compensation provided by the output of the multiplexer 1012. signal.

The multiplexer 1012 is connected to output a V _SUM _BUCK signal or a V _SUM _BOOST signal. The V _SUM _BUCK signal includes a sum of the sensed current from current sensor 916, the buck mode offset signal, and a buck slope compensation signal, which are summed together in adder circuit 1014. The V _SUM _BOOST signal is generated by adder 1016 by summing the I _SNS input current measurement from current sensor 916, a boost mode offset signal, and a boost slope compensation signal. The sensed current voltage I _SNS from the current sensor 916 is summed with the buck mode offset or boost mode offset to ensure that the error amplifier 910 is operating with a suitable DC bias. The buck or boost compensation slope is added to the sensed current to avoid oscillation of the subharmonic during operation during a large duty cycle. Each of the V _SUM _BUCK and V _SUM _BOOST compensation signals is provided to the input of the multiplexer 1012. According to the buck-boost converter operating in a buck mode of operation or a boost mode of operation, not the V _SUM _BUCK (buck mode) is the V _SUM _BOOST (boost mode) responsive to the multiplexer 1012 The mode signal is selected and the selected signal is provided as the output current compensation signal V _SUM .

The V _SUM signal is provided to the inverted input of the PWM comparator 1015. The non-inverting input of the PWM comparator 1015 is coupled to receive the voltage error signal V _COMP from an error amplifier 910. The V _COMP signal is utilized as previously described in a single phase mode of operation in the multi-phase mode of operation. The output of the PWM comparator 1015 is provided as an input to an inverter 1017. The inverted output from inverter 1017 is provided to a first input of OR gate 1018 and a first input of AND gate 1020. Another input of OR gate 1018 is coupled to receive the MAX_D signal from the output of the maximum duty cycle detection and mode selection logic 1006. The other input of the AND gate 1020 is coupled to receive an inverted MAX_D signal from an inverter 1022. The output of the OR gate 1018 provides the logic signal to the R input of the SR latch 1004 to enable the generation of the buck PWM signal. The output of the AND gate 1020 is provided to an inverter 1024. The output of inverter 1024 is provided to the S input of SR latch 1010 to facilitate the generation of the boost PWM signal. The maximum duty cycle detection and mode selection logic 1006 is responsive to a PWM_BUCK signal from the output of the SR latch 1004, a PWM_BOOST signal from the SR latch 1010, and a clock input signal to generate the MAX_D control signal and a mode control signal. .

Referring now to Figure 11, an embodiment of the maximum duty cycle detection and mode selection logic 1006 is depicted. The MAX_D signal is provided to an S input of an SR latch 1102. A clock input CLK is provided to the R input of the SR latch 1102. The Q output of the SR latch 1102 is provided to an input of a pair of AND gates 1104 and 1106. The AND gate 1104 is a mode signal input that receives the PWM_BUCK signal at its input, is inverted from one of the inverters 1108, and an output of the SR latch 1102. Similarly, the AND gate 1106 is at its input receiving the output of the SR latch 1102, the mode signal, and an inverted version of the PWM_BOOST signal from the inverter 1110. The output of the AND gate 1104 is provided to the S input of the SR latch 1112. The R input of the SR latch receives the output of the AND gate 1106. The Q output of the SR latch 1112 provides a MODE_PRE signal that is provided to a D input of the delay latch 1114. The clock input of the delay latch 1114 is coupled to receive the CLK signal, and the Q output of the delay latch 1114 provides the MODE signal.

The basic operation of the circuit of Figure 11 is as follows. When V _{IN is} close to V _OUT , the duty cycle is close to 100%. In order to maintain the switching of each cycle, a maximum duty cycle signal (MAX_D) is preset. Whenever the PWM signals (PWM_BUCK and PWM_BOOST) reach the MAX_D value, a signal MODE_PRE is set or reset according to the current operating mode (buck or boost). However, the MODE_PRE is not initially applied to the modulator, but becomes active only after the next clock signal pulse is received. The rising edge of the clock sets the mode signal and adjusts the modulator. Operating mode. Each modulator has its own independent decision circuit.

Referring now to Figure 12, there is depicted a two phase non-inverting buck-boost converter operating in a buck mode steady state where V _{IN is} greater than V _OUT . These waveforms depict buck-boost mode operating in a buck mode with V _IN greater than V _OUT . The inductor currents are interleaved to achieve current sharing and small output ripple. The current of each phase is balanced.

Referring now to Figure 13, there is depicted a two phase non-inverting buck-boost converter in a buck mode of operation in which V _IN is closer to V _OUT . The inductor current is interleaved in a more complex way than pure buck and pure boost modes. In this operating region, the converter operates back and forth between a buck and boost mode to regulate the output voltage. In this way, one phase can operate in the buck mode while the other phase operates in the boost mode. In this way, the output chopping system is reduced.

Referring now to Figure 14, a two-phase non-inverting buck-boost converter operating in a buck mode in which V _{IN is} less than V _OUT is depicted. The inductor currents are interleaved to achieve current sharing and small output ripple. The current of each phase is balanced.

Therefore, by providing a plurality of buck-boost power levels in parallel, a larger power system is achieved. This design achieves current balancing without the need to add additional circuitry needed to achieve this current balance result. Smooth line transitions between modes with small output chopping are also provided.

Those skilled in the art, with the benefit of this disclosure, will recognize that the non-inverting buck-boost voltage converter provides improved operation when switching between buck and boost modes of operation. It is to be understood that the appended claims Rather, any further modifications, changes, rearrangements, substitutions, alternatives, designs, and embodiments are apparent to those skilled in the art without departing from the scope of the following claims. The spirit and scope of the invention. Accordingly, the appended claims are intended to cover all such modifications, modifications,

102. . . Input voltage node

104. . . Step-down transistor

106. . . node

108. . . Step-down transistor

110. . . Inductor

112. . . node

114. . . Boost transistor

116. . . node

118. . . Boost transistor

120. . . Output capacitor

122. . . Output load resistance

124. . . Buck-boost control circuit

202. . . Buck-boost converter circuit

204. . . Input node

206. . . Output node

208. . . Drive logic

210. . . PWM control logic

212. . . Control compensation logic

214. . . Current sensor

216. . . Mode control logic

302. . . Buck-boost converter

304. . . Input voltage node

306. . . Current sensor

308. . . High-side step-down transistor

310. . . node

312. . . Low-side step-down transistor

314. . . Ground node

316. . . Inductor

318. . . node

320. . . High side boost transistor

321. . . Low side booster transistor

322. . . Output voltage node

324. . . Low side booster transistor

326. . . Output capacitor

328. . . load

330. . . Buck mode current logic and driver

332. . . Boost mode control logic and driver

334. . . SR latch

336. . . Mode control logic

338. . . SR latch

340. . . Maximum duty cycle detection circuit

342. . . Mode selection logic

344. . . Multiplexer

346. . . Adder circuit

348. . . Adder circuit

350. . . PWM comparator

352. . . Error amplifier

354. . . Capacitor

356. . . Resistor

358. . . Resistor

360. . . node

362. . . inverter

364. . . AND gate

366. . . OR gate

368. . . inverter

370. . . inverter

402. . . step

404. . . step

406. . . Query step

408. . . step

410. . . Query step

502. . . V _IN

504. . . V _OUT

506. . . V _SUM

508. . . V _COMP

510. . . Inductor current

602. . . V _IN

604. . . V _OUT

606. . . V _SUM

610. . . Inductor current

702. . . Error amplifier

704. . . Driver circuit

706. . . Buck-boost converter

708. . . Current sensor

802. . . PWM logic

804. . . Drive logic

806. . . Mode control logic

808. . . Compensation circuit

902. . . node

904. . . Resistor

906. . . node

908. . . Resistor

906. . . node

910. . . Error amplifier

912. . . node

914. . . Comparators

915. . . Input voltage node

917. . . Current sensor

918. . . node

919. . . High-side step-down transistor

920. . . node

922. . . Low-side step-down transistor

924. . . Ground node

926. . . Inductor

928. . . node

930. . . High side boost transistor

932. . . V _OUT

934. . . Low side booster transistor

935. . . Resistor

936. . . Capacitor

1002. . . Control logic and driver

1004. . . SR latch

1006. . . Mode selection logic

1008. . . driver

1010. . . SR latch

1012. . . Multiplexer

1014. . . Adder circuit

1015. . . PWM comparator

1016. . . Adder

1017. . . inverter

1018. . . OR gate

1020. . . AND gate

1022. . . inverter

1024. . . inverter

1102. . . SR latch

1104. . . AND gate

1106. . . AND gate

1108. . . inverter

1110. . . inverter

1112. . . SR latch

1114. . . Delayed latch

For a more complete understanding, reference is now made to the above description in conjunction with the accompanying drawings, in which:

Figure 1 is a schematic view of a step-up and step-down converter;

2 is a functional block diagram depicting a non-inverting buck-boost converter of the present disclosure;

3 is a more detailed block diagram of a non-inverting buck-boost converter providing the present disclosure;

4 is a flow chart depicting the operation of the non-inverting buck-boost converter of FIG. 3;

5a-5c depict waveforms of the buck-boost converter operation when transitioning from a buck mode of operation to a boost mode of operation;

6a-6c depict waveforms of the buck-boost converter operation when transitioning from a boost mode of operation to a step-down mode of operation;

Figure 7 is a functional block diagram of a multi-phase non-inverting buck-boost converter;

Figure 8 is a block diagram of a modulator and driver circuit of the multiphase buck-boost converter;

Figure 9 is a more detailed block diagram of the multiphase non-inverting buck-boost converter with intrinsic current sharing;

Figure 10 is a block diagram showing an outline of the modulator and the driver circuit;

Figure 11 is a schematic diagram of the maximum duty cycle detection and mode selection circuit;

Figure 12 is a diagram showing the operation of a two-phase non-inverting buck-boost converter operating in a buck mode steady state;

Figure 13 is a diagram showing a two-phase non-inverting buck-boost converter operating in a buck mode steady state;

Figure 14 depicts a two-phase non-inverting buck-boost converter operating in a boost mode steady state.

202. . . Buck-boost converter circuit

204. . . Input node

206. . . Output node

208. . . Drive logic

210. . . PWM control logic

212. . . Control compensation logic

214. . . Current sensor

216. . . Mode control logic

Claims (23)

A multi-phase non-inverting buck-boost voltage converter, comprising: a plurality of buck-boost converters, wherein each of the plurality of buck-boost converters and the multi-phase non-inverting buck-boost voltage An additional phase of the converter is associated for generating an adjusted output voltage in response to an input voltage; a plurality of current sensors, wherein each of the plurality of current sensors is current senser And a buck-boost converter coupled to one of the plurality of buck-boost converters for monitoring an input current to the associated buck-boost converter and generating a current sense signal for the associated phase a plurality of buck-boost mode control circuits, wherein each of the buck-boost mode control circuits of the plurality of buck-boost mode control circuits is coupled to an associated buck-boost converter for responding to an error voltage and for The current sense signal of the associated phase controls the associated buck-boost converter to utilize peak current mode control in a buck mode of operation and in a boost operation Using valley current mode control, wherein the plurality of buck-boost mode control circuits provide current balancing between the phases; and a voltage error circuit coupled to the plurality of mode control circuits and the plurality of buck-boosts a converter for generating the error voltage in response to the adjusted output voltage. The multiphase non-inverting buck-boost voltage converter of claim 1, wherein the voltage error circuit further comprises an error for generating the error voltage in response to the adjusted output voltage and a reference voltage Amplifier. The multiphase non-inverting buck-boost voltage converter of claim 1, wherein each of the plurality of buck-boost mode control circuits further comprises: PWM control logic for responding to one a maximum duty cycle detection signal, the error voltage and the current sense signal to generate a buck PWM control signal and a boost PWM control signal; a buck mode control and drive circuit coupled to the PWM control logic, And responsive to the buck PWM control signal and a mode signal to generate a high side buck switching transistor control signal and a low side buck switching transistor control signal; a boost mode control and driving circuit Coupled to the PWM control logic for responsive to the boost PWM control signal and the mode signal to generate a high side boost switch transistor control signal and a low side boost switch transistor control signal; and mode control Logic coupled to the buck mode control and drive circuit and the boost mode control and drive circuit for responding to the buck PWM control signal And the boost PWM control signal to generate the maximum duty cycle detection signal and the mode signal. A multiphase non-inverting buck-boost voltage converter as claimed in claim 3, further comprising a current control compensation circuit for generating a compensation voltage, wherein the compensation voltage is responsive to the mode signal in a first state Generating in response to the monitored input current, a buck mode offset signal, and a buck mode slope compensation signal, and responsive to the A second state mode signal is generated in response to the monitored input current, a boost mode offset signal, and a boost mode slope compensation signal. The multiphase non-inverting buck-boost voltage converter of claim 4, wherein the current control compensation circuit further comprises: a first adder for summing the monitored input current, the buck a mode offset signal and the buck mode slope compensation signal to generate a step-down voltage compensation signal; a second adder for summing the monitored input current, the boost mode offset signal, and the rise Pressing the mode slope compensation signal to generate a boost voltage compensation signal; and a multiplexer for selecting the buck voltage compensation signal or the boost voltage compensation signal as the voltage compensation signal in response to the mode signal. The multiphase non-inverting buck-boost voltage converter of claim 3, wherein the mode control logic further comprises: a maximum duty cycle detecting circuit responsive to the buck PWM control signal and the boosting a PWM control signal to detect a maximum duty cycle condition and generate the maximum duty cycle detection signal; and a mode selection circuit responsive to the maximum duty cycle detection signal and a clock signal to generate the mode Signal, the mode signal indicates the boost mode of operation or the buck mode of operation. The multiphase non-inverting buck-boost voltage converter of claim 3, wherein the mode control logic further comprises: a first control logic for setting a first value in response to a buck PWM control signal or a boost PWM control signal reaching a maximum duty cycle value; and a second control logic responsive to A clock signal outputs the first value as the mode signal. The multiphase non-inverting buck-boost voltage converter of claim 3, wherein each of the plurality of buck-boost converters further comprises: a high side buck switching transistor; a side buck switching transistor; a high side boost switch transistor; and a low side boost switch transistor, wherein in the buck mode of operation, the high side boost switch transistor control a signal and the low side boost switch transistor control signal, the high side boost switch transistor system is turned on and the low side boost switch transistor system is turned off, and responsive to the high side buck switch a transistor control signal and the low side buck switch transistor control signal, the high side buck switching transistor and the low side buck switching cell system are selectively switched, and wherein the boosting operation In the mode, the high side buck switching transistor system is turned on and the low side buck switch is turned on in response to the high side buck switch transistor control signal and the low side buck switch transistor control signal. Crystal system Is turned off, and in response to the high side boost switch transistor control signal and the low side boost switch transistor control signal, the high side The boost switch transistor and the low side boost switch transistor system are selectively switched. The multiphase non-inverting buck-boost voltage converter of claim 4, wherein the PWM control logic further comprises: a PWM comparator for comparing the error voltage with the compensation voltage and responsive to the error voltage And the compensation voltage to generate a first PWM signal; the PWM control logic is configured to generate a second PWM signal and a third PWM signal in response to the first PWM signal and the maximum duty cycle detection signal; a first latch for generating the buck PWM control signal in response to the second PWM signal and a clock signal; and a second latch for responding to the third PWM signal and the The clock signal is used to generate the boost PWM control signal. The multiphase non-inverting buck-boost voltage converter of claim 1, wherein the error voltage supplied to each of the buck-boost mode control circuits of the plurality of buck-boost mode control circuits provides current between the phases balance. A method for controlling a multi-phase non-inverting buck-boost voltage converter, comprising: generating an adjusted output voltage in response to an input voltage of a plurality of buck-boost converters, wherein the plurality of buck-boost conversions Each of the buck-boost converters in the device is associated with an individual phase of the multiphase non-inverting buck-boost voltage converter; Monitoring an input current of each of the buck-boost converters; generating a current sensing signal for each of the buck-boost converters; controlling the response in response to an error voltage and a current sensing signal associated with the buck-boost converter Each buck-boost converter utilizes a peak current mode control in a buck mode of operation and utilizes a valley current mode control in a boost mode of operation; responsive to the error voltage and for each of the buck-boost conversions The current sensing signal of the device balances a plurality of phase currents between the plurality of buck-boost converters. The method of claim 11, further comprising generating the error voltage in response to the adjusted output voltage and a reference voltage. The method of claim 11, wherein the controlling further comprises: responsive to a maximum duty cycle detection signal, the error voltage, and a compensation voltage to generate a buck PWM control signal; and responsive to the buck PWM The control signal and a mode signal are used to generate a high side buck switching transistor control signal and a low side buck switching transistor control signal. The method of claim 11, wherein the controlling in a boost operating mode further comprises: generating a buck PWM control signal in response to a maximum duty cycle detection signal, an error voltage, and a compensation voltage; Responding to the maximum duty cycle detection signal, the error voltage, and The compensation voltage is generated to generate a boost PWM control signal; responsive to the boost PWM control signal and a mode signal to generate a high side boost switch transistor control signal and a low side boost switch transistor control signal; And generating the maximum duty cycle detection signal and the mode signal in response to the buck PWM control signal and the boost PWM control signal. The method of claim 14, further comprising generating the compensation voltage, wherein the compensation voltage includes the monitored input current, a buck mode offset signal in response to the mode signal in a first state And a buck mode slope compensation signal, and in response to the mode signal in a second state, the compensation voltage includes the monitored input current, a boost mode offset signal, and a boost mode slope compensation signal. The method of claim 15, wherein the generating the compensation voltage further comprises: summing the monitored input current, the buck mode offset signal, and the buck mode slope compensation signal to generate a step-down voltage compensation a signal; summing the monitored input current, the boost mode offset signal, and the boost mode slope compensation signal to generate a boost voltage compensation signal; and responsive to being in the first state or the second state The mode signal selects the buck voltage compensation signal or the boost voltage compensation signal as the voltage compensation signal. The method of claim 14, wherein the generating the maximum duty cycle detection signal and the mode signal further comprises: Responding to the buck PWM control signal and the boost PWM control signal to detect a maximum duty cycle condition; generating the maximum duty cycle detection signal in response to the detected maximum duty cycle condition; and responding The signal is detected during the maximum duty cycle and a clock signal is generated to indicate the boost operation mode or the buck operation mode. The method of claim 14, wherein the generating the buck PWM control signal and the boosting the PWM control signal further comprises: comparing the error voltage with the compensation voltage and responding to the error voltage and the compensation voltage to generate a a PWM signal; generating a second PWM signal and a third PWM signal in response to the first PWM signal and the maximum duty cycle detection signal; generating the voltage reduction in response to the second PWM signal and a clock signal a PWM control signal; and responsive to the third PWM signal and the clock signal to generate the boost PWM control signal. The method of claim 13, wherein the controlling further comprises: comparing the error voltage with the compensation voltage and responding to the error voltage and the compensation voltage to generate a first PWM signal; responsive to the first PWM signal and the a maximum duty cycle detection signal to generate a second PWM signal and a third PWM signal; responsive to the second PWM signal and a clock signal to generate the buck a PWM control signal; and responsive to the third PWM signal and the clock signal to generate the boost PWM control signal. The method of claim 11, wherein the balancing further comprises an error voltage associated with a phase of the multiphase non-inverting buck-boost voltage converter and the current sensing for each of the buck-boost converters The signals are compared. A method for controlling a buck-boost voltage converter, comprising: monitoring an input current flowing to a first buck-boost converter of the buck-boost voltage converter; generating a first current in response to the input current Sensing a signal; monitoring an output voltage of the buck-boost voltage converter; generating a compensating voltage signal in response to the output voltage; generating a first plurality of driving signals in response to the compensating voltage signal and the first current sensing signal; Generating the output voltage in response to the first plurality of drive signals and the first current sense signal; monitoring the input current flowing to a second buck-boost converter of the buck-boost voltage converter; responsive to the input current Generating a second current sensing signal; generating a second plurality of driving signals in response to the compensation voltage signal and the second current sensing signal; and responsive to the second plurality of driving signals and the second current sensing signal The output voltage is generated. A method for operating a buck-boost converter in a multi-phase non-inverting buck-boost voltage converter, comprising: operating the buck-boost converter in a first mode; determining a first maximum duty cycle Whether the condition is detected; if the first maximum duty cycle condition has been detected, operating the buck-boost converter in a second mode; determining whether a second maximum duty cycle condition is detected; and if The second largest duty cycle condition has been detected to operate the buck-boost converter in the first mode. The method of claim 22, wherein the first mode is a peak current control mode of operation, the second mode is a valley current control mode of operation, and the determining operation is performed by a mode control logic unit.